VLSI Design - Science topic

Clock skew in VLSI design refers to the variation in arrival times of clock signals at different parts of a chip. This can lead to timing issues and affect overall circuit performance. Understanding its impact and employing effective mitigation strategies is crucial for robust VLSI designs.

Hello Everyone, I want to perform division operation in Verilog - HDL. Please suggest me an algorithm for division in which the clock cycle taken by division operation is independent on input. That is for division of any number a (a can be any number) by b(b can be any number),same number of clock cycle wil be taken by division operation for different set of a and b.  

Recently domain-specific hardware accelerators are getting more popular. While designing them what should be the approach? If anyone can guide me here. As I am a bit confused about the implementation part.

How to calculate the power dissipation for different switching activity in sequential elements?

When we measure voltage across a isolated diode, what will the voltmeter read?

1) 0 V but voltmeter shows a non zero value which is approximately equal to built-in voltage.

2) Built in voltage but if it's the case then why can't we use diode as a voltage source?

PS : I was taught in my bachelors that we get a 0V reading across diode which is the algebraic sum of built in voltage and the voltage across metal(wire)-semiconductor interface.

What is the major difference between the pre-layout and post-layout simulation?

According to the number of Input and outputs ports of the FPGA chip we have, can we add (implement) any number of ethernet (100base) RJ45 and Fibre LC connector to the FPGA? What is the way to do that?

Also how can I also implement the following protocol into the FPGA; DNP3 , GOOSE and MODBUS?

which tools or libraries are using for these protocols on FPGA?

and what is best affordable cheap FPGA development board to buy with Ethernet Rj45 and Fibre LC connector SFP

At schematic level design i need to add bitline capacitances in HSPICE Simulation. preferred model card is PTM.

I am plotting the graphs in MS EXCEL. But after seeing IEEE papers, I noticed that the figures are small with a better clarity. I am wondering if there is any other software that may be used for the same. I know there are many free softwares but which software do you prefer.

When I try to reduce my figure size(plotted in EXCEL), it looks distorted.

Any suggestion will be appreciated.

EDIT (10/10/2022): I have used ORIGIN for the recent papers and the results are quite satisfactory.

Hello All, I am trying to design a simple NAND gate using shared diffusion. I designed the IC but it is not working as expected and I don't know why. If the diffusion regions are far apart then the circuit is working fine. But I want to share the diffusion for eliminating extra diffusion capacitance and to reduce the delay. Any help will be appreciated.

I am using C5N technology and I have attached my design as zip and the schematic.

I am a masters student and cannot access college amenities (HSPICE) now due to lockdown. I have to finish my minor project on CNTFET. Can you please suggest me a way to do that ASAP?

Thank you.

It is evident that dynamic tspc flip flop is more power hungry than the its static counterpart, but is more fast. If the design is required for high speed application (clock freq in ~GHz), then which one is better.

VA A Gnd PULSE (0 vdd 2ns 100ps 100ps 5ns 10ns)

.

.

.

.measure tran delay_ar TRIG v(A) val='Supply*0.5' td=1ns rise=3

+ TARG v(out) val='Supply*0.5' fall=3

What's wrong?

I don’t think that the textbook scaling equations can be used for fair comparisons for recent nodes.

in FPGA or VLSI design, How can, identified short path problem and corrections.

I am an Mtech final year student. My interest research fields are semiconductor devices, VLSI Designs and FinFETs. Recently, I joined Intel Corporation as an structural design intern for my final year. For the past two months as an intern, I learnt and trained in Synopsys Fusion Compiler. I am just starting to join the one year intern and I have more to learn. My original goal is to do PhD in the above research field. My real intention to join this intern is to get the industrial knowledge on VLSI Design as Engineering research requires both theoretical and industial experience. So, my question is, will this intern be worth for my PhD? Will working in Synopsys help my knowledge on Semiconductor research?

ASIC technology progressively decreases their standard voltage from 5 to 3.3 to 2.5 to 1.8V ...

However, at the same times, the analogue signals stay at a level of about 1V at the input of ADC, and even larger for some analogue applications. Moreover, keeping high linearity performances in amplifier, analog buffer and other analogue processing, is not realy compatible with low voltage power supply.

Foundries "sale" VLSI/ASIC CMOS and BiCMOS technology exhibiting a recommended power supply.

Have you some recommendations or examples of mixed-designs applications using low-voltage ASIC technology with higher voltage supply for part of the design. For example, a mixed ASIC made of 2.5V ASIC technology biasing under 5V one of the last stages of an amplifier design (while satisfying the maximum breakdown voltage recommendations Vds, Vgs, Vce ...)?

Hi, Does anybody explain the use of multiple valued logic in cmos vlsi design?

I am trying to simulate the deposition of Silicon over SiO2. In reality, when we try to deposit a crystalline Silicon over SiO2 (amorphous), we get rather a polycrystalline Silicon. In ATHENA though, when simulating the same process, the final deposited Silicon layer is not Polycrystalline Silicon but Crystalline silicon.

So, If someone can help me know how to capture this effect in Silicon and how to measure the quality of the deposited film in the Silvaco ATHENA TCAD tool, it would be really helpful.

If the proper simulation is not possible in ATHENA, please let me know which tool can capture these effects properly.

A book or some set materials are not even close to enough for CMOS Layout design. But to start with, I require a good book and some relevant materials. I have done the layouts of some basic static CMOS circuits. Now it is the time to make the layout of the design I am working with (an architecture of ternary CAM with some control and gating circuitry).

Which books or materials I can refer for an optimised layout? I am going to use virtuoso layout suite for the design.     

how to transform a parameter of one technology to another technology in VLSI design? if we know the value delay and power in 180 nm technology how to calculate power and delay in 90 nm manually?

Hi everyone, I don't under this layout figure (5.c) in pic attached .

This is a screenshot from research paper in this link:- https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=7573442

My basic Curiosity is that layout are generally in shape of squares and rectangles, but in this layout what is that blot (ink drop) like thing in fig 5.c

TO GET MORE UNDERSTANDING ABOUT VLSI DESIGN

I am searching for a good topic in Dynamic RAM for my research practice/project in VLSI Design domain. I want to work on outer peripheral circuitry for low power applications (Not into device level i.e structure and composition ).

Designing an analog only CMOS IC (RFIC sub 25GHz) with exact same function on various nano-meter technologies. Will it be just a difference in size and cost? Would it depend on the circuit function?

Similarly what will be the right MMIC process for MMIC sub 25 GHz, 0.5mm phemt or 0.15mm phemt? Will it be just a difference in size and cost? Would it depend on the circuit function?

This is a question without a single answer, since there are many variables and dependencies here which are impossible to pin down, and will change according to design parameters, technology generation/features, logic/circuit design methodologies and capabilities, and (very importantly) the design of the memory hierarchy, and the workload(s) under consideration. Even the basic metrics (power, and performance) are subject to much discussion: how should one trade off power vs performance to make a "fair" comparison? Nonetheless, it would be interesting to hear folks' opinions and analysis on this topic. To start things off, let's assume that you need to meet a certain ("relatively high") performance level, measured as performance per thread in a multi-core/multi-threaded microprocessor, but you are also subject to a per-thread power constraint (typical of today's high-performance processors). Obviously, the deeper the pipeline, the higher the operating frequency. Or, frequency can be traded off for power, by lowering the operating voltage. However, lowering the design FO4 and deepening the pipeline will impact the power-performance of the design in a variety of ways:

1) Number of flops in the design increases, driving up power, especially power used for clocking. Also, the delay overhead of the flop and any clock uncertainty takes a relatively larger bite out of the cycle time.

2) "Design difficulty" increases since logic has to be divided more finely to achieve the higher cycle time. Also increased timing/device modeling accuracy is called for. Tighter signal slews will be required, and number of repeaters/buffers will increase.

3) CPI will increase, since miss penalties (measured in numbers of cycles) will increase. Also, in light of #2, the design may be pushed towards a simpler microarchitecture.

4) There may be many other costs, depending on the design, ranging from SER impacts, power/current density issues, cache design issues, etc.

I'll start by suggesting that, given where most commercial designs seem to be landing, that 10FO4 is probably well below the ideal cycle time (despite considerable literature which might suggest otherwise). Also, something like 50FO4 is probably too high. Comments anyone?

sir ,

I am final year student of mtech vlsi design and looking for topic of thesis in front end .

please suggest some good topic .

Even though the accuracy matters, I would like to know whether this can be done for all designs?

In VLSI design software such as cadence how can we calculate the delay between two different outputs and delay between input and output?

Many work in VLSI area, it is mentioned about iso-area concept. What it meant by?

Thanks in advance

What are the circuits that consumes high power  in both analog and digital systems .

I would like to have some knowledge sharing on power budget estimation at top level.

Basically as a block level pd engineer I have been given a power budget(say 200mW) and allowable drop threshold (say 6%). I have some rough idea on how do they arrive it, but how do they freeze those values early in the design flow for a block at top level? It would be helpful if you can share some knowledge on this.

body biasing techniques is used for low power cmos desgin 

how to calculate the maximum source to bulk voltage before latch up problem occurs .

Actually, what happen in Indian Universities most of the institutes teach Semi Custom VLSI design (VHDL) for the name sake of VLSI design. They  don't have fabrication facility  even for demo. Due to which students have only theoretical knowledge which i think, insufficient for engineering UG or PG students

Please suggest reputed journals for the same. Whether the result of Tanner V16 is accepted by the sci journals?

IIL=Integrated injection logic

I need best partitioning algorithm which is present in the latest VLSI design tools. Which algorithm does it?

I have seen in almost all processor, L2 cache associativity is some power of 2 (L1 is generally direct mapped  or some low power of 2). Although in Alpha 21164 super-scalar processor L2 cache (96KB) was 3-way set associative. Which doctrine had convinced the architect of alpha 21164 processor to not to have the associativity some power of 2 ? 

How does absence of clock help lessen the effects of EM ? 

With referring to the topic below

I have been trying since last few days to design a modified radix 4 booth multiplier. I want to implement compressors, so as to reduce the delay while adding the partial products. But, I am facing a great deal of difficulty in understanding the sign extension. If I use the conventional method of sign extension, hardware will become quite large and in turn will increase the delay of the system. I have tried looking up on google, but the method that has been described doesn't seem to work. Does anyone know a proven and an efficient scheme that will reduce the delay of the system and will work alongside the compressors and parallel prefix adder?

I am trying to see what is the easiest way to export the MLC positions from individual control points from a Pinnacle VMAT plan. Can this information be embedded in a Dicom RT file?

can anyone please give me some useful link where I can find a complete solved example of "2 bit common subexpression elimination in MCM" method-as proposed by mahesh mahendale in Synthesis of Multiplierless FIR Filters using minimum number of adders.

If possible, please provide me a way to solve this matrix using steps (as proposed by the above paper). 

Looking for kind help.

Dwaipayan.

How and why CMOS VLSI DESIGN  consumes less power and VLSI DESIGN consumes more power ?Scaling is possible both in cmos vlsi and vlsi than why we go for cmos vlsi ?what is the most importance difference and advantage in cmos vlsi with proper reason. Expalin?If low power why and how?

Is there something that we can do in cmos vlsi that we cant do in simple Vlsi design?Is there any differences in scaling properties of both?

If we tell die area reduction that we can also do in vlsi because scaling is possible.

nmos and pmos together gives low power

but if we put anyone it consumes more power why and how?

can anyone let me know about clock gating technique used in low power cmos vlsi design?

Hello Everyone,

In the circuit (see attachment), when at the gate of the NMOS, 0 volt is given, in this condition the NMOS should be in OFF state and no current shold flow through NMOS then why i am getting the High output at the source terminal.

Note : Net 6 is the input at gate terminal and net 4 at drain terminal.

VHDl code for UART is somewhat lengthy using state machine ,so i am thinking to implement it without state machine .is it best??

We visualize, quantify and optimize the facilities layout (see http://www.amia-systems.com)

Our next challenge will be to position, physically, items in complex graph with valued edges.

We made some research and didn't find relevant publications concerning this topic. 

Could you refer us to some publications?

I am at your disposal if you need further information,

Abdelkrim

HI,

Good Day to all...

In digital design, i want to insert control logic or lock mechanism at internal nets. As far as i know, inserting control logic or lock mechanism at High fan-out nets is the best solution in which less no. of locks will have controllability on more no. of internal nodes.

I want to know is there any other net (means any other digital parameter to decide in which net i can insert) if i insert will impact more no. of logic, especially my concern is to increase controllability of output ports. But, fan-in will not help me for this purpose i hope...

Thank you in advance....

Regards,

SUMATHI G.

Hi all,

I would like to know if someone know the data from a white paper/report/research paper about

-> SoftErrors: Failure in Time (FIT) rate (neutron/meoun/proton etc.) for some Flip-Flops which are based on FinFET and/or FDSOI technologies. As there are few papers available on SRAM FinFET FIT rate. Furthermore, there are few papers on CMOS FIT rate for flip flops are also available.

Thanks.

In Signal flow graph based VLSI design research paper, the term cut set retiming present. What it mean the technical term “cut set retiming” in VLSI Design?

plz send me any paper aboute VLSI Design in Wireless Sensor Network

I want to measure the frequency of ring oscillator circuit I inserted in my design. I made circuit schematic using xilinx ISE. During behavioral simulation, my circuit is switching its output, but I could not see its waveform. Hence I could not measure its delay i.e. frequency.

When I select the mode of simulation as post-route, it shows my design is not yet instantiated (question mark near design), when I try to instantiate, its not doing so. Finally I could not measure ring oscillator frequency.

In low power VLSI design clock gating technique will reduce power all time or it depends upon the input date? Is any chance, the computation power may increase?

Please explain the difference between body effect and body bias.

Hello

I have few quires about modelling NBTI Trapping/Detrapping Model Based on Predictive Technology Model (PTMs) firstly for CMOS and then FinFETs for smaller tech. nodes such as 16nm/22nm/32nm/45nm.

Q1: What material PTM (CMOS and FinFETs) models used for Gate-Oxide (e.g. Aluminium oxide Al₂O₃ or Hafnium oxide HfO₂ etc...)?

Q2: Based on above material, what is the typical trap density (i.e. number of traps/cm^2) for 16nm/22nm/32nm/45nm PTMs?

Q3: What is the typical Activation Energy (Ea) value for trapped charge emission? and what is its' range?

Thank you.

Usman

VLSI Design

I have implemented 4-bit adders (Ripple carry and carry look ahead adder) on VHDL (Xilinx ISE design suit). How can I measure speed and power of both the designs for comparison?

How to take Dynamic power and switching power report using design complier or prime time synopsys tool?

 Respected  all.

Please  explain me little bit  about, " Green transistor"?

Is there any simulation tool available to check that the proposed IC design would work in all kind of environments, including space? I want to check the effect of radiation on the chips that we use in space satellites.

Hi all,

I am new to monte carlo analysis features and I am unable to interpret results from that simulation in cadence. I have designed band-gap current reference and I want to know how the resultant current varies with process and mismatch. Can anyone tell me why I am not getting Gaussian distribution curve for the resulted current (figure is attached in pdf for 2 different cases)? These are the procedure I followed:

Set-up: I opened Montecarlo → selected, sampling method to Random --> Number of points to 500 → save process and mismatch data → run nominal simulation → all instances are selected in specify instances - > ok.

Case 1: Temperature is not varied, only DC operating save option is selected in analysis for MC. It is shown in bottom figure in pdf, where 497 samples are concentrated at only one point. Its mean is showing to be 1.18uA where 'nom' is designed for the current of 1.050uA at 27 Deg C. Why Gaussian plot isn't appearing?

Case 2: Temperature range is selected from -10 to 100 Deg C in analysis option in ADE for the MC run. Its mean is showing as 1.1uA (top figure in pdf). Here 499 samples are concentrated at one point. Here again why Gaussian response isn't appearing and different samples are taken at which temperature (as I varied temp from -10 to 100Deg C)?

For the preparation of manuscript I need a good software for drawing some circuits and graphs. The graphs I have created using ORIGINPRO. Mainly I am going to use some basic shapes, MOSFETs, Logic gates and texts in the circuit drawing. What is the best software for drawing these circuits which produces high resolution images in all formats with clear edges. 

I'm trying to implement a current starved VCO in both 50n and 1u technology (using LTSpice).

It works for 50n but not 1u.

Is there anything I'm leaving out?

Dear all,

This is a very general question regarding planar CMOS Bulk production. As we all know that due to lots of problems in terms of Reliable Design in the presence of Power, Speed for CMOS bulk. I was wondering if there is any company still doing production of ICs with planar bulk CMOS below let say 32nm?

Usman

Due to the design complexity and integration density of the device components, interconnect centric layout design has become an inevitable part to the physical design engineers. Increase in integration density as well as faster switching induces more power consumption i.e. power density resulting need for faster heat dissipation. Generation of heat increases temperature affecting reliability of the chip as an effect of electromigration. In what other ways the chip design gets affected in this scenario due to thermal effects?

According to them, only area and speed are the two crucial factors while evaluating performance of any such circuits. Why so? Though I understand the importance of speed of operation and area  for any digital circuits, should the word "PERFORMANCE" only depicts speed and area information?

We would like to fabricate an IC which includes various students' research works in TSMC90nm Technology. I have two option, 1)MOSIS 2)IMEC, Which choice would be preferred?

What will be the approximate cost?

There are many research papers on process variations  and aging affects on CMOS and FinFETs. However, I would like to have an opinion on this forum about what are the significant process parameters which can affect the circuit reliability? In my opinion: Fill in the blanks with your valuable comments:

For CMOS Process Parameters: TOXE, Leff, Weff and ___,___,___?

For FinFETs Process Parameters: TOXE, Lg, HFIN, TFIN, PHIG and ___,____,_____?

If the above are wrong in your opinion please comment on them as well.

Thank you.

I have done sensitivity analysis using ADEL in Cadence virtuoso for my design for ac and dc base. I have attached some part of the result of sensitivity analysis for ac base .What does this result show?

Whilst doing RCX an error occured, (please see attached). Can anyone help with this?

Using the Calculator in Visualization and Analysis in Cadence Virtuoso Avg. Power, Static Power, Peak power and Energy Can be calculated. I am unable to calculate the correct dynamic power. What are the process I need to follow prior to run the simulation and after it? 

I am learning basic designs using Cadence Virtuoso. I have Learned up to Schematic, Layout Design, Parasitic extraction of Combinational Circuits. The Build in Libraries present are the technology libraries gpdk(180/90/45), analoglib, samples etc.

I have used Schematic-driven layout. What extra libraries I need for TAPEOUT?

Is it possible to determine all the leakage currents (from all sources) in digital subsystems at logic level? If the answer is no, then what about circuit level? list out the possible tools to work on power optimization at circuit level? 

Can anyone help me to write testbench with varying input probability for unsigned multiplier design, which include .tcf file generation for power calculation

Normally we will perform both STA and DTA at GLN level. However, in general, STA is preferred in the back-end process. Is it necessary to do DTA again after completing the routing process.

I am using SPARTRAN XC3S50 PQG208EGQ1117 D4238638A 4C FPGA for synthesis and simulation process. Where will the speed of the circuit be shown?

Optoelectronics-VLSI technology is inherently a multi-disciplinary field. The building of systems require the gathering of experts such as optical hardware designers, opto-mechanics engineers, semiconductor (optoelectronic) manufacturers, system architects, computer scientists, VLSI circuit designers in the digital and analogue domains, specialists in hybrid integration, assembly engineers, packaging and testing engineers. Research groups tend consequently to be very large and to have sufficient resources for the fabrication of prototypes.