Shengdong Hu's research while affiliated with Chongqing University and other places

What is this page?

This page lists the scientific contributions of an author, who either does not have a ResearchGate profile, or has not yet added these contributions to their profile.

It was automatically created by ResearchGate to create a record of this author's body of work. We create such pages to advance our goal of creating and maintaining the most comprehensive scientific repository possible. In doing so, we process publicly available (personal) data relating to the author as a member of the scientific community.

If you're a ResearchGate member, you can follow this page to keep up with this author's work.

If you are this author, and you don't want us to display this page anymore, please let us know.

Publications (1)

Cross‐sectional views of the MOSFETs (a) C‐TMOS, (b) HJD‐TMOS, (c) Band diagram along line AA' for the HJD structure in the interface of the P‐poly and the CSL
Static simulation results (a) The BV (Vgs = 0 V) and, (b) The Ron (Vgs = 15 V), the VF (Vgs = −5 V) and the VPN for the HJD‐TMOS
BVs and the electric field distributions of the C‐TMOS and the HJD‐TMOS at the Vds of 650 V (a) BVs, (b) The electric field distribution of the C‐TMOS, (c) The electric field distribution of the HJD‐TMOS
First‐ and third‐quadrant I‐V characteristics of the C‐TMOS and the HJD‐TMOS at the gate voltage (Vgs) of 15 and −5 V, respectively (a) The forward I‐V and reverse conduction characteristics of the C‐TMOS and HJD‐TMOS at Vgs = 15 and −5 V, respectively, (b) The IdsH as a function of the Vds; (c) The Ids as a function of the Vds The active area of each device is 1 cm²
Gate charge test of the C‐TMOS and the HJD‐TMOS. The insert picture is test circuit

+3

A SiC Trench MOSFET with Heterojunction Junction Diode for Low Switching Loss and High Short Circuit Capability
  • Article
  • Publisher preview available

June 2019

·

89 Reads

·

10 Citations

IET Power Electronics

IET Power Electronics

Junjie An

·

Shengdong Hu

A SiC trench MOSFET with a merged heterojunction diode is proposed and numerically analysed here. The merged heterojunction diode can effectively suppress the turn‐on of the parasitic body diode in the proposed SiC trench MOSFET. In addition, a P + shield layer surrounding the gate oxide layer can dramatically alleviate the gate oxide corner from the concentration of the electric field and improve the static and dynamic performances of the proposed device. As a result, not only the breakdown voltage is increased by 24% but also the miller charge and the switching losses of the proposed structure are reduced by 43 and 48.6%, respectively, when compared with those of the conventional SiC trench MOSFET with a grounded P + shield layer. Moreover, the short‐circuit capability and its failure mechanism are numerically studied for the proposed structure. Finally, a feasible fabrication procedure is provided to realise the fabrication of this new device.

View access options
Share

Citations (1)

... Silicon carbide (SiC) material, known for its wide bandgap, high critical breakdown electric field strength and high thermal conductivity, replaces silicon as a new generation power semiconductor material [1][2][3]. The 4H-SiC trench MOSFET (TMOS) has gained significant attention as an emerging power semiconductor device with advantages such as high breakdown voltage (BV), high current capacity, and fast switching speed, which made it widely employed in power-integrated circuits [4][5][6][7][8]. ...

Reference:

Investigations of 4H‐SiC trench MOSFET with integrated high‐K deep trench and gate dielectric
A SiC Trench MOSFET with Heterojunction Junction Diode for Low Switching Loss and High Short Circuit Capability
IET Power Electronics

IET Power Electronics

Junjie An

·

Shengdong Hu