S Geetha's scientific contributions

What is this page?
This page lists the scientific contributions of an author, who either does not have a ResearchGate profile, or has not yet added these contributions to their profile.

It was automatically created by ResearchGate to create a record of this author's body of work. We create such pages to advance our goal of creating and maintaining the most comprehensive scientific repository possible. In doing so, we process publicly available (personal) data relating to the author as a member of the scientific community.

If you're a ResearchGate member, you can follow this page to keep up with this author's work.

If you are this author, and you don't want us to display this page anymore, please let us know.

Publications (2)

Figure 2. Gated VDD SRAM cell
Figure 4. MTCMOS SRAM Cell array of data storage on row and column...
Figure 5. Conventional 6T Cell simulation
Comparison of Various Parameters
Design and Analysis of Low Power MTCMOS using SRAM cell
Article
Full-text available
  • Mar 2019
A rapid growth of portable battery operated devices has made low power IC design a priority in recent years. Conventional SRAM cell designs are power hungry and poor performers in this new fast mobile computing. In this paper, low power SRAM cell designs have been analyzed for power consumption and write power delay. Gated VDD and MTCMOS design tec...
Cite
Download full-text
Fig.3.3 (a)Write ability yields of read-decoupled SRAM cells. (b) WWTVs...
1 Comparative analysis on various static random access memory architectures
Survey on Static Random Access Memory
Article
Full-text available
  • Apr 2018
This paper presents an extensive summary of the latest developments in low power circuit techniques and methods for static random access (SRAM) memories. SRAM has been a major component in many VLSI chips due to their large storage density and small access time. It has become the topic of substantial research due to the rapid development for low po...
Cite
Download full-text

Citations

... 6T based SRAM cell and array designing is discussed using Low power reducing techniques such as gated VDD and MTCMOS (1) . Design of 6T, 8T, and 9T based SRAM is carried using MTCMOS technique in (2) . ...
Reference: Analysis of 7T SRAM Cell Based on MTCMOS, SVL and I-SVL Technique
View full-text