Raj N. Master's research while affiliated with Mountain View College and other places
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Publications (35)
Non-uniform power distribution, increased die-size, and multiple-chip modules present new challenges for the thermal management of modern integrated circuit (IC) packages. Thermal characterization techniques capable of resolving partial thermal resistances at the component level have received increased emphasis in development of advanced packaging...
In flip chip microelectronic packages, solder bumps are used to connect the silicon die and package substrate for electrical functionality. However, due to the large mismatch of silicon and organic package in the coefficient of thermal expansion (CTE), the solder bumps undergo large viscoplastic deformation in temperature cycling test and in field...
In flip chip microelectronic packages, solder bumps are used to connect the silicon die and package substrate for electrical functionality. However, due to the large mismatch of silicon and organic package in the coefficient of thermal expansion (CTE), the solder bumps undergo large viscoplastic deformation in temperature cycling test and in field...
The advanced flip-chip-in-package (FCIP) process technology, using no-flow underfill material for high I/O density (over 3000 I/O) and fine-pitch (down to 150 mum) interconnect applications, presents challenges for flip chip processing because underfill void formation during reflow drives interconnect yield down and degrades reliability. In spite o...
Optimal thermal design of high-power electronic components often requires use of solder-type thermal interface materials. Pure indium solder provides best combination of mechanical and thermo-mechanical properties for efficient thermal design. Two indium TIM assembly approaches were investigated: pre-attach approach and preform approach. Pre-attach...
The advanced flip chip in package (FCIP) process using no-flow underfill material for high I/O density and fine-pitch interconnect applications presents challenges for an assembly process that must achieve high electrical interconnect yield and high reliability performance. With respect to high reliability, the voids formed in the underfill between...
This paper studied the factors causing adhesion failure between lid and adhesive. Adhesive curing mechanism has been experimentally investigated in combination of surface behaviour analysis on lid by using FTIR and XPS. The results showed residue on lid surface caused by low water rinse flow can affect the curing condition.
This paper presents a study done on the orientation of C4 solder bumps with respect to bulk silicon (Si) in transmission electron microscopy (TEM). The research found that when a sample comprising both controlled-collapse-chip-connection (C4) solder and Si was oriented with respect to a known zone axis of Si, the orientation of the C4 solder grains...
This paper studied the factors of causing adhesion failure between lid and adhesive. Adhesive curing mechanism has been experimentally investigated in combination of surface behaviour analysis on lid by using FTIR and XPS. The results showed residue on lid surface caused by low water rinse flow can affect the curing condition.
As the demand for computing performance and density increases, the demand for packaging microprocessors is getting more complex. Computing speed and increased functionalities are achieved by reducing lithography features and increasing no. of transistors and no. metal layers. The performance is further enhanced by incorporating low K dielectric fil...
In flip-chip package, the mismatch of thermal expansion coefficients between the silicon die, copper heat spreader and packaging substrate induces concentrated stress field around the edges and corners of silicon die during assembly, testing and services. The concentrated stresses result in delamination on various interfaces involving a range of le...
With the increasing connection density of ICs, the bump pitch is growing smaller and smaller. The limitations of the conventional solder bumps are becoming more and more obvious due to the spherical geometry of the solder bumps. A novel interconnect structure - copper pillar bump with the structure of a non-reflowable copper pillar and a reflowable...
Lid or heat spreader in flip chip packages has become a vital component for high performance and high power IC applications. While mechanics and reliability of flip chip packages have been extensively investigated in the last decade, majority of the research was focused on the packages without lid. Hence, we still lack of fundamental understanding...
Efficient heat dissipation is a major challenge for the packaging of high power microprocessors. This paper discusses a novel lid assembly process and characterization techniques that were successfully developed for a high power microprocessor in high volume production. For a high power microprocessor flip chip organic package with under fill, die...
The application of no-flow underfills for high IO density, fine-pitch, flip chip in package (FCIP) applications is analyzed. A number of commercially developed no flow underfills are evaluated. Process parameters for improved assembly yields depend strongly on the underfill materials characteristics and particularly the reflow profile. The test veh...
Voids in flip chip packaging of organic land grid array (OLGA) caused by the inclusion of air, other gases and moisture were studied and experiments were designed to understand the cause of void formation. Reactions among the solder mask, flux residue, underfill and solder bump were investigated to understand the mechanism of voids formation during...
As technology continues to scale, there is increasing demands on I/O counts and power requirements, leading to decreasing solder pitch and increasing current density for solder bumps in high-density flip-chip packages. At the same time, increasing performance requirements has led to the use of organic packages instead of the conventional ceramic pa...
Chip-package-interaction (CPI) induced BEoL (back-end-of-line) delamination has emerged as a major reliability concern with the adoption of Cu/low-k as the mainstream BEoL technology. To study the dependence of Cu/low-k delamination on package underfill material properties and BEoL stack up configuration, a multi-level finite element analysis model...
This paper investigated the factors to cause the formation of underfill voids during dispense and cure of underfill in the flip chip technique. The extrusion mechanism of solder bump has been studied in detail. The experimental results show that additional interim-cure processing is an effective way to eliminate ring voids.
![Fig. 1. Interface toughness versus mode mixity [1].](profile/Richard-Blish/publication/3430015/figure/fig1/AS:662575800913920@1534981789661/Interface-toughness-versus-mode-mixity-1_Q320.jpg)
A generalized plane strain condition is assumed for an edge interfacial crack between die passivation and underfill on an organic substrate flip chip package. C4 solder bumps are explicitly modeled. Temperature excursions are treated as loading conditions. The design factors studied include underfill elastic modulus, underfill coefficient of therma...
The integration of several passives into a single component is essential to keep them in the vicinity of the microprocessor, and their reliability becomes critical for the overall robustness of the product. This paper uses both modeling and experimental approaches to address design/process optimization for a resistor pack (R-pack, also known as chi...
A generalized plane strain condition was assumed for an edge interfacial crack between die passivation and underfill. for an organic substrate flip chip package. C4 solder bumps are explicitly modeled. Temperature excursion is applied as loading condition. The design factors studied include underfill modulus, underfill coefficient of thermal expans...
With increasing applications of thin multi-layer flip chip packages with complex interweaving layout, the difficulties and ineffectiveness of fault isolation with current nondestructive techniques such as RTX (real time X-ray) and SAM (scanning acoustic microscopy) have increased significantly. TDR (time domain reflectometry) and scanning SQUID (su...
In this paper, we describe a new approach and a new system developed for EM tests of solder balls in a packaging assembly. The approach was based on the Wheatstone bridge method, which provided significant improvement in the sensitivity for detecting EM damage in solder balls. In the bridge circuit, each of the arms can contain an ensemble of solde...
Jet fluxing can offer precise, accurate weight flux deposition for flip chip, ball grid array and ceramic grid array packages.
We will describe the kinetics and mechanism of degradation of flip
chip bumps when subjected to overly agressive High Temperature
Operational Life tests. Higher temperature is used to shorten the
qualification time. Flip Chip bumps degrade when the temperature of the
HTOL test exceeds 155 deg.C. The result of this degradation is
electrical opens. T...
In many applications today involving flip chip, ball grid array
and column grid array technologies; flux application is an important
process parameter. Dispensing flux requires reproducibility of dispense
weight so that amount of flux residue can be controlled. Flux residue
causes defects such as voids and delamination when flip chip is
underfilled...
A new high volume application using jet fluxer is described. This fluxing application is intended for flip chip, ball grid array and column grid array applications. The process has been implemented in high volume production successfully for both flip chip and column grid array applications.
AMD's heat spreader attach process utilizes a thermally conductive
silicone adhesive which can be quickly and easily dispensed and cured.
The heat spreader attach assembly process eliminates the need for gross
leak testing (a.k.a, bubble testing), an expensive and time consuming
test and reduces the capital equipment required while increasing
produ...
Current desktop and consumer applications for microprocessors
require that systems be Energy Star compliant. In addition, other power
management initiatives such as Advanced Configuration and Power
Interface (ACPI) define low power system states that the operating
system controls. These initiatives are directed at reducing the energy
consumption of...
Flip-chip technology in the form of Controlled Collapse Connection
(C4) was adopted for the AMD K6 microprocessor. The need arose from the
pad limitations of wire-bond technology. The necessity of more pads for
connectivity resulted in growth of die size. This would have impacted
the net die per wafer and, therefore, the capacity of the wafer
fabri...
Reliability of ceramic ball grid arrays has been reported in
previous studies. These studies were carried out with respect to the
body size and assembly parameters. This paper will report on reliability
of a relatively thin package (<1 mm) in a daughter card format. This
format is typical of many mobile personal computers. In addition, we
will desc...
Ceramic Column Grid Array (CCGA) technology was introduced by IBM
several years ago. The purpose of the Column Grid Array (CGA) technology
was its improved reliability compared to the Ball Grid Array due to
height and compliance. This paper describes several process improvements
in fabricating the columns onto the substrates. These improvement's
in...
Citations
... [1], [2] It is well known that by increasing the standoff height, the solder fatigue life underneath the termination can be increased. [3] However, there is still controversy about calculating the solder fatigue life at the fillet portion. [1], [4] In recent years, the surface evolver was adopted to predict a more realistic solder shape, so that a more accurate solder fatigue life can be acquired/obtained. ...
... The first term, F , in (12) represents the data fidelity, which keeps the consistency between the data predicted by the model and the measured data. The second term, ℓ 1 -regularization term G, is sparsity-promoting, so that we expect that the obtained constant spectrum R(·) will be zero apart from narrow peaks around ln τ i , see (4). In this way, the proposed method is able to improve the resolution over the standard NID method. ...
... In the analysis that follows the role of one important characteristic of the USCB is addressed: the glass transition temperature (T g ) of the underfill epoxy [28][29][30]. Below T g the epoxy is in a hard (glassy) state. Above the T g it transitions to a rubbery state and, as a result, the material's modulus decreases and its CTE increases. ...
... More than 50% of electronics failure is connected to temperature management [5], and higher temperature ranges induce higher thermomechanical stresses caused by the coefficient of thermal expansion (CTE) mismatch between components [6]. In order to improve heat removal, heat spreaders in the form of lid have been extensively employed in the industry for flip-chip applications [7]. The lid is usually attached do the silicon die via a thermal interface material (TIM) and M. Bagetti Jeronimo et al. on package reliability, as well as underfill failure modes can be found in [21][22][23][24][25][26][27]. ...
... One stress test on a DUT accompanies four individual in-situ monitored delamination experiments at two different loading conditions. No additional effort is required for time-intensive analyses after a stress test by means of SAM [63] or FIB. Fourth, by its layout, the delamination sensor is given the characteristics of being local and self-calibrating. ...
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... In some earlier works, effect of performance because of clock jitter has been shown [14,15]. Using proper packaging technology, including decoupling capacitor, using of LDOs are popular technique to deal with the issue [16,17]. ...
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... Accordingly, In was a potential material candidate for low-temperature SLID bonding and thermal interface MPa [7], which were comparable with the strengths of Cu/Sn interconnects [9]. Accordingly, In was a potential material candidate for low-temperature SLID bonding and thermal interface materials [10][11][12][13][14]. Fundamental information on the interfacial reactions between In and Cu is crucial for evaluating the feasibility of In solder. ...
... Void formation of the no-flow underfill was traced using image processing tools in Matlab software to get a precise value of void formation percentage [29]. The image of the complete process of no-flow underfill was first captured from Ansys Fluent software. ...
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... By neglecting the radiation, FPCB would have a lower board-level temperature due to non-uniform heat distribution compared to the ambient. A similar finding on overshoot temperature was reported by Zhang et al. [42]. ...
... But it presented several problems when use solvent-filled flux as the solvent is quickly to evaporate, and is become inapplicable as the film become thinner and less area. An optic flux thickness measure method using a unique dual-light interferometer is developing [6]. But it still has not good means to measure fluid in a groove quantitative. ...
