P.K. Tan's research while affiliated with GlobalFoundries Inc. and other places
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Publications (60)
The continuous growth and advancements of semiconductor devices for automotive applications and internet-of-things drive the demand and scaling of embedded non-volatile memories (eNVM). Existing eNVM landscape in 40 nm and 28 nm advanced processes is dominated by split-gate flash memory devices (Do, 2016) where inter-poly oxide (IPO) defect is one...
The global radio frequency (RF) semiconductor market size is growing dramatically in recent years, especially with the growing demand for mobile devices, communication networks, automotive applications, etc. Failure analysis (FA) on RF devices is normally more complex than digital devices, especially when it involves soft failure. This paper discus...
Gate oxide breakdown has always been a critical reliability issue in Complementary Metal-Oxide-Silicon (CMOS) devices. Pinhole analysis is one of the commonly use failure analysis (FA) technique to analysis Gate oxide breakdown issue. However, in order to have a better understanding of the root cause and mechanism, a defect physically without any d...
Passive voltage contrast (PVC) is widely used to detect underlying connectivity issues between metals based on the brightness of upper metals using scanning electron microscopy (SEM) or focused ion beam (FIB). [1] However, it cannot be applied in all cases due to the uniqueness of each case where brightness alone is insufficient to tell leakage loc...
Reliability tests, such as Time-Dependent Dielectric Breakdown (TDDB), High-Temperature Operating Life (HTOL), Hot Carrier Injection (HCI), etc., is required for the lifetime prediction of an integrated circuit (IC) product. Those reliability tests are more stringent and complex especially for automotive Complementary Metal–Oxide–Semiconductor (CMO...
Non-volatile memory is the most important memory device in IC chips. As a memory, embedded non-volatile memory (NVM) is a fundamental structure in many kinds of semiconductor devices. It is commonly used in the modern electrical appliance as a code or data memory. For different applications, there are different memory designs or IP, like ROM, OTP,...
Electrostatic Discharge (ESD) is an important area for the semiconductor industry because ESD has an impact on production yield and product quality. ESD problems are increasing and have become challenging in the semiconductor industry because of the trends toward higher speed and shrinking in technology node. By continually shrinking the transistor...
Integrated circuit (IC) reliability failure at field presents significant cost to both manufacturer and consumer. This paper targets reliability issue due to IC design weakness, presenting a case of 28 nm Input/Output (I/O) circuit reliability failure, and shows a complete work flow, starting from root cause identification using Final Test (FT) and...
Cross-sectional sample preparation is one of the most important failure analysis (FA) techniques in the semiconductor industry. It was commonly used for film stack critical dimension measurement, defect identification, electrical fault isolation and etc. However, cross-sectional sample preparation to a specific target location on a sub-micron devic...
Using in situ transmission electron microscopy (TEM), we studied boron diffusion and segregation in CoFeB/SiO2 nanostructured thin film stacks. We also investigated how these phenomena affected the phase and microstructure of CoFeB thin films under electron beam irradiation at 300 kV. A unique phase transformation was observed in CoFeB thin films u...
Cross-sectional analysis is one of the important areas for physical failure analysis. Focus Ion Beam (FIB) and mechanical polish sample preparation are commonly used and necessary techniques in the semiconductor industry and Failure Analysis (FA) Company (Wills and Perungulam, 2007). However, each technique has its own limitation. Mechanical polish...
With technology scaling of semiconductor devices and further growth of the integrated circuit (IC)¹ design and function complexity, the package size has shrank down proportionally too. Hence, flip-chip solder bump mounting is the current semiconductor devices trend to replace the wire bonding technology.
When come to PFA² on the flip-chip devices w...
With continuous scaling on CMOS device dimensions, it is becoming increasingly challenging for conventional failure analysis (FA) methods to identify the failure mechanism at the circuit level in an integrated chip. Scanning Electron Microscopy (SEM) based nanoprobing is becoming an increasingly critical tool for identifying non-visual failures via...
Presently two major limiting factors are hindering the failure analysis (FA) development during the semiconductor manufacturing process and technology improvement: (1) Impossibility of manual polishing on the edge dies due to the amenability of layer peeling off; (2) Abundant demand of multi-locations FA, especially focusing different levels of lay...
The shrinking in feature sizes of semiconductor devices from integrated circuit (IC)¹ and function complexity has led to greater PFA² delayering challenges. The challenges stem from incorporation of top thick hard Silicon Dioxide (SiO2) material that is formed from Tetra Ethyl Ortho Silicate (TEOS)³ as Inter-Metal Dielectric (IMD)⁴ and very thin ul...
With continuous scaling of Complementary Metal Oxide Semicondutor (CMOS) device dimensions, traditional inter-level dielectrics have be replaced by low-k materials, because of the advantages of ultra low-k material such as lower parasitic capacitance, lower cross talk effects, and lower RC delay. The new material in integrated circuits (IC) makes p...
Reliability tests, such as High-Temperature Operating Life (HTOL), Hot Carrier Injection (HCI), Time Dependent Dielectric Breakdown (TDDB), etc., is required for the lifetime prediction of an integrated circuit (IC) product. Transmission Electron Microscopy (TEM) analysis is required to provide insights to the defect mechanisms, induced in the scal...
With continuous scaling of CMOS device dimensions, sample preparation for Transmission Electron Microscope (TEM) analysis becomes increasingly important and challenging as the required sample thickness is less than several tens of nanometers. This paper studies the protection materials for FIB milling to increase the success rate of ex-situ 'lift-o...
With technology scaling of semiconductor devices and further growth of the integrated circuit (IC) design and function complexity, it is necessary to increase the number of transistors in IC's chip, layer stacks, and process steps. The last few metal layers of Back End Of Line (BEOL) are usually very thick metal lines (>4μm thickness) and protected...
In this work, we present two case studies on the utilization of advanced nanoprobing on 20nm logic devices at contact layer to identify the root cause of scan logic failures. In both cases, conventional failure analysis followed by inspection of passive voltage contrast (PVC) failed to identify any abnormality in the devices. Technology advancement...
It is becoming increasingly challenging for conventional failure analysis methods to identify the failure mechanism at circuit level in an integrated chip. This paper demonstrates the utilization of nanoprobing for on-chip device and circuit debugging for defect localization at circuit level. FIB circuit edit was first performed to isolate the inte...
With the scaling of semiconductor devices to nanometer range, ensuring surface uniformity over a large area while performing top down physical delayering has become a greater challenge. In this paper, the application of laser deprocessing technique (LDT) to achieve better surface uniformity as well as for fast deprocessing of sample for defect iden...
Top-down layer by layer delayering inspection with polisher and progressive cross-sectional Focus Ion Beam (XFIB) slicing are two common approaches for Physical Failure Analysis (PFA). This paper uses cross-sectional focus ion beam to perform top down layer by layer delayering inspection. The advantages of this technique include: 1) having a better...
Conductive-Atomic Force Microscopy (C-AFM) is a popular failure analysis method used for localization of failures in Static Random Access Memory (SRAM) devices. The SRAM structure has a highly repetitive pattern where any abnormality in a failed cell compared to neighboring cells could be easily identified from its current image. Unlike topographic...
With the shrinkage of the IC device dimension, Cu and ultra-low-k dielectric were introduced into IC devices to reduce the RC delay. Ultra-low-k dielectrics generally suffer more damage than silicon oxide dielectric during process integration and subsequently cause reliability degradation. Therefore, ultra-low-k damage characterization on Cu damasc...
With further technology scaling, it becomes increasingly challenging for conventional methods of failure analysis (FA) to identify the cause of a failure. In this work, we present three case studies on the utilization of advanced nanoprobing for SRAM circuit analysis and fault identification on 20 nm technology node SRAM single bit devices. In the...
Top-down, layer-by-layer de-layering inspection with a mechanical polisher and serial cross-sectional Focused Ion Beam (XFIB) slicing are two common approaches for physical failure analysis (PFA). This paper uses XFIB to perform top-down, layer-by-layer de-layering followed by Scanning Electron Microscope (SEM) inspection. The advantage of the FIB-...
Sharper nanotips are required for application in nanoprobing systems due to a shrinking contact size with each new transistor technology node. We describe a two-step etching process to fabricate W nanotips with controllable tip dimensions. The first process is an optimized AC electrochemical etching in KOH to fabricate nanotips with a radius of cur...
Top-down, layer-by-layer de-layering inspection with a mechanical polisher and serial cross-sectional Focused Ion Beam (XFIB) slicing are two common approaches for physical failure analysis (PFA). This paper uses XFIB to perform top-down, layer-by-layer de-layering followed by Scanning Electron Microscope (SEM) inspection. The advantage of the FIB-...
Rapid technology scaling results in ever shrinking device size. As such, sharper nanotips are required for application in nanoprobing systems. In this work, we present a two-step methodology of fabricating tungsten nanotips with radius of curvature down to 20 nm by using and optimized AC electrochemical etching of tungsten in KOH followed by laser...
With the scaling down of semiconductor devices to nanometer range, fault isolation and physical failure analysis (PFA) have become more challenging. In this paper, different types of fault isolation techniques to identify gross short failures in nanoscale devices are discussed. The proposed cut/deprocess and microprobe/bench technique is an economi...
SEM-based nanoprobing has proven vital in identifying nonvisual failures through electrical characterization in current FA metrology for fault identification. With eight probes used concurrently, the system could have the ability to obtain other important information such as cell stability as well as the static noise margin (SNM). In this work, the...
Electrical characterizations were needed to identify the root cause of leakage issues in IC devices. The methodology required was dependent on the failure mode obtained during testing and global or nano-scale isolations had to be implemented accordingly. As such, challenges encountered in sample preparation or due to detection methodology choices f...
The scanning electron microscope (SEM) based nanoprobing technique has established itself as an indispensable failure analysis (FA) technique as technology nodes continue to shrink according to Moore's Law. Although it has its share of disadvantages, SEM-based nanoprobing is often preferred because of its advantages over other FA techniques such as...
Ni diffusion in sub-100 nm devices can adversely affect electrical performance, and contribute greatly to yield loss. Despite the tremendous advantages of Ni salicide technology over Ti or Co, there are problems associated with the intrinsic properties of NiSi. Ni spiking into Si substrate or conductive bridges between silicide on the gate electrod...
As electronic devices shrink further in the nanometer regime, electrical characterization using nanoprobing has become increasingly important. Focused ion beam (FIB) is one useful technique that can be used to create markings for ease of defective site identification during nanoprobing. This paper investigates the impact of FIB exposure on the elec...
With the scaling down of semiconductor devices to nanometer range, physical failure analysis (PFA) has become more challenging. In this paper, a different method of performing PFA to identify a physical vertical short of intermetal layer in nanoscale devices is discussed. The proposed chemical etch and backside chemical etch PFA techniques have the...
With the miniaturization of electronic devices, identifying the root cause of soft failures using physical failure analysis (PFA) techniques has become a more challenging task. By characterizing the electrical behavior of malfunctioned devices, nanoprobing precisely locates defects before any PFA is performed and allows for deeper understanding of...
Selection of optimized electron beam parameters for in-line monitoring is necessary to eliminate false signals. Application of electron beam to detect electrical defects, particularly leakages, for static random access memory (SRAM) cells poses a great challenge as it requires current measurement tool with nanometer resolution to complement it. By...
With the shrinkage of the transistor dimensions, the spacing between the structures become smaller and smaller. However due to the intrinsic characteristic of the CMOS device, the reduction of the operating voltage is limited. The electrical field between different structures keeps on increasing with the shrinkage of the transistor dimensions. Furt...
This paper highlights the use of a localized probing technique, nanoprobing, to reveal some of the subtle defects affecting the yield of integrated circuits in the nanometer generation nodes. The tool is equipped with the capability to isolate and characterize the exact failing transistors of the malfunctioned devices. As a result, the identificati...
With the scaling down of semiconductor devices to nanometer range, physical failure analysis (PFA) has become more challenging. In this paper, a different method of performing PFA to identify a physical vertical short of inter-metal layer in nanoscale devices is discussed. The proposed chemical etch and backside chemical etch PFA techniques have th...
As electronic devices shrink further in the nanometer regime, electrical characterization using nanoprobing has become increasingly important. Focused ion beam (FIB) is one useful technique that can be used to create markings for ease of defective site identification during nanoprobing. This paper investigates the impact of FIB exposure on the elec...
Nanoprobing plays a crucial role for failure analysis (FA) in the nanometer-region generation nodes by having the capability to detect the failure sites and characterize the electrical behaviour of malfunctional devices for better understanding of the failure mechanisms. It also offers a guide to the necessary physical analysis in identifying the c...
NiSi has replaced CoSi<sub>2</sub> as the salicide material for 65 nm technology and beyond mainly due to its low salicide resistance for the narrow line width structures. However, it may bring along unwanted salicidation, resulting in failed transistors. This paper highlights how unwanted salicidation, also known as Ni piping, is successfully iden...
The combined use of scanning probe microscope based techniques, namely conductive atomic force microscopy (C-AFM) and tunneling atomic force microscopy (TUNA), and nanoprobing technique is presented. In 90 nm process and below, C-AFM identifies leakage by current mapping, while TUNA measures the current-voltage (I-V) curves of different contacts to...
A retrospective review was made of 28 surgically treated tennis elbows in the Department of Orthopaedics Surgery O SGH between Jan 1986 and Aug 1988. Biodata, duration of conservative treatment, postoperative results and length of recuperation were analysed. All except one patient was discharged from follow-up at the time of the study. Females outn...
Device scaling has been implemented throughout the chip making industry as a means of increasing density and performance. This has imposed a lot of challenging tasks to develop new processes, improve process window and reduce defect density. In our fabrication of 65nm W contact to M1 scheme, we found severe metal 1 shorts after electrical testing,...
Citations
... Te size of memory cell is mainly related to its stability, and the noise margin is an important parameter for the stable storage of data in the memory cell. Te noise margin of nvSRAM mainly includes static noise margin (SNM) [10], read noise margin (RNM) [11][12][13], and write noise margin (WNM) [14]. Te three-noise margin represents the antinoise ability of the memory cell in three modes: data storage, reading, and writing. ...
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... FIB milling technique utilizes a finely focused gallium (Ga+) ion beam (i-beam) by directly milling on the target for physical failure isolation with e-beam for real-time imaging [6]. Milling technique is important as it can determine the outcome of the analysis: finding or missing the defect. ...
... In nonvolatile memory (NVM) devices, the memory bit-counting is even more challenging, since the metal layer (here it is M5) blocking the WLs directly lands on the memory cells (Figure 2a, b). There have been numerous FA studies on SRAM/NVM devices, from hard short/open failure [2][3][4] to subtle defect induced marginal failure [5][6][7]. After the electrical fault isolation (EFI) or bit-map analysis, memory bit-counting is the key step for TEM analysis or transistor-level probing to locate the defect. ...
... For decades, the classic pad-based on-chip ESD protection scheme has been widely used for almost all ESD protection designs, which work effectively to protect ICs against the external-oriented "from-external-tointernal" types of ESD events, such as human body model (HBM), machine model (MM) and International Electrotechnical Commission (IEC) ESD test models [1]. Nevertheless, while the pad-based ESD protection method has been the default solution for CDM ESD protection, its effectiveness is becoming increasingly questionable due to the fact that CDM ESD protection remains notoriously uncertain and unreliable in designs, testing and field failure analysis, in spite of all CDM ESD protection design efforts [5][6][7]. Recently, it is reported that conventional pad-based CDM ESD protection method may be theoretically wrong because CDM ESD phenomena are internal-oriented and "from-internal-to-external" in nature [7]. In addition, traditional in-plane side-by-side ESD protection designs not only consume significant Si die area, but also are extremely layout-unfriendly, particularly for large and high-pin-count chips in beyond-28nm IC technologies [4]. ...
![[object Object]](https://i1.rgstatic.net/ii/profile.image/1108061573918722-1641193874480_Q64/Binghai-Liu.jpg)
... In refs. [3,4] a unique phase transformation was observed in the CoFeB thin films under high-dose electron irradiation, from a polycrystalline Co 3 Fe to a unilateral amorphous phase of Co 3 Fe and nanocrystalline alloy. Kinetic studies by in situ transmission electron microscopy revealed that the surface crystallization and diffusion-controlled nucleation and grain growth are significantly enhanced by the radiation-enhanced atomic diffusivity caused by the high-concentration of radiation-induced point defects in different materials. ...
... Based on the defect counting values and polishing removal rates, we propose suitable polymer abrasives that can improve the yields of IC chips in wafer fabrication and manufacturing. Figure 1 shows a schematic plot of semiconductor fabrication for wafers that can be classified into a front-end-of-line (FEOL) step, indicated by the white regions with interior brown segments, and back-end-of-line (BEOL) steps, indicated by the purple and yellow regions with interior brown segments [9]. These are the production phase steps. ...
... Typically, the body effect is measured by a transistor parameter analyzer such as HP4156. However, if we want to measure the body effect in the DRAM cell, the DRAM wafer or package must be destroyed in a nanoprobe measurement [16,18]. This paper proposes a novel method to measure the DRAM cell transistor body effect, instead of using a TEG method or nano-probe method. ...
... In modern electronic industry, the development of the integrated circuit (IC) design and technology node of semiconductor devices poses increasing challenges to PFA techniques due to the higher density of transistors and metal layers in a chip [1]. As one of the failure analysis (FA) branches for defect identification and yield improvement, PFA acts an important role in analyzing memory failure devices, where bit-counting and marking on the failed bits are necessary for the final physical imaging of the defect in transmission electron microscopy (TEM). ...
... In this paper, we will introduce an innovative LDT assisted memory bit-counting method that is applicable to both SRAM and NVM devices. LDT is fast, simple, and has been used to secure an uneven sample surface and remove unwanted layers [1,8]. LDT employs pulse laser with high peak power to irradiate the sample and physically remove material from the surface, which is economical, efficient, and user-friendly. ...
... MP has been documented as a difficult and uncontrolled process that does not allow for the targeting of a specific depth or layer, especially very thin layers (hundreds or fewer nanometers) [9]. ...
