Mateus Thurow Schoenknecht's research while affiliated with Universidade Federal de Pelotas and other places

This paper presents a hardware design for the H.264/AVC Quarter-Pixel Motion Estimation Refinement to be used in a complete Fractional Motion Estimation architecture. The architecture was optimized to reach a high throughput through a balanced pipeline and parallelism exploration. The design was described in VHDL and synthesized to an Altera Stratix III FPGA device. The design achieves an operation frequency of 245 MHz, processing up to 39 QHDTV frames (3840×2048 pixels) per second. This architecture is also able to reach real time when processing other resolutions, like HD 1080p (1920×1080 pixels) with lower operation frequencies. The final results are very competitive when compared to related works.

This paper presents a hardware design for the H.264/AVC Eighth-Pixel Chrominance Interpolation Unit that is a part of the Motion Compensation Unit. The architecture was optimized to reach a high throughput through a balanced pipeline and internal parallelism exploration. The design was described in VHDL and synthesized to a Xilinx Virtex2p FPGA. The best performance results achieve an operation frequency of 100 MHz, processing up to 42 QHDTV frames (3840×2048 pixels) per second.

This paper presents a high-performance hardware architecture for the H.264/AVC Half-Pixel Motion Estimation that targets high-definition videos. This design can process very high-definition videos like QHDTV (3840×2048) in real time (30 frames per second). It also presents an optimized arrangement of interpolated samples, which is the main key to achieve an efficient search. The interpolation process is interleaved with the SAD calculation and comparison, allowing the high throughput. The architecture was fully described in VHDL, synthesized for two different Xilinx FPGA devices, and it achieved very good results when compared to related works.

This work presents a high performance hardware architecture for the H.264/AVC Half-Pixel Motion Estimation Refinement. This design can process very high definition videos like QHDTV (3840x2048) in real time processing (30 frames per second). It also presents a very optimized arrangement of interpolated samples, which is the main key to achieve an efficient search. The architecture was fully described in VHDL, synthesized to two different Xilinx FPGA devices and achieved the best results when compared to related works.

This work presents a high performance half pixel interpolation unit for the H.264/AVC standard. The presented architecture is able to process very high definition videos (3840 × 2048 pixels) at real time processing (30 frames per second), and can be integrated in a complete motion estimation architecture without limiting the other modules' performance. It also presents a novel arrangement of interpolated samples which makes simple the search for the best fractional motion vector. The architecture was described in VHDL and synthesized to a Xilinx Virtex4 FPGA, and it achieved the best results when compared to related works published in the literature.

This work proposes a hardware solution for the H.264/AVC Quarter-Pixel Motion Estimation Refinement, ready to be used in a complete Fractional Motion Estimation architecture. The architecture was optimized to reach a high throughput through a balanced pipeline and parallelism exploration. The design was described in VHDL and synthesized to an Altera Stratix III FPGA device, achieving an operation frequency of 245 MHz and processing up to 39 QHDTV frames (3840x2048 pixels) per second. This architecture is also able to reach real time when processing lower resolutions, like HD 1080p (1920x1080 pixels) with lower operation frequencies. The final results are very competitive when compared to related works.