M. Fonseca's scientific contributions
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Publications (3)
In this work, we present a design of a radix-2m Hybrid array multiplier using Carry Save Adder (CSA) circuit in the partial product lines in order to speed-up the carry propagation along the array. The Hybrid multiplier architecture was previously presented in the literature using Ripple Carry Adders (RCA) in the partial product lines. In our work...
In this work, we present a design of a radix-2m Hybrid array multiplier using Carry Save Adder (CSA) circuit in the partial product lines in order to speed-up the carry propagation along the array. The Hybrid multiplier architecture was previously presented in the literature using Ripple Carry Adders (RCA) in the partial product lines. In our work...
Citations
... In 2005, Fonseca, M.; da Costa, E. et al presented a design of a Radix 2 m hybrid Array multiplier to handle operands in 2's-complement form by using Carry Save Adder in each partial product lines. The results showed that the multiplier architecture with CSA gives better performance in terms of area, speed and power consumption as compared to the architecture with RCA [10]. Further in 2008, Hasan Krad and Aws Yousif Al-Taie worked on performance analysis of a 32-Bit unsigned data multiplier with CLA logic and a 32-bit multiplier with a RCA using VHDL. ...
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... This architecture leads to an improvement in performance at the cost of an area penalty. In [12], another approach for radix-2 m is presented by using carry save adder (CSA) in the partial products, to improve the corresponding modified Booth circuits. Dedicated 16 and 256 radices by using CSA in the partial products are presented in [27], which improve the generic solutions presented in [12,13]. ...
