M D Sameera Shrity's scientific contributions

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Publications (1)


Fig. 4 Circuit Simulation of 1 bit-full adder
Fig.5 Transmission gate based Full-Adder [2]
Fig. 7 Schematic result of Transmission Gate based Full-Adder
Fig. 8 Gate Diffusion input based full adder [3]
Fig. 10 Schematic view of Basic Gate Diffusion inverter

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An Efficient full adder using FinFET Technology
  • Article
  • Full-text available

April 2019

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3,261 Reads

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5 Citations

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M Dharmendra

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R Pavan Sai

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M D Sameera Shrity

Due to the recent technology trends all the electronic markets are based on reliable and speed performance devices. By developing semiconductor industry, all the passive and active components are assembled on a single chip named as an Integrated chip (IC). Developing this type of technology made all the electronic devices becomes smarter and reliable in performance. These technology nodes are based on CMOS technology. The main component in the processor is an ALU. We make survey on Adder type of devices which gave you addition subtraction and all arithmetical operators performed in circuit level and logic level implementation. And also we designed new technology named as FinFET based adder circuits which give us better performance like. Less Leakage power, low power consumption and less propagation delay. We verify all the parameters in 45nm Technology node to both CMOS and FinFET technology by using spice tool.

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Citations (1)


... Compared to traditional CMOS adders, the FINFET-based GDI full adder has a low PDP. 5 The hybrid full adder (HFA), which is FINFET-based, has the least latency and operates at a high speed. The best application for FINFET HFA is therefore highspeed. ...

Reference:

Erratum: Diode Connected Transistor-Based Low PDP Adiabatic Full Adder in 7nm FINFET Technology for MIMO Applications
An Efficient full adder using FinFET Technology