M. Chandra Sekhar Reddy's research while affiliated with Sri Venkateswara College of Engineering and other places

A FinFET-based 8-bit low-power arithmetic and logic unit (ALU) with full-swing 9-transistor GDI-hybrid full adder has been presented in this research paper. An intelligent signal gating-aware energy-efficient ALU is proposed using this adder and signal gating circuit. An adaptive signal gating is applied according to the current ALU operation based on the particular operation corresponding control word. The input signals to the other blocks are gated such that the proposed intelligent signal gating scheme customizes the overall power utilization of the proposed ALU. The proposed ALU has been implemented using 20 nm FinFET PTM models. The total power consumption of the conventional FinFET ALU to execute all eight operations is 619.55 µW, whereas the proposed ALU consumes 225.53 µW only. The average power consumption of the traditional FinFET ALU is 77.44 µW per operation, while the proposed low-power ALU needs 28.19 µW only. The maximum amount of total and average power that the proposed scheme can optimize is 63.59%.

This paper objective is to design a low power VCRO with less area optimization using Single Electron transistor (SET). This design requires nine differential amplifiers in which the last stage is feedbacked to input. Using SET technology, the frequency range of VCRO is increased up to 40 GHz, and power dissipation is 20 microwatts and area utilized is 600 nano meter square. A 73% improvement in power consumption is observed in SET compared to CMOS.