L. DiCarlo's research while affiliated with Delft University of Technology and other places

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Publications (114)


(a) Schematic and SEM images at two length scales of the test structures used to investigate uniformity of Dolan versus Manhattan JJ pairs on planar and TSV-integrated wafers. Two junctions in each structure complete a loop with a pre-fabricated NbTiN base. Probing pads in the base allow measuring the parallel conductance of the junction pair. (b) Die-level planar layout with 17, 4×4 sub-arrays of junction test structures. Each array is centered at the location of one transmon in our planar Surface-17 SQP. Each array has a sweep of junction overlap area Aoverlap in one of three ranges (labeled l, m and h). (c) Die-level TSV layout arranged as 17, 5×5 sub-arrays of junction test structures. Each array is centered at the location of one transmon in our TSV-integrated Surface-17. One such array is highlighted by the white dotted line. Each array has an identical sweep of Aoverlap . Test structures that overlap with vias (black circles) are ignored and not included in measurements, yielding at most 378 test structures per die. Heatmaps in (b) and (c) indicate the chosen Aoverlap for each test structure.
(a) Wafer-scale mean-normalized conductance heatmap of Dolan (top) and Manhattan (bottom) JJ test structures on the Planar 17Q wafer. The origin (0,0) indicates wafer center. Blank cells correspond to test structures identified as defective by the filtering. For this dataset, both JJ types are fabricated on a single wafer. (b) Wafer-scale conductance CV for both junction types as a function of Aoverlap . (c) Die-level RSD of predicted qubit frequency as a function of distance (d) between die and wafer centers.
(a) Wafer-scale mean-normalized conductance heatmap of Dolan (top) and Manhattan (bottom) JJ test structures on TSV-integrated 17Q wafers. For this dataset, two separate wafers are fabricated, one for each JJ type. The origin (0,0) indicates wafer center. Blank cells correspond to defective junctions removed by filtering outliers at die level. Cells marked with black circles indicate TSV locations. (b) Wafer-scale conductance CV for unfiltered (nf) and regression-filtered (f) Dolan JJ pairs and for filtered Manhattan JJ pairs as a function of Aoverlap . (c) Die-level RSD of predicted qubit frequency as a function of distance (d) between die and wafer centers.
(a) Schematic of e-beam Al evaporation setup (not drawn to scale). Please see text for further details and parameter values. The illustration shows the decrease in junction electrode width from center to edge of wafer arising from the spatially-dependent shadowing effect. (b) Wafer-scale mean-normalized conductance computed from actual junction overlap area Aoverlap′ as per equation (2), for Manhattan JJs with Wt=Wb=200nm and δWoffset=25nm . (c) Same as (b) but adding the overlap contribution from sidewalls as per equation (4). (d) Same as (c) but adding effects of the first evaporation (of the bottom electrode) on the second evaporation (of the top electrode) (equations (5)–(7)).
Wafer-scale mean-normalized conductance heatmap of 35×35 array of Manhattan JJ test structures fabricated on three planar wafers with the variants indicated by the top schematics. (a), (b) Symmetric junction pairs with (a) NbTiN probing pads deposited by sputtering and (b) TiN probing pads deposited by ALD. The black dotted line indicates the diagonal along which the JJ pairs are imaged for figure S9. (c) Single junctions with simultaneously fabricated Al probing pads. The hatched rows indicate accidentally omitted junctions during data acquisition. (d)–(f) Distribution of actual JJ overlap area Aoverlap′ as a function of junction radial position (d). Here, Aoverlap′ is extracted from top-view SEM images. Note that Aoverlap′ does not include the sidewall overlap as this contribution cannot be extracted from these images. The black curves are the best fits of the simplest geometric model (equation (2) with single free parameter δWoffset ). (g)–(i) Effective junction conductivity (computed from designed and actual overlap areas) as a function of d. The dashed (solid) curves are quadratic fits of Aoverlap ( Aoverlap′ ).
Wafer-scale uniformity of Dolan-bridge and bridgeless Manhattan-style Josephson junctions for superconducting quantum processors
  • Article
  • Full-text available

February 2024

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35 Reads

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2 Citations

Quantum Science and Technology

Quantum Science and Technology

Nandini Muthusubramanian

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Matvey Finkel

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Pim Duivestein

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[...]

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Leonardo DiCarlo

We investigate die-level and wafer-scale uniformity of Dolan-bridge and bridgeless Manhattan Josephson junctions, using multiple substrates with and without through-silicon vias (TSVs). Dolan junctions fabricated on planar substrates have the highest yield and lowest room-temperature conductance spread, equivalent to ~100 MHz in transmon frequency. In TSV-integrated substrates, Dolan junctions suffer most in both yield and disorder, making Manhattan junctions preferable. Manhattan junctions show pronounced conductance decrease from wafer center to edge, which we qualitatively capture using a geometric model of spatially-dependent resist shadowing during junction electrode evaporation. Analysis of actual junction overlap areas using scanning electron micrographs supports the model, and further points to a remnant spatial dependence possibly due to contact resistance.

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Fig. 3 Quantum control setup. a Schematic of wiring and control electronics, highlighting critical feedback path between outputs of the quantum processor, the analog-interface devices, controller, and the flux-drive lines. b Timing diagram for the critical feedback path. Hashed regions indicate idling operations for each instrument. Latency concerns the time necessary to ensure synchronicity, since instruments are delayed with respect to the AWGs to account for the difference in propagation/latency time between readout and qubit drive instrumentation.
Fig. 4 Quantum neural network using the repeat-until-success conditional gearbox circuit. a Schematic representation of simplest feedforward network, highlighting the role played by parameters (w 1 , w 2 , b) in weighing the sum of input signals, before the result is passed through a non-linear activation function. Q I1 and Q I2 are input nodes, Q O is the output node and Q A is an ancilla used first within the RUS circuit and then as expected output for the training set. b Quantum circuit for a 3-neuron feedforward network. This circuit is divided into four steps. Input (Q I1 , Q I2 ) preparation into maximal superposition; threshold activation into Q O using RUS conditional gearbox circuit with (w 1 , w 2 , b); unitary encoding of Boolean function (AND, in this case) using oracle; and comparison of Q A with Q O . XY-4 specifies an error mitigation sequence 38 applied during measurement and the symbol ⊔ denotes parking of spectator qubit Q I2 (Q I1 ) during CZ(Q A , Q I1 ) ( CZ(Q A , Q I2 )) gates [Supplementary Materials].
Fig. 5 Feature space landscapes of three Boolean functions. 2-D slices of 〈C〉 and 〈N RTS 〉 for XOR (a, b) IMPLICATION 2 (c, d), and NAND (e, f). For each function, the slice includes (w 1 , w 2 , b) parameters that minimize 〈C〉 for an ideal quantum processor. Black dots indicate the experimental parameters achieving minimal 〈C〉 within each slice.
Fig. 6 Learning the NAND function. a Training the QNN to learn NAND over the full parameter space (w 1 , w 2 , b) by minimizing 〈C〉 with an adaptive algorithm. Training starts from a randomly-chosen point, then explores the boundaries, and ultimately converges within ~ 50 steps. b-e Evolution of training parameters (w 1 , w 2 , b) and 〈C〉 as a function of training step. The current best setting achieved is marked by a star.
Fig. 7 Specificity of the quantum neural network. Cost function of the optimized parameter set for every training function (horizontal axis) against all oracle functions (vertical axis). In each axis, the functions are ordered from constant, to balanced, to unbalanced. Functions are put alongside their complementary function (NULL and IDENTITY, TRANSFER1 and NOT1, etc.). For an ideal processor, 〈C〉 values are expected at or close to multiples of 0.25, due to the varying overlap between the 16 Boolean functions (i.e., the number of 2-bit inputs producing different 1-bit outcomes). Further differences arise in the experiment due to variations in the average circuit depth of the RUS-based activation functions and in the fixed circuit depth of oracle functions.
Realization of a quantum neural network using repeat-until-success circuits in a superconducting quantum processor

November 2023

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92 Reads

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3 Citations

npj Quantum Information

Artificial neural networks are becoming an integral part of digital solutions to complex problems. However, employing neural networks on quantum processors faces challenges related to the implementation of non-linear functions using quantum circuits. In this paper, we use repeat-until-success circuits enabled by real-time control-flow feedback to realize quantum neurons with non-linear activation functions. These neurons constitute elementary building blocks that can be arranged in a variety of layouts to carry out deep learning tasks quantum coherently. As an example, we construct a minimal feedforward quantum neural network capable of learning all 2-to-1-bit Boolean functions by optimization of network activation parameters within the supervised-learning paradigm. This model is shown to perform non-linear classification and effectively learns from multiple copies of a single training state consisting of the maximal superposition of all inputs.


Post-fabrication frequency trimming of coplanar-waveguide resonators in circuit QED quantum processors

July 2023

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10 Reads

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4 Citations

Applied Physics Letters

We present the use of a set of airbridges to trim the frequency of microwave coplanar-waveguide (CPW) resonators post-fabrication. This method is compatible with the fabrication steps of conventional CPW airbridges and crossovers and increases device yield by allowing compensation of design and fabrication uncertainty with 100 MHz range and 10 MHz resolution. We showcase two applications in circuit QED. The first is the elimination of frequency collisions between resonators intended to readout different transmons by frequency-division multiplexing. The second is frequency matching of readout and Purcell-filter resonator pairs. Combining this matching with transmon frequency trimming by laser annealing reliably achieves fast and high-fidelity readout across 17-transmon quantum processors.


Lower-temperature fabrication of airbridges by grayscale lithography to increase yield of nanowire transmons in circuit QED quantum processors

July 2023

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26 Reads

Applied Physics Letters

Quantum hardware based on circuit quantum electrodynamics makes extensive use of airbridges to suppress unwanted modes of wave propagation in coplanar-waveguide transmission lines. Airbridges also provide an interconnect enabling transmission lines to cross. Traditional airbridge fabrication produces a curved profile by reflowing resist at elevated temperature prior to metallization. The elevated temperature can affect the coupling energy and even yield of pre-fabricated Josephson elements of superconducting qubits, tunable couplers, and resonators. We employ grayscale lithography to enable reflow and thereby reduce the peak temperature of our airbridge fabrication process from 200 to 150 °C and link this change to a substantial increase in the physical yield of transmon qubits with Josephson elements realized using Al-contacted InAs nanowires.


All-Microwave Leakage Reduction Units for Quantum Error Correction with Superconducting Transmon Qubits

June 2023

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15 Reads

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13 Citations

Physical Review Letters

Minimizing leakage from computational states is a challenge when using many-level systems like superconducting quantum circuits as qubits. We realize and extend the quantum-hardware-efficient, all-microwave leakage reduction unit (LRU) for transmons in a circuit QED architecture proposed by Battistel et al. This LRU effectively reduces leakage in the second- and third-excited transmon states with up to 99% efficacy in 220 ns, with minimum impact on the qubit subspace. As a first application in the context of quantum error correction, we show how multiple simultaneous LRUs can reduce the error detection rate and suppress leakage buildup within 1% in data and ancilla qubits over 50 cycles of a weight-2 stabilizer measurement.


Wafer-scale uniformity of Dolan-bridge and bridgeless Manhattan-style Josephson junctions for superconducting quantum processors

April 2023

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51 Reads

We investigate die-level and wafer-scale uniformity of Dolan-bridge and bridgeless Manhattan Josephson junctions, using multiple substrates with and without through-silicon vias (TSVs). Dolan junctions fabricated on planar substrates have the highest yield and lowest room-temperature conductance spread, equivalent to ~100 MHz in transmon frequency. In TSV-integrated substrates, Dolan junctions suffer most in both yield and disorder, making Manhattan junctions preferable. Manhattan junctions show pronounced conductance decrease from wafer centre to edge, which we qualitatively capture using a geometric model of spatially-dependent resist shadowing during junction electrode evaporation. Analysis of actual junction overlap areas using scanning electron micrographs supports the model, and further points to a remnant spatial dependence possibly due to contact resistance.


Post-fabrication frequency trimming of coplanar-waveguide resonators in circuit QED quantum processors

February 2023

·

11 Reads

We present the use of grounding airbridge arrays to trim the frequency of microwave coplanar-waveguide (CPW) resonators post fabrication. This method is compatible with the fabrication steps of conventional CPW airbridges and crossovers and increases device yield by allowing compensation of design and fabrication uncertainty with $100~\mathrm{MHz}$ range and $10~\mathrm{MHz}$ resolution. We showcase two applications in circuit QED. The first is elimination of frequency crowding between resonators intended to readout different transmons by frequency-division multiplexing. The second is frequency matching of readout and Purcell-filter resonator pairs. Combining this matching with transmon frequency trimming by laser annealing reliably achieves fast and high-fidelity readout across 17-transmon quantum processors.


All-microwave leakage reduction units for quantum error correction with superconducting transmon qubits

February 2023

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10 Reads

Minimizing leakage from computational states is a challenge when using many-level systems like superconducting quantum circuits as qubits. We realize and extend the quantum-hardware-efficient, all-microwave leakage reduction unit (LRU) for transmons in a circuit QED architecture proposed by Battistel et al. This LRU effectively reduces leakage in the second- and third-excited transmon states with up to $99\% $ efficacy in $220~\mathrm{ns}$, with minimum impact on the qubit subspace. As a first application in the context of quantum error correction, we demonstrate the ability of multiple simultaneous LRUs to reduce the error detection rate and to suppress leakage buildup within $1\%$ in data and ancilla qubits over 50 cycles of a weight-2 parity measurement.


Figure 6: Learning the NAND function. (a) Training the QNN to learn NAND over the full parameter space (w 1 , w 2 , b) by minimizing C with an adaptive algorithm. Training starts from a randomly-chosen point, then explores the boundaries, and ultimately converges within ∼ 50 steps. (b-e) Evolution of training parameters (w 1 , w 2 , b) and C as a function of training step. The current best setting achieved is marked by a star.
Figure 7: Specificity of the quantum neural network. Cost function of the optimized parameter set for every training function (horizontal axis) against all oracle functions (vertical axis). In each axis, the functions are ordered from constant, to balanced, to unbalanced. Functions are put alongside their complementary function (NULL and IDENTITY, TRANSFER1 and NOT1, etc.). For an ideal processor, C values are expected at or close to multiples of 0.25, due to the varying overlap between the 16 Boolean functions (i.e., the number of 2-bit inputs producing different 1-bit outcome). Further differences arise in experiment due to variation in the average circuit depth of the RUS-based activation functions and in the fixed circuit depth of oracle functions.
Figure S2: Residual ZZ coupling. Characterization of residual ZZ coupling between all qubit pairs at the bias point (simultaneous flux sweetspot). The matrix elements indicate the shift in frequency experienced by one qubit (target qubit) when another (spectator qubit) changes from |0 to |1. The procedure used for this measurement is similar to the one described in [S1].
Figure S14: Simulation of feature space landscapes for the NAND function. Top panels show noiseless simulation of (a) C and (b) N RTS for NAND along 2-D slices of the 3-parameter space. Similarly, panels (c and d) show noisy simulation results and panels (e and f) the corresponding experimental results (same as Figs. 5e and 5f, respectively), reproduced here to facilitate comparison. Black dots indicate the parameters minimizing C within the slice.
Realization of a quantum neural network using repeat-until-success circuits in a superconducting quantum processor

February 2023

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33 Reads

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1 Citation

Artificial neural networks are becoming an integral part of digital solutions to complex problems. However, employing neural networks on quantum processors faces challenges related to the implementation of non-linear functions using quantum circuits. In this paper, we use repeat-until-success circuits enabled by real-time control-flow feedback to realize quantum neurons with non-linear activation functions. These neurons constitute elementary building blocks that can be arranged in a variety of layouts to carry out deep learning tasks quantum coherently. As an example, we construct a minimal feedforward quantum neural network capable of learning all 2-to-1-bit Boolean functions by optimization of network activation parameters within the supervised-learning paradigm. This model is shown to perform non-linear classification and effectively learns from multiple copies of a single training state consisting of the maximal superposition of all inputs.


Lower-temperature fabrication of airbridges by grayscale lithography to increase yield of nanowire transmons in circuit QED quantum processors

January 2023

·

13 Reads

Quantum hardware based on circuit quantum electrodynamics makes extensive use of airbridges to suppress unwanted modes of wave propagation in coplanar-waveguide transmission lines. Airbridges also provide an interconnect enabling transmission lines to cross. Traditional airbridge fabrication produces a curved profile by reflowing resist at elevated temperature prior to metallization. The elevated temperature can affect the coupling energy and even yield of pre-fabricated Josephson elements of superconducting qubits, tuneable couplers and resonators. We employ grayscale lithography in place of reflow to reduce the peak airbridge processing temperature from $200$ to $150^\circ\mathrm{C}$, showing a substantial yield increase of transmon qubits with Josephson elements realized using Al-contacted InAs nanowires.


Citations (64)


... However, the resulting resist inhomogeneity due to apertures being present during resist-spinning leads to devices with increased wafer-scale resistance spread. This is in-line with the results of Muthusubramanian et al. [28] In addition we record JJs that were unmeasureable due to chipping of the sapphire. (d) Histograms of the JJ resistances prior to, and after, the sapphire machining process. ...

Reference:

Integration of through-sapphire substrate machining with superconducting quantum processors
Wafer-scale uniformity of Dolan-bridge and bridgeless Manhattan-style Josephson junctions for superconducting quantum processors
Quantum Science and Technology

Quantum Science and Technology

... As sketched in Fig. 1a, our DQNN has a layer-by-layer structure, and maps the quantum information layerwise from the input layer state ρ in , through L hidden layers, to the output layer state ρ out . Quantum perceptrons are the building blocks of the DQNN, and different types of quantum perceptrons have been experimentally implemented recently [26][27][28] . DQNNs with the most general form of quantum perceptrons, which can apply generic unitaries on all qubits at adjacent layers, are capable of universal quantum computation 29 . ...

Realization of a quantum neural network using repeat-until-success circuits in a superconducting quantum processor

npj Quantum Information

... Recently, researchers used a set of air bridges to adjust the frequency of the CPW resonator, achieving frequency matching between the readout resonator and the Purcell filter. [21] To avoid trials and errors in experiments, this work combines the circuit simulations and the finite element calculations to analyze the microwave transmission characteristics and coupling structure design of the Purcell filter (Heinsoo et al. [20] ) under graphical edge etching deviations. This study provides design guidance for optimizing the structure of the CPW, filters, and feed lines, so as to significantly improve the performance stability of the Purcell filter. ...

Post-fabrication frequency trimming of coplanar-waveguide resonators in circuit QED quantum processors
  • Citing Article
  • July 2023

Applied Physics Letters

... When an LRU is included in a QEC scheme, a threshold can be obtained for leakage noise [14]. LRUs can broadly be split into two categories: hardware-based, which directly return qubits to the computational space [9,[15][16][17][18], and circuit-based, which modify the QEC circuit to ensure all qubits are regularly reset-returning them to the computational space if they were leaked [8,14]. Both types of LRU have costs associated with them: hardware-based LRUs often inject more computational noise into the system, whereas circuit-based LRUs require extra qubits and gates. ...

All-Microwave Leakage Reduction Units for Quantum Error Correction with Superconducting Transmon Qubits
  • Citing Article
  • June 2023

Physical Review Letters

... Quantum computing has made enomorous experimental progresses in recent years [1,2], most prominently the demonstrations of quantum computational advantages [3][4][5][6][7][8][9][10] and of quantum error correction [11][12][13][14][15][16][17][18][19][20]. However, there is still a considerable level of noise rates in all the existing quantum computing hardware, and there is still a long way before achieving full fault-tolerant quantum computing. ...

Logical-qubit operations in an error-detecting surface code

Nature Physics

... In recent years, new types of quantum algorithms including adaptations of classical ones have been developed to leverage the capacity of quantum computers [10], both for the near-term and fault-tolerant eras [11]. Algorithms developed for fault-tolerant quantum computers typically require the use of Quantum Phase Estimation (QPE) [12][13][14] as a sub-routine, while those made for near-term devices are typically based on variational routines such as the Variational Quantum Eigensolver (VQE) [15,16] or Quantum Approximate Optimization Algorithms (QAOA) [17,18]. * daniele.morrone@unimi.it ...

Variational preparation of finite-temperature states on a quantum computer

npj Quantum Information

... The gate duration can be short and is determined by the qubit-qubit coupling constant. This scheme is prone to (i) significant qubit dephasing, because the qubits are operated outside of their sweet spots, which can be addressed with net-zero pulses [15], (ii) crossing of two-level systems (TLS) defects during gate operation [16], and (iii) large residual ZZ crosstalk when the qubits are detuned from each other. The need to traverse a large frequency range with the qubit and thus potentially cross strongly coupled TLS defects can be circumvented, for example, using a parametrically modulated signal [17]. ...

High-Fidelity Controlled- Z Gate with Maximal Intermediate Leakage Operating at the Speed Limit in a Superconducting Quantum Processor
  • Citing Article
  • June 2021

Physical Review Letters

... The output of the compiler, low-level instructions, are then further translated into speci c pulses to operate and control the chip's qubits. For this purpose, quantum instruction set architectures [14], [15] and microarchitectures [16], [17] as well as control electronics (at even cryogenic temperatures) [18] have been developed. ...

Enhancing a Near-Term Quantum Accelerator's Instruction Set Architecture for Materials Science Applications

IEEE Transactions on Quantum Engineering

... In a circuit-based LRU, the QEC circuit is modified so that the roles between auxiliary and data qubits are regularly exchanged, thus allowing every qubit to be reset periodically [8,[19][20][21][22][23]. In superconducting platforms, leakage can naturally move between qubits, a property known as leakage mobility [24]. Therefore, leakage could in principle move from data to auxiliary qubits without the need for a circuit-based LRU. ...

Leakage detection for a transmon-based surface code

npj Quantum Information

... Thus, with YAQQ, we can determine which settings of the rotation angles (of, say, the generic P1 gate) can be hardcoded as a specific quantum instruction. This is an important problem in the design of the quantum microarchitectures [96]. Similar to how the {H1, T1} 1 qubit universality is proven by the SKT, and we understand their importance for entanglement generation and magic-state, the novel gate sets might lead us to discover new properties [97] of quantum information processing (e.g., super golden gates [26] and special perfect entanglers [98]) and aid in the understanding [99] of quantum resources [83]. ...

eQASM: An Executable Quantum Instruction Set Architecture
  • Citing Conference Paper
  • February 2019