Juhee Han's research while affiliated with Hanyang University and other places
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Publications (4)
The effect of crosstalk-induced errors becomes more significant in high-performance circuits and systems. In this paper, compact crosstalk test patterns are introduced for a system-on-a-chip and board level interconnects considering physically effective aggressors. By being able to target multiple victim lines, 6 n , where n is the number of nets p...
Today's system-on-a-chip (SoC) is designed with reusable intellectual property cores to meet short time-to-market requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, an efficiently testable design technique is introduced for an SoC with an on/off-chip bus bridge for the...
This paper introduces an efficient test access mechanism for advanced microcontroller bus architecture (AMBA) based SoC to reduce the test application time while minimally adding a new test interface logic. Testable design technique is applied to an SoC with the advanced high-performance bus (AHB) and PCI bus bridge by maximally reusing the bridge...
It becomes crucial to test and verify embedded hardware systems precisely and efficiently. For an embedded System-on-a-Chip
(SoC) comprised of multiple IP cores, various design techniques have been proposed to provide diverse test access link configurations.
In this paper, a Flag-based Wrapped Core Link Controller (FWCLC) is introduced to enable ef...
Citations
... In the approach, the linear feedback shift register ( LFSR ) was used to produce the test vectors. S.Jaehoon [8] investigated the fault detection of crosstalk faults in system on chip, the compact test pattern of crosstalk faults was presented considering physically effective aggressors. M.Pyoungwoo [9] discussed the crsootalk fault detection for system on chip and board interconnects, a test set with 6n test patterns was introduced to completely detect and diagnose both static and crosstalk faults, the n is the total number of interconnect nets. ...
... The project helps to develop effective and dependable embedded systems for a variety of application domains by tackling the difficulties involved in bridging different bus protocols. In order to maximise interaction among maximum performance,less-power peripherals, AHB, APB integrating is essential in contemporary SoCc designs (Sowmya Aithal et al. 2016;Song et al. 2008). The FPGA implementation of an Verilog bridge from AHB 2 APB is presented in this paper, enabling smooth transmission of data and the translation process of control signals via these popular bus protocols. ...
