Jorge Rivera's research while affiliated with Center for Research and Advanced Studies of the National Polytechnic Institute and other places

This article addresses a novel methodology for the utilization of Field Programmable Gate Array (FPGA) accelerators in on-board Synthetic Aperture Radar (SAR) processing routines. The methodology consists of using High-Level Synthesis (HLS) to create Intellectual property (IP) blocks and using the Reusable Integration Framework for FPGA Accelerators (RIFFA) to develop a Peripheral Component Interconnect express (PCIe) interface between the Central Processing Unit (CPU) and the FPGA, attaining transfer rates up to 15.7 GB/s. HLS and RIFFA reduce development time (between fivefold and tenfold) by using high-level programming languages (e.g., C/C++); moreover, HLS provides optimizations like pipeline, cyclic partition, and unroll. The proposed schematic also has the advantage of being highly flexible and scalable since the IPs can be exchanged to perform different processing routines, and since RIFFA allows employing up to five FPGAs, multiple IPs can be implemented in each FPGA. Since Fast Fourier Transform (FFT) is one of the main functions in SAR processing, we present a FPGA accelerator in charge of the reordering stage of VEC-FFT (an optimized version of FFT) as a proof of concept. Results are retrieved in reversed bit order, and the conventional reordering function may consume more than half of the total clock cycles. Next, to demonstrate flexibility, an IP for matrix transposition is implemented, another computationally expensive process in SAR due to memory access.

The boost converter is mostly used as a DC–DC converter, but two boost converter power stages can be configured to perform the DC–AC conversion. In this case, the control system of the power stage must be designed for trajectory tracking (instead of regulation), which brings interesting challenges. This work deals with the design of a higher-order sliding mode output regulator for a DC-biased sinusoidal power conversion problem on a single boost converter stage of a boost inverter for asymptotic trajectory tracking of the voltage capacitor. The steady-state reference signal for the inductor current is proposed as an approximated solution of the well-known Francis–Isidori–Byrnes equations. The used approach is the direct control of the output, where the nonminimum phase variable, i.e., an adequate sliding function, stabilizes the current through the inductor. Lastly, by means of real-time experimentation, the good performance of the proposed control strategy is verified.

Step-up converters are widely used in many applications, such as renewable energy generation with photovoltaic panels and fuel cell stacks. In many cases, the required voltage gain is larger for those applications than a traditional boost converter can achieve. Several large-voltage gain converters have been recently studied. This paper introduces a converter topology in which the voltage gain is larger than a traditional boost converter. The main advantages of the proposed topology are: (i) it provides a large voltage gain without the use of an extreme duty cycle; (ii) its capacitors require a smaller voltage to be sustained compared with other, similar state-of-the-art converters; (iii) the voltage among the ground input and output is not pulsating; and (iv) it can be synthesized with commercial, off-the-shelf half-bridge packed transistors. The proposed converter can be employed in different applications, such as distributed generation and microgrids. This paper presents the steady-state analysis of the proposed converter in the continuous conduction mode, a short comparison with similar topologies, and their voltage on capacitors. Computer-based simulation results are provided to verify the principle of the proposed converter in different operating conditions.