John J. Shedletsky's research while affiliated with IBM Research and other places
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Publications (12)
Delay testing is a test procedure to verify the timing performance of manufactured logic networks. When a level-sensitive scan design (LSSD) discipline is used, all networks are combinational. Appropriate test patterns are selected on the basis of certain theoretical criteria. These criteria are embodied in an experimental test generation program....
A recurring problem in the analysis of random testing is the tradeoff between accuracy and computational efficienlcy. Every random test requires an (implicit or explicit) analysis of the relaretionship between test confidence and test length for thle circuit under test. This analysis is used to specify a test length. The error latency model ELM [1]...
Dynamic self-checking is a technique used in computers to detect a fault quickly before extensive data contamination caused by the fault can occur. When the self-checking properties of the computer circuits are not perfect, as in the case of self-testing only and partially self-checking circuits, a recovery procedure may be required to roll back pr...
The correspondence between Boolean network probabilities and the design formalisms of Ledley and Aiken is demonstrated.
A new technique for low-cost error correction is the alternate-data retry (ADR). Like a conventional retry, an ADR is a re-execution of an operation that initially fails to produce an error-free result. Unlike a conventional retry, an ADR uses an alternate representation of the initial data. The choice of the alternate data representation and the d...
The application of delay tests is complicated in LSI due to the inaccesibility of individual gates for delay measurement. For designs conforming to the LSSD design discipline, a workable approach is to measure the delay incurred by a signal transition as it propagates along a single path from network input to network output. This paper examines the...
The sequential and indeterminate behavior of an end-around-carry (EAC) adder is examined. This behavior is commonly overlooked in the literature. Design modifications to impose determinism are provided. These modifications also eliminate the troublesome negative zero found in the one's complement number system.
In digital circuits there is typically a delay between the occurrence of a fault and the first error in the output. This delay is the error latency of the fault. A model to characterize the error latency of a fault in a sequential circuit is presented. Random testing of sequential circuits is analyzed using the error-latency model (ELM). For a desi...
Methods to obtain the value of the distruction parameter and thereby to
describe the error latency are given. The error latency models developed
provide analytic tools that are particularly suited to the study of:
(1.) random testing of a digital circuit; (2.) reliability modeling of a
digital circuit; and (3.) program rollback during recovery. The...
COMMENT Subtraction byaddition ofthecomplement isacommontechnique in computer design. Thediminished radix system fortherepresentation ofbinary numbers iswell knownandreferred toastheone's complement system(1), (2). Theone's complement ofabinary number A iseasily formed bycomplementing eachbitofA.Zerohastworepresentations, both00...0(positive zero)...
A recurring problem in the analysis of random testing is the tradeoff between accuracy and computational efficienlcy. Every random test requires an (implicit or explicit) analysis of the relaretionship between test confidence and test length for thle circuit under test. This analysis is used to specify a test length. The error latency model ELM [1]...
Citations
... However, even if the system has input codes to detect some faults, they might not be readily imputed to the system. Therefore, some faults might not be detected rapidly by self-testing [2][3][4]. Hence, to detect faults early and surely, it would be necessary to perform external inspection such as imputing a set of test codes at periodic times. In this case, if the system fails, then its fault is detected by self-testing or the next periodic inspection, whichever occur first. ...
... The error latency EL -of a fault F is the number of network whilei F inpu t (detection latency DLi) vectors applied to a is active until the first error (detection) response due toiF i is observed. The mean error (and detection) latency can be extremely large in , '-' some cases [ 7,8]. Definition. ...
... The paths selected for delay measurement can be timing-critical paths whose delays exceed the specified timing threshold under static timing analysis (STA) or statistical STA [40], [41] . Based on the selected timing-critical paths, the method proposed in [39] provides an effective way to further find an optimal path set for measurement, while the delays of all the selected timing-critical paths can be obtained either by direct measurement or by calculation from the measured delays. In this paper, we mainly focus on the design of the path delay measurement architecture. ...
... Equations (8) and (9) are also probability-ready expressions [67][68][69][70][71][72][73][74][75] (See Appendix C) that are useful in signal-probability calculations [76][77][78][79][80][81][82][83][84][85][86] as they transform on a one-toone basis to the probability domain, namely ...
... The model of memory with stuck-at defects has received attention also in computer architecture community and several computer architecture approaches were proposed to handle stuck-at defects [27]- [31]. These computer architecture approaches have been motivated by the following observations: ...
... The mixer module is a DX generator [103], whose output is as follows: [104] (CLS) and End-Around Carry Adder [105] (ECA) to optimize the multiplication operations. They finally suggest to choose a reseeding period that must be not only prime, but also not a multiple of the nonlinear chaotic map PRNG. ...
... A method for calculation of the length of testing sequence required for fault detection with the given probability in the mode of autonomous checking where the automaton is driven in a special mode of testing was described in [2]. It relies on constructing a special R + 1-state Markov chain, where R is the number of states of the checked automaton. ...
