Jaehoon Song's research while affiliated with Hanyang University and other places

Today's System-on-a-Chip (SoC) is designed with reusable IP cores to meet short time-tomarket requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, an efficient parallel scan test technique is introduced to minimize the test application time. Multiple scan enable signals are adopted to implement scan architecture to achieve optimal test application time for the test patterns scheduled for concurrent scan test. Experimental results show that testing times are considerably reduced with little area overhead.

In the deep sub-micron ICs, growing amounts of on-die memory and scaling effects make embedded memories increasingly vulnerable to reliability and yield problems. Spare columns are often included in memories to repair defective cells or bit lines during production test. In many cases, the repair process will not use all spare columns. Schemes have been proposed to exploit these unused spare columns to store additional check bits which can be used to reduce the miscorrection probability for triple errors in single error correction -- double error detection (SEC-DED). These additional check bits increase the dimensions of the parity check matrix (H-matrix) requiring extra area and delay overhead. A method is proposed in this paper to efficiently fill the extra rows of the H-matrix on the basis of similarity of logic between the other rows. Optimization of the whole H-matrix is accomplished through logic sharing within a feasible operating time resulting in the reduced area and delay overhead.

The effect of crosstalk-induced errors becomes more significant in high-performance circuits and systems. In this paper, compact crosstalk test patterns are introduced for a system-on-a-chip and board level interconnects considering physically effective aggressors. By being able to target multiple victim lines, 6 n , where n is the number of nets patterns are drastically reduced to a constant number 6 D , where D indicates the effective distance among interconnect nets. The test quality for static and crosstalk faults are completely preserved with 6 D patterns.

Today's system-on-a-chip (SoC) is designed with reusable intellectual property cores to meet short time-to-market requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, an efficiently testable design technique is introduced for an SoC with an on/off-chip bus bridge for the on-chip advanced high-performance bus and off-chip peripheral-component-interconnect bus. The bridge is exploited by maximally reusing the bridge function to achieve efficient functional and structural testing. The testing time can be significantly reduced by increasing the number of test channels and shortening the test-control protocols. Experimental results show that area overhead and testing times are considerably reduced in both functional- and structural-test modes. The proposed technique can be extended to the other types of on/off-chip bus bridges.

This poster presents an efficient secure scan design based on a fake key to protect a secret key from scan-based side channel attack. This technique targeted for an SoC embedding an Advanced Encryption Standard (AES) core can be adopted without requiring any modification to the functional body of the IP core, thus overheads for area, timing, and power are negligible while preserving the compatibility with the IEEE1149.1 standard.

In this paper, a reduced-pin-count-testing technique is presented to control the IEEE-1500 wrapper through the IEEE-1149.1 TAP for scan delay test. By using only the IEEE- 1149.1 TAP control pins as test-access pins and by embedding an on-chip test clock generator, low-cost automated test equipment (ATE) can be efficiently utilized to reduce testing costs. Experiments show the effectiveness of our technique in utilizing the ATE channels and scan delay testing.

The large test data volume and power consumption are major problems in testing system-on-a-chip (SoC) which is a key component of today's embedded system. To reduce the test application time from an automatic test equipment (ATE), a new test data compression technique is proposed in this paper. Don't-cares in a pre-computed test cube set are assigned to reduce the test power consumption. Then, fully specified low-power test data is transformed to improve compression efficiency by neighboring bit-wise exclusive-or technique. Finally, test set converted is compressed to reduce test application time.

This paper introduces an efficient test access mechanism for advanced microcontroller bus architecture (AMBA) based SoC to reduce the test application time while minimally adding a new test interface logic. Testable design technique is applied to an SoC with the advanced high-performance bus (AHB) and PCI bus bridge by maximally reusing the bridge functions. Testing time can be significantly reduced by increasing the test channels and by shortening the test control protocols. Experimental results show that area overhead and testing times in both functional and structural test modes are considerably reduced.

It becomes crucial to test and verify embedded hardware systems precisely and efficiently. For an embedded System-on-a-Chip (SoC) comprised of multiple IP cores, various design techniques have been proposed to provide diverse test access link configurations. In this paper, a Flag-based Wrapped Core Link Controller (FWCLC) is introduced to enable efficient accessibility to embedded cores as well as seamless integration of IEEE 1149.1 TAP’d cores and IEEE 1500 wrapped cores. Compared with other state-of-the-art techniques, our technique requires no modification on each core, less area overhead, and provides more diverse link configurations for design-for-debug as well as design-for-test.

A test interface controller (TIC) provided by ARM Ltd. is widely used for functional testing of system-on-a-chip (SoC) which adopts an advanced microcontroller bus architecture (AMBA) bus system. Unfortunately, this architecture has the deficiency of not being able to concurrently shift in and out the structural scan test patterns through the TIC and AMBA bus. This paper introduces a new AMBA based test access mechanism (ATAM) for speedy testing of SoCs embedding ARM cores. Since scan-in and out operations can be performed simultaneously, test application time on the expensive automatic test equipment (ATE) can be drastically reduced while preserving the compatibility with the ARM TIC.