Dirk Koch's research while affiliated with Universität Heidelberg and other places

As semiconductor technology advances and transistor feature sizes shrink, the increasing significance of process variation poses critical challenges to the reliability of semiconductor devices. This paper thoroughly explores the impact of process variation within the Clock Regions (CRs) of AMD-Xilinx UltraScale+ devices. We employ a novel method to characterize process variation with significantly higher precision than conventional ring oscillator (RO)-based sensors. Our experimental findings on ZYNQ XCZU9EG reveal that the latency of resources during rising and falling transitions may differ. Additionally, the proximity of Interconnect (INT) tiles to various tile types can influence the latency of resources within a column in a given CR. Moreover, we demonstrate that specific segments within CRs consistently exhibit faster performance compared to other areas within the same CR.

The memory subsystem is often the main performance bottleneck in an FPGA acceleration system. This paper presents two memory-aware runtime schedulers that decide the order of running tasks to improve the system’s performance: memory model-aware (MMA) and memory access pattern-aware (MAPA) schedulers. The proposed approaches consider memory characteristics in scheduling decisions to alleviate the memory overhead and enhance the system’s performance. MMA considers the accessed memory regions when scheduling the tasks in a way that reduces the memory page miss rates. On the other hand, MAPA alleviates the pressure on the memory subsystem by scheduling the tasks mainly based on their memory intensity and access patterns. The proposed runtime schedulers are evaluated and implemented on an Ultra96 FPGA board. The presented approaches show (on average) approximately \(10\%\), \(22\%\), \(12\%\), and \(9\%\) improvements in memory throughput, task execution time, makespan time, and job throughput, respectively, over an existing state-of-the-art memory-agnostic scheduler.

From better resource pooling for FPGA cloud providers to building dynamic execution pipelines at runtime, the capabilities of partial reconfiguration (PR) are waiting to be fully explored. However, the community still fails to materialize PR at scale, and FPGAs are only used as updatable ASICs, hence, omitting the opportunities offered by dynamically reconfiguring FPGAs at runtime. This work proposes a resourceful FPGA bitstream manipulation framework. The proposed tool provides means for parsing, modification, and generation of bitstream files, and it has been open-sourced and demonstrated in a working system. As a distinguished feature, it supports multi-die FPGAs (among the 106 Xilinx 7 Series, UltraScale, and UltraScale+ devices), and enables datacenter FPGAs to be used for relocatable PR. Using the versatile tool's built-in (dis)assembler allows for manual bitstream manipulations. Bundled with an efficient bitstream manipulation core, the efficacy is demonstrated by two case studies where we observe 58-377x higher bitstream merging throughput than a current state-of-art tool.

FPGAs have demonstrated substantial performance and energy efficiency advantages for workloads that fit a stream processing model with direct module-to-module communications. However, when the dataflow processing system is required to adapt to runtime conditions, current static acceleration solutions are limited in how efficiently the FPGA can be utilized due to the inability to switch out idling modules. To better use FPGAs in dynamic scenarios, this paper proposes using partial reconfigura-tion to stitch together different physically implemented operator modules on-the-fly. Rather than using designated module slots, our system places all modules and routing wires into a shared region with more placement options to minimize fragmentation. Furthermore, we use a module library that provides different resource and performance trade-offs for faster execution while considering the configuration cost. Then our system finds the optimal set of modules while scheduling multiple acceleration requests and managing all constraints transparently to the end-user. We demonstrate that the overheads of the middleware are insignificant enough to form accelerators with end-to-end execution times equal to hand-crafted static systems with small datasets while being 7.2× faster when streaming large datasets. We exemplified our approach for database acceleration, where the whole operation is abstracted to execute SQL queries directly.

See published version: https://www.researchgate.net/publication/365276026

FPGAs are efficient at dataflow applications, as demonstrated in various application domains, including machine learning, communication, and image processing. In this demo, we accelerate database management operations transparently to the user by stitching together partially reconfigurable stream processing modules that implement database operators. Our runtime system orchestrates this, which builds custom pipelines according to runtime conditions. This demo will showcase an acceleration of SQL queries using our dynamic stream processing system running on a ZCU102 FPGA board.