Impact of the Physical Layout of High-Current Rectifiers on Current Division and Magnetic Field Using PEEC Method

Abstract

This paper addresses some problems linked to the physical layout of high-current rectifiers: paralleling components, magnetic field close to the rectifier, and also the validation of the physical layout at reduced current. Even if the impact of cabling stray inductance is well known, some new tools and methodology are available today to design quicker and safer physical layout of such high-current rectifiers.

Full text

892 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 46, NO. 2, MARCH/APRIL 2010
Impact of the Physical Layout of
High-Current Rectifiers on Current Division
and Magnetic Field Using PEEC Method
Jean-Luc Schanen, Senior Member, IEEE, Jean-Michel Guichon, James Roudet,
Cyril Domenech, and Luc Meysenc
Abstract—This paper addresses some problems linked to the
physical layout of high-current rectifiers: paralleling components,
magnetic field close to the rectifier, and also the validation of the
physical layout at reduced current. Even if the impact of cabling
stray inductance is well known, some new tools and methodology
are available today to design quicker and safer physical layout of
such high-current rectifiers.
Index Terms—Circuit modeling, current distribution, electro-
magnetic compatibility, electromagnetic fields, power electronics,
rectifiers.
I. INTRODUCTION
ELECTROCHEMICAL process of aluminum involves high
dc currents provided by high-power rectifier–transformer
units (Fig. 1.) [1]. If the global behavior of these rectifiers
is well known, the physical layout is still a challenging
task for design engineers, since it impacts on several issues
simultaneously.
1) Device design normally supposes a good current share
between all SCRs of each secondary phase. However,
this current division is affected by the devices’ intrinsic
property (but chips are often selected individually for
high-power structures) and also by the layout of the
rectifier itself [1]–[4].
2) Devices’ cooling must be accounted for when choosing
the rectifier layout.
Paper 2008-PEDCC-243.R1, presented at the 2008 Industry Applications
Society Annual Meeting, Edmonton, AB, Canada, October 5–9, and approved
for publication in the IE EE TRANSACTIONS ON INDUSTRY APPLICATIONS
by the Power Electronic Devices and Components Committee of the IEEE
Industry Applications Society. Manuscript submitted for review November 28,
2008 and released for publication July 7, 2009. First published February 2,
2010; current version published March 19, 2010.
J.-L. Schanen, J.-M. Guichon, and J. Roudet are with the
Grenoble Electrical Engineering Laboratory (G2ELab), CNRS UMR 5269
INPG/UJF ENSE3, 38402 St. Martin d’Hères Cedex, France (e-mail:
jean-luc.schanen@g2elab.grenoble-inp.fr).
C. Domenech is with the Grenoble Electrical Engineering Laboratory
(G2ELab), CNRS UMR 5269 INPG/UJF ENSIEG, 38402 St. Martin d’Hères
Cedex, France and also with Schneider Electric France, Project and Engineering
Center, Project Management, 38100 Grenoble, France.
L. Meysenc is with Schneider Electric France, Project and Engineering
Center, Project Management, 38100 Grenoble, France.
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIA.2010.2041083
3) The restrictions on magnetic close field in the aluminum
plant and also near the rectifier are currently increasing.
This field map is obviously linked to the physical layout.
It is worth noting that the price and delays of such heavy
realizations do not allow any trial and error method in designing
the rectifier layout.
In addition, for such high-current converters, industry rarely
provides test facilities, and the rectifier behavior must be vali-
dated directly on the aluminum plant, which is always the most
exciting point of the business—if all works well! There is thus
a strong need of internal validation using smaller currents but
allowing an extrapolation to nominal behavior.
In this paper, it will be shown that the use of computer-aided
design tools associated with cabling rules can help in proposing
high-current rectifier layouts, fulfilling all constraints. In ad-
dition, the comparison of simulation results with several tests
at reduced current level will permit a first validation of the
structure and higher current extrapolation, before final testing
in the actual plant.
The main interest of the proposed approach is that it accounts
for all stray elements brought by the cabling structure without
any approximation. Usually, design rules are deduced from
conventional geometries by neglecting coupling coefficients
which are usually small in such layout. However, when chang-
ing the geometry during the design, this approximation may
become false, which could lead to a bad surprise when building
the rectifier. This may be all the more important in future
automatic design procedures, where the optimization process
may converge to a bad solution if a specific phenomenon has
not been taken into account.
However, the complete design rules accounting for all the
coupling inside the cabling geometry are useless if the im-
pedance matrix of the topology cannot be computed and au-
tomatically associated to the electrical equivalent circuit. This
is achieved using partial element equivalent circuit (PEEC)
method [5]. This electromagnetic modeling directly results in
an equivalent circuit composed of resistors, inductors, and
coupling. It is particularly well adapted to industrial system
with large size and complex 3-D geometries. Contrary to finite
element method (FEM), this integral method does not need the
meshing of the air, and only the conductors are subdivided. In
addition, the computation of the complete impedance matrix
using FEM is heavy and necessitates several resolutions using
various excitation sources.
0093-9994/$26.00 © 2010 IEEE
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Author manuscript, published in "IEEE Transactions on Industry Applications 46, 2 (2010) pp892-900"

SCHANEN et al.: IMPACT OF PHYSICAL LAYOUT OF RECTIFIERS ON CURRENT DIVISION USING PEECMETHOD 893
Fig. 1. Basic rectifier topology.
This paper will first investigate paralleling component issues
and particularly recall the impact of transformer leakage induc-
tance and layout parasitic. In addition, constraints on the matrix
impedance representing the rectifier layout will be established.
They may be useful to characterize and even optimize the layout
(Section II). Then, close field computation will be addressed
(Section III). In Section IV, the example of a 40-kA booster
will be proposed to illustrate the methodology.
II. PARALLELING DEVICE ISSUES
The problem of paralleling several devices is well known
and has been studied with the beginning of the rectifiers [1].
For high power, the components can be selected individually
in order that their characteristics match together. Therefore,
potential dissymmetry is due to cabling only. Different im-
pedance between the semiconductors and also mutual couplings
initiate dynamic differences between all components [1]–[4].
Still today, even if all the reasons of current imbalance are (or
at least, should be) understood, the inverse problem is not easy
to solve: how to find the right geometry to provide symmetrical
electrical characteristics, even accounting for mutual coeffi-
cients? Simulation can provide useful results to achieve this
task. Indeed, even a geometrical symmetry does not guarantee
symmetrical impedance matrix when accounting for all mutual,
as will be shown in Section IV. Approximations proposed in
[1] to simplify the computation may become wrong for modern
rectifier with high integration ratio.
A first analysis of dynamical effects can be proposed in
order to investigate the problem of current division (Fig. 2.).
During the commutation from one phase to the other, encroach-
ment phenomenon occurs, mainly due to leakage inductance
of the transformer. Global dI/dt of a phase is thus fixed, but
the repartition between elementary components in each phase
depends on the current divider formed by the cabling stray
impedances. Stray impedance and mutual coupling must thus
be accounted. It is worth noting from this simple model that
all mutual inductance between all conductors have an impact,
which is usually neglected in conventional design where all
phase legs are designed independently. The higher level of
integration will perhaps lead to the necessity of accounting
for all mutual couplings during the design, including the other
phases of the converter.
Cabling rules, based on the same idea as [1] but without
any assumption, have been proposed in [6] and can be adapted
here, starting from the equivalent circuit of Fig. 2. To obtain
Fig. 2. Equivalent circuit during encroachment (all mutual inductances are not
displayed).
synchronized turn on, all diode voltage of the same leg must
be similar: this impacts on several mutual values and can be
summarized with a simple cabling rule, which must be fulfilled
due to the physical layout. Let us call K and L as two phases
of the rectifier. Phase K has ndiodes and phase L has m
(usually, m=n, but the formulation is general). At the end of
the conduction of phase K, just before phase L is being turned
on, all diode voltages of phase L are expressed as a function of
all current and impedance parameters
⎡
⎢
⎢
⎣
Vd1
Vd2
.
.
.
Vdm
⎤
⎥
⎥
⎦L
=
⎡
⎢
⎢
⎣
....
..
Mij
....
..
⎤
⎥
⎥
⎦·d
dt
⎡
⎢
⎢
⎢
⎢
⎣
Iphase
Id1
Id2
.
.
.
Idn
⎤
⎥
⎥
⎥
⎥
⎦K
.(1)
[Mij ]represents the mutual inductance matrix between the
legs of phase L and all other conductors where current is flow-
ing, including phase K. Iphase is the total current of phase K,
and Id1...Idnare the currents of each diode of phase K.
First, all voltage Vd1...Vdm must be equal. Second, as-
suming that the final layout will fulfill all conditions to have
balanced currents, it can be supposed that Idi =Iphase/n.
Therefore, (1) can be rewritten as
⎡
⎢
⎢
⎣
Vd
Vd
.
.
.
Vd
⎤
⎥
⎥
⎦L
=
⎡
⎢
⎢
⎣
....
..
Mij
....
..
⎤
⎥
⎥
⎦·
⎡
⎢
⎢
⎢
⎢
⎣
1
1/n
1/n
.
.
.
1/n
⎤
⎥
⎥
⎥
⎥
⎦·dIphase
dt K.(2)
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894 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 46, NO. 2, MARCH/APRIL 2010
Equation (2) can be expressed as mcabling rules between
mutual coefficients of the considered phase and the rest of the
structure.
When all diodes are in the ON state, obtaining the same
currents necessitates fulfilling another set of rules, including
both mutual inductance and stray impedance [6]
⎡
⎢
⎢
⎣
Vm
Vm
.
.
.
Vm
⎤
⎥
⎥
⎦L
=
⎡
⎢
⎢
⎣
....
..
Zij
....
..
⎤
⎥
⎥
⎦·d
dt
⎡
⎢
⎢
⎢
⎢
⎢
⎢
⎢
⎢
⎢
⎣
Iphase
Id1K
.
.
.
IdnK
Id1L
.
.
.
IdmL
⎤
⎥
⎥
⎥
⎥
⎥
⎥
⎥
⎥
⎥
⎦
.(3)
Voltages V1...Vm are the leg voltages of phase m.All
paralleled legs have the same voltage. Matrix [Zij]links these
voltages Vmto all currents of the structure: IdiK, currents of
each leg of phase K; IdiL, currents of each leg of phase L; and
Iphase, the global current. Assuming that the final layout will
allow equal current division, this leads to IdiK =Iphase/n,
and IdiL =Iphase/m. Therefore, (3) can be expressed as
⎡
⎢
⎢
⎣
Vm
Vm
.
.
.
Vm
⎤
⎥
⎥
⎦L
=
⎡
⎢
⎢
⎣
....
..
Zij
....
..
⎤
⎥
⎥
⎦·
⎡
⎢
⎢
⎢
⎢
⎢
⎢
⎢
⎢
⎢
⎢
⎣
1
1
n
.
.
.
1/n
1/m
.
.
.
1/m
⎤
⎥
⎥
⎥
⎥
⎥
⎥
⎥
⎥
⎥
⎥
⎦
dIphase
dt .(4)
The same as (2), (4) corresponds to a set of mconditions on
impedance matrix [Zij].
Even if these two sets of cabling rules cannot be used directly
to find a proper layout for an inverter, they have been obtained
without any assumption and therefore account for all couplings
inside the system.
They can be used to qualify a tentative layout, or even in an
optimization process, to provide the “best” layout. Such proce-
dures have been validated successfully in other applications [7].
Obtaining the complete impedance matrix of the
system—necessary for the extraction of [Mij]and [Zij]—
starting from the rectifier geometry is quite simple using
the PEEC method [5], [8]. This modeling method allows
attributing to each part of a circuit a portion of the complete
loop inductance. The complete geometry is thus decomposed
into several massive segments or bars. Analytical formula can
be used to determine all inductance and mutual values, starting
from the bar geometry only. To account for frequency effects,
each bar can be meshed into elementary conductors. The final
impedance matrix results from the association of all segments
at desired frequency (Fig. 3).
III. CLOSE FIELD MAGNETIC RADIATED EMISSION
This issue has today become more and more of a challenge
and must be accounted for by new rectifiers. Indeed, due to
high currents circulating in the system, the magnetic field in
Fig. 3. Illustration of PEEC Method.
the vicinity may be huge. Compensating loops are used for
the complete plant, but they do not cancel the magnetic field
around the rectifier itself. Therefore, people entering into the
rectifier area may be exposed to magnetic fields exceeding the
maximum allowed values for human health. Even if the effects
are not well known, new standards begin to appear, and rectifier
manufacturers are strongly encouraged to anticipate this new
context. The same problem is encountered, for instance, when
building railway substations [9].
Additionally, high magnetic field may disturb all surrounding
electronics, particularly the control boards of the SCRs, and
all other control equipment. Therefore, the knowledge of the
magnetic field will become a key point of rectifier design in the
near future.
The main cause of magnetic field shape close to the rectifier
is due to cabling geometry. As mentioned in the Introduction,
FEM is not adapted for such large problems because it is
time and memory consuming. Consequently, PEEC method
will be preferred. Obtaining magnetic induction close to the
conductors is quite simple using this approach: After modeling,
the equivalent circuit is solved at desired frequency. Therefore,
all currents in the elementary subdivisions (assumed uniform)
are known. Then, Biot–Savard law can be easily used to com-
pute the magnetic field from each subdivision of each part
of the circuit since analytical formulation is available for an
elementary bar [10].
The magnetic field in all free spaces around the rectifier is
thus computed as the vector sum of all contributions of all
elementary conductors.
IV. 40-kA BOOSTER DESIGN
To illustrate how modeling can be useful in layout design,
we propose here a complete study of a booster, which is usually
used in aluminum plant for helping the main rectifiers. In
comparison with the main rectifier, the current rating of this
booster is low; however, 40 kA is still a challenging design
regarding current division. Eight SCRs are used for each leg.
Furthermore, since the testing facility is limited to 15 kA,
the complete rectifier will not be actually tested before being
installed in the actual plant, which makes the simulation partic-
ularly interesting.
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Fig. 4. Physical layout proposal and associated modeling.
A. Rectifier Structure
Fig. 4 shows a layout proposal for rectifier implementation,
as well as the electromagnetic modeling using PEEC method
[11]. The basic structure is as symmetrical as possible, using
a ladder structure (as proposed in [1]). Thermal management
is achieved using a simple solution: The mechanical support
for the SCR has also the electrical role of interconnection.
Furthermore, hollow bars are used, allowing liquid cooling.
This allows a homogeneous cooling between all SCRs. In
this case, the main cause of any temperature difference is
due to the power dissipation and thus, to current imbalance.
Electrothermal coupling has not been taken into account in the
modeling.
B. Modeling and Simulation
After modeling with PEEC method, an automatic circuit
extraction system to a circuit simulator [12] allows obtaining all
current waveforms in the components. Precise ON-state charac-
teristics have been taken into account, based on manufacturer
datasheets: Von = 0.85 V, Ron = 89 μΩ.
Transformer is also important in the model, since leakage
imposes the global current variation speed, as explained in
the previous section. Since two secondaries are needed, the
equivalent circuit is not obvious. Complete equivalent circuits
are available for multiwinding transformers [13], but they ne-
cessitate more data than usual datasheets.
The total number of parameters to represent the magnetic
coupling of a two-winding transformer would be six, since
it corresponds to three coupled inductors. Assuming the two
secondaries to be identical, we used the equivalent scheme of
Fig. 5. In this simplified scheme, only four independent parame-
ters are needed to represent the magnetic coupling, contrary to
the complete representation. Indeed, in the inductance matrix,
the two secondary inductances are identical, as well as the two
mutual inductances in the primary side. In the scheme of Fig. 5,
Lm represents the magnetizing inductance, L1and L2account
for the leakage, and ηis the no-load transformer ratio.
Identifying all elements necessitates two short-circuit volt-
ages Ucc1and Ucc2:1)Ucc1should have nominal current
when secondary 1 is short circuited and 2) Ucc2should have
nominal current when both secondaries are short circuited.
Fig. 5. Equivalent circuit used for one phase (all elements are on the
primary side).
Unfortunately, only Ucc2was given in the datasheet. We
therefore used the empirical relation between L1and L2:
L1/L2=R1/R2=1/4, which has been validated for various
transformers of such power.
The transformer had the following characteristics:
2∗2300 kVA (2300 kVA for each secondary winding);
primary voltage 11 000 V−secondary voltages 165 V;
Ucc2 = 8%;
Pcc2 = 76 000 W.
Based on Ucc2and Pcc2, we obtained
R1=0.14 Ω L1=2.15 mH
R2=0.56 Ω L2=8.6mH.
The temporal simulation results allow computing the average
and rms current mismatch, and current derating can be checked.
Fig. 6 shows the simulation results for phase 3, with the
current division between the eight SCRs for nominal current.
The geometrical implantation as well as the SCR numbers is
displayed on the top of this figure. The geometrical symmetry
has obvious consequences, since SCRs 1 and 4, 2 and 3, 5 and 8,
and 6 and 7 have the same behavior. However, it can be noticed
that the coupling between phases is important, since SCRs 1
and 5, and 2 and 6 do not carry the same current.
These different temporal waveforms induce different mean
and rms values, as illustrated in Table I. The derating is com-
puted with respect to the ideal case, where all SCRs would carry
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896 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 46, NO. 2, MARCH/APRIL 2010
Fig. 6. Top: rectifier structure and SCR reference. Bottom: example of current
division among the eight SCRs for phase 3 and a 46-kA current (simulation).
the same current. For a load current of 46 545 A (corresponding
to simulation conditions), the reference mean and rms currents
can be easily computed, based on the normal behavior of this
structure (each secondary sees Idc/2during a third of the
period)
Iavg/SCR =46545
2·8·1
3= 970 A
Irms/SCR =46545
2·8·1
√3= 1680 A.
The worst case of current division is for phase 2 and phase 1.
This can be explained by their position in the rectifier and the
impact of couplings with the rest of the structure. However, the
overall derating is below 30%, which is reasonable. Indeed,
the cooling system has been designed to account for a missing
SCR in case of a fault. With safety margin, this corresponds to
a 40% derating.
Another way of investigating the quality of the proposed
layout is to check the cabling rules presented in Section II. This
is all the more interesting because it avoids the heavy process of
modifying the geometry, then running a long temporal simula-
tion, analyzing the results, and modifying the geometry again....
The proposed cabling rules keep the link between the geometry
and electrical characteristics and therefore, are suitable to build
an optimization process: The geometry will be modified accord-
ing to the cabling rule criteria using an appropriate optimization
algorithm. This solution has been carried out successfully in
another application [7]. In this case, however, this has not been
necessary since the SCR derating was considered acceptable.
TAB L E I
MEAN AND RMS CURRENTS OF ALL PHASES
Fig. 7. Two full-bridge rectifiers feeding the same dc load. Only one has been
considered for modeling. Each diode function is composed of four physical
components.
Another application can be presented to illustrate the impact
of a bad layout on the current division. This time, the rectifier
is a conventional full-bridge topology. Two different rectifiers
are used to feed the same dc load through the conventional in-
terphase inductors (Fig. 7). The two converters are far enough;
therefore, the mutual coupling between the two structures can
be neglected, and only one rectifier has been studied.
Each diode function is realized using four diodes. The aim of
the study is to investigate the impact of the rectifier layout on
the current division. The complete layout, described in Fig. 8,
has been modeled using the PEEC method, and the cabling
rules (2) and (4) applied to this rectifier exhibit worse result than
the previous rectifier. The time simulations (Fig. 9 and Table II)
confirm this result, since the current division is poor (more
than 37% derating). The explanation can be attributed to the
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Fig. 8. The rectifier layout with the three phases and four diodes per phase.
Fig. 9. Current division among the four diodes of phase 1 (simulation results).
TAB L E I I
RMS CURRENTS OF ALL FOUR DIODES OF PHASE 1
Fig. 10. Current division among the four diodes of phase 1 without any
coupling between the phases and the dc bus (simulation results).
nonsymmetrical layout of the rectifier: Diodes 1 and 2, located
close to the phase input, carry more current than diodes 3
and 4, which are far away. Additionally, the study of the
impedance matrix has shown the importance of the couplings
between the dc bus conductors and the phase conductors even
if they are small, since the main directions are perpendicular.
This is confirmed by the simulation results of Fig. 10, where
these couplings have been mathematically cancelled. It shows
the interest of the presented complete analysis without any
assumption.
Fig. 11. View of the complete rectifier.
Fig. 12. Comparison of simulated and experimental results for SCR #6 of
phase 1 in the case of a 10-kA test with two SCRs.
C. Experimental Validation
Several “low current” (10 and 15 kA) validations have been
carried out on the actual rectifier (Fig. 11) to check the validity
of the simulation (e.g., Figs. 12 and 13) and to validate the
cooling aspects. At 10 kA, only two SCRs per phase were kept
to validate the cooling.
The “low power” transformer was identified, since it was ob-
viously different from the one designed for the 40-kA rectifier,
and a new set of temporal simulations was carried out.
Fig. 12 shows the very good agreement between measured
current in SCR #6 of phase 1. Experimental conditions were
Idc =10kA, obtained in a short circuit with a firing angle of
71◦and only two SCRs (5 and 6). Other measurements with
SCRs 1 and 2 have also given the same good results. Fig. 13
shows the superposition of simulated and measured currents in
SCRs 1 and 2 of phase 1 in the same operating conditions. In
this case, the current division is not as bad as in the simulation
of Fig. 6, since the operating conditions are different: The
transformer is not the same, the current level is lower, and all
SCRs are not used.
Some experimental results were also achieved at 15 kA with
all SCRs, but all currents could not be recorded due to the
number of current probes and space needed. The measurement
of voltage drop across the fuses in series with the SCR allows a
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898 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 46, NO. 2, MARCH/APRIL 2010
Fig. 13. Comparison of simulated and experimental results for SCRs 1 and 2
of phase 1 in the case of a 10-kA test with two SCRs. Solid lines: simulation.
Cross: measurement.
Fig. 14. Grid definition for magnetic field computation.
rough estimate of the current flowing through the device. This
has confirmed the tendency obtained in the simulation: The
most loaded devices are the external ones (1 and 4, and 5 and 8).
In conclusion, the good agreement between current commu-
tation speed in one SCR validates the PEEC model of the rec-
tifier because it is only due to cabling impedance. Furthermore,
the tendency when using all eight SCRs has also been validated.
D. Close Field Map
After the converter modeling validation, we focused on near
magnetic field. The field spectrum obviously contains not only
a dc part but also ac components, due to the waveforms of
the SCR currents. By using Fourier series, the ac magnetic
field can be obtained by superposition of several field maps at
various frequencies representing the harmonic decomposition
of the SCR currents. Due to the decrease of harmonic amplitude
with the order, we only focused on the fundamental component
(50 Hz). It is worthy of note that the dc field is much more
restrictive for all the control boards of the SCRs and the
electrical cabinets.
1) Positioning of the Cartography Grids: Magnetic induc-
tion was computed and plotted on a grid and shown in Fig. 14.
Three different distances were defined in order to investigate
the decrease of the field with the distance (0.5, 1, and 1.5 m).
Fig. 15. DC Induction at (top) 0.5 m and (bottom) 1.5 m obtained with PEEC
method.
The height of the grid has been chosen 3 m higher than a human
being.
Some results are shown on Fig. 15 for dc component and
Fig. 16 for the 50-Hz ac field. It is worth noting that the
induction global shape is more complex near the rectifier than
far from it.
This can be explained by the multipole expansion theory
[14]: Far from a radiating source, only the dipole term is
preponderant, whereas near the device, higher orders appear.
Compared with dc, the induction shape is changed at 50 Hz,
as shown in Fig. 16. This is due to the different localization of
ac currents compared with dc currents.
All results are summarized in Table III. Induction stays at
low values at any distance and frequency, which is reassuring
for human exposure (service engineering). Furthermore, control
boards of SCR have been tested at 150-gauss dc fields without
any problem.
V. C ONCLUSION
High-current rectifier layout impacts on several aspects and
mainly on current division, as well as on induction radiated
around the converter. Even if the problem of current division
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Fig. 16. AC induction at 0.5 m (50 Hz) obtained with PEEC Method.
TABLE III
SUMMARY OF MAXIMUM AND MINIMUM INDUCTION VALUES
has been known since tens of years, new modeling tools allow
a better precision for layout investigation. The PEEC method is
well adapted for this purpose. It provides an electrical equiva-
lent circuit of the converter layout. A coupling with simulation
software allows a direct analysis of temporal current wave-
forms. Cabling rules have also been presented: Starting from
the equivalent modeling of the converter, they give restrictions
on the impedance matrix of the system in order to guarantee a
good current division. The use of these rules allows avoiding
temporal simulation and opens the possibility of automatic
layout optimization of such high-power rectifiers. The proposed
Fig. 17. Flowchart of the proposed design procedure.
design procedure is shown in Fig. 17. A tentative layout can be
quickly evaluated owing to the proposed cabling rules; when
it is considered satisfying, a temporal simulation can be car-
ried out, and electrical performances checked. Then, magnetic
induction limits close to the rectifier can be investigated and
compared with existing or future standards. This may allow
much savings in such high-power engineering design activities.
An optimization process can even be proposed in the near
future: The layout geometry may be the result of automatic
design; the objective function being the proposed cabling rules.
This has been achieved successfully in other applications [7]:
The main difficulty is to describe the complex 3-D geome-
try and all associated constraints with a sufficient number of
parameters.
REFERENCES
[1] D. A. Paice, “Multiple paralleling of power diodes,” IEEE Trans. Ind.
Electron. Control Instrum., vol. IECI-22, no. 2, pp. 151–158, May 1975.
[2] R. Fuentes and L. Neira, “Current distribution in paralleled
thyristors—A comparative analysis of 5 real cases in high current
transformer–Rectifiers,” in Conf. Rec. IEEE IAS Annu. Meeting, Seattle,
WA, 2004, p. 476.
[3] R. Fuentes, “Effects of layout on current distribution in paralleled thyris-
tors of high current rectifiers,” in Proc. PCIC, 2007, pp. 1–6.
[4] E. Clavel, J. Roudet, J.-L. Schanen, and A. Fontanet, “Influence of the
cabling geometry on paralleled diodes in a high power rectifier,” in Conf.
Rec. IEEE IAS Annu. Meeting, San Diego, CA, 1996, pp. 993–998.
[5] A. E. Ruehli, “Inductance calculations in a complex integrated cir-
cuit environment,” IBM J. Res. Develop., vol. 16, no. 5, pp. 470–481,
Sep. 1972.
[6] J.-L. Schanen, C. Martin, D. Frey, and R. Pasterczyk, “Impedance cri-
terion for power modules comparison,” IEEE Trans. Power Electron.,
vol. 21, no. 1, pp. 18–26, Jan. 2006.
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[7] C. Martin, J. M. Guichon, J. L. Schanen, and R. Pasterczyk, “Gate
circuit layout optimization of power module regarding transient current
imbalance,” IEEE Trans. Power Electron., vol. 21, no. 5, pp. 1176–1184,
Sep. 2006.
[8] C. Paul, Introduction to EM Compatibility. New York: Wiley-
InterScience, 1992.
[9] P. Mariscotti, “Low-frequency magnetic field in DC railway substations,”
IEEE Trans. Veh. Technol., vol. 53, no. 1, pp. 192–198, Jan. 2004.
[10] L. Urankar, “Vector potential and magnetic field of current-carrying finite
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Nov. 1982.
[11] InCa-Cedrat Software—Cedrat, Meylan, France. [Online]. Available:
www.cedrat.com
[12] Portunus Software–Cedrat, Meylan, France. [Online]. Available:
www.cedrat.com
[13] X. Margueron and J. P. Keradec, “Identifying the magnetic part of the
equivalent circuit of n-winding transformer,” in Proc. IMTC, Ottawa, ON,
Canada, May 2005, pp. 1064–1069.
[14] B. Vincent, O. Chadebec, and J. L. Schanen, “Multipolar expansion sen-
sors for near field characterization,” in Proc. IEEE-EMC Eur.,Hamburg,
Germany, Sep. 8–12, 2008, pp. 1–4.
Jean-Luc Schanen (M’99–SM’04) was born in
1968. He received the Diploma in electrical engi-
neering and the Ph.D. degree from Grenoble Institute
of Technology, Grenoble, France, in 1990 and 1994,
respectively.
He is currently a Professor at Grenoble Institute
of Technology. He has been with the Grenoble Elec-
trical Engineering Laboratory (G2ELab), St. Martin
d’Hères, France, since 1994, working in the field
of power electronics. His main activities concern
the technological design of power converters. His
research team uses (or develops, if not available) all kinds of modeling tools
in order to improve the performance of power electronics converters, including
electromagnetic compatibility and thermal aspects.
Prof. Schanen is a Senior Member of the IEEE Power Electronics Society
and IEEE Industry Applications Society, and was Chairman of the Power Elec-
tronics Devices and Components Committee of the IEEE Industry Applications
Society between 2006 and 2007.
Jean-Michel Guichon was born in 1975. He re-
ceived the Diploma in electrical engineering and
the Ph.D. degree from Grenoble Institute of Tech-
nology, Grenoble, France, in 1998 and 2001,
respectively.
He is an Associate Professor at the Université
Joseph Fourier, Grenoble, France. He has been
with the Grenoble Electrical Engineering Laboratory
(G2ELab), St. Martin d’Hères, France, since 2003,
working in the field of power electronics. He is in-
volved in the development of design tools for power
electronics, in particular, electromagnetics formulations.
James Roudet was born in 1963. He received the
Diploma in electrical engineering in 1986 and the
Ph.D. degree in 1990, both from Grenoble Institute
of Technology, Grenoble, France
He is a Professor at Grenoble University (Uni-
versité Joseph Fourier), Grenoble, working within
the Grenoble Electrical Engineering Laboratory
(G2ELab), St. Martin d’Hères, France, in the field
of power electronics. He currently holds the Director
position in the G2ELab after several years of leading
the power electronics team. His first research interest
concerned resonant converters. Later, he promoted EMC activities in the field of
power electronics and developed a leading activity in the technological design
of power converters.
Cyril Domenech was born in 1982. He received the
M.S. degree in electrical engineering from Grenoble
Institute of Technology, Grenoble, France in 2007.
He is currently with Schneider Electric Industry,
Grenoble, France, as a Testing Engineer for low-
voltage products. After his internship working on the
modeling of high-power rectifier transformer units
using PEEC method, he joined Schneider Electric
to carry out tests of development, certification, or
quality control on low-voltage products like circuit
breakers, contactors, fuses, and bus bars.
Luc Meysenc was born in 1969 in Grenoble, France.
He received the Diploma in electrical engineer-
ing and Ph.D. degree from Grenoble Institute of
Technology, Grenoble, France, in 1995 and 1998,
respectively.
From 1997 to 2000, he was with Alstom Trans-
port, Tarbes, France, where he managed the power
module thermal laboratory and an R&D team dealing
with power integration. From 2000 to 2005, he was
with ABB Corporate Research, Baden, Switzerland,
where he managed the power electronics R&D
activity. Since 2005, he has been with the Schneider Electric Project and
Engineering Center, Grenoble, France, working to develop high current
rectifiers, and where, since 2007, he has been managing the power business
R&D activity. His fields of interest are power electronics conversion, power
system management, and thermal management.
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