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A 77 GHz SiGe power amplifier for potential applications in automotive radar systems
Abstract
We present the performance of a 77 GHz power amplifier for potential applications directed towards automotive radar systems. The circuit was fabricated in a SiGe bipolar preproduction technology. A balanced two-stage common emitter circuit topology was used to achieve 6.1 dB of power gain at 77 GHz and 11.6 dBm output power at 1dB compression. The power amplifier uses a single 2.5 V supply and was fully integrated (including matching elements) to demonstrate its low-cost potential. First experimental results show its broadband characteristic from 40 GHz to 80 GHz and its temperature dependence up to 130°C.
... A millimeter wave power amplifier (PA) design in CMOS processes has only recently gained research interest. Millimeter wave PA has been discussed in many researches [5][6][7]. In [5], Yao et al. developed three stages Class A power amplifier in common emitter topology. ...
... The millimeter wave PA relied on 300 Ω base resistance to raise the collector-emitter breakdown (BVcer) to 4 V by using power combining in the last stage to increase the output power. Later, Pfeiffer et al. in [7] developed 61.5 GHz transformer matched class AB power amplifier with single stage differential cascade topology, in which the cascade base was grounded to overcome the breakdown voltage and allow supply voltage 4 V. Hajimiri and Hajimiri in [6] and [8] developed a wideband PA at 77 GHz a peak power gain of 17.5 dB with 50 Ω input and output matching is fabricated in a 0.12 μm SiGe BiCMOS process [1]. However Komijani is optimized the PA to give wideband frequency while he did not give much concern for efficiency and gain. ...
In this paper, a new CMOS power amplifier that can operate at 70GHz is designed and developed. The advantages of using 70 GHz at millimeter wave (mmW) band is the huge amount of bandwidth available forvarious purposes whether they are in the cellular industry or manufacture devices such as high bandwidth wireless LAN and low attenuation of bandwidth frequencies around 70 GHz bands comparing with 60 GHz. Design power amplifiers at 70 GHz are quite challenges task. The complication such as the stability of the amplifier is difficult and hard to be achieved. In this paper, we design power amplifier with 3 singleended, common source stages biased in class A. The proposed circuitresulted in a stable power amplifier capable of working at 70 GHz frequency. The purpose of using three stages is not only to maximize gain but also to increase isolation against reflections. We found thatthisconfiguration has many advantages in terms of lower power supplyrequired, leading to higher efficiency and good linearity. The first stageis biased at a peak Fmax biased of 0.2 mA/μm to maximize the gain to 10.58 dB. The second and third stages are biased at optimum linearitycurrent density of 0.28 mA/μm.
... All stages are biased with current density of 0.7 mA m using digitally adjustable current mirrors, through a quarter-wave transmission line, shorted by a MIM capacitor at RF. This arrangement enables biasing of the CE stage above for improved linearity and allows better flexibility in layout placement of bias circuits [17]. The PA's output is capacitivly coupled to a power detector [9] with programmable dynamic range. ...
... 79GHz automotive radars for collision avoidance and adaptive cruise control (ACC) [1] that use Wband wireless transceivers have become popular. For such applications, a W-band RF front end is realized using compound semiconductors such as SiGe and InP [2][3]. On the other hand, MOSFETs using CMOS technology increase the maximum operation frequency (fmax) and maximum available gain (MAG). ...
We proposed a temperature compensation method for a CMOS power amplifier (PA) without an external feedback circuit. The 79GHz PA using temperature compensation bias was fabricated using 40nm CMOS technology and suppressed the variation of the small-signal gain and the degradation of linearity to within 0.6dB in the temperature range from 10 to 100C with a fixed bias voltage. The PA using temperature compensation bias achieved a small-signal gain of 6.0dB, a 23.5GHz bandwidth and a saturated output power (Psat) of 6.3dBm with 24.8mW power consumption at 100C.
... The suitability of Si/SiGe hetero-bipolar transistors (HBTs) for applications beyond 70 GHz has already been proven e.g. in12345. However, amplifiers at these frequencies use single-ended or double-balanced design architectures making the packaging highly critical. ...
In this work, the authors present a fully integrated, fully differential amplifier operating at 79 GHz using a high-speed Si/SiGe hetero-bipolar technology. This amplifier needs a single supply voltage and shows high performance such as high gain, excellent reverse isolation and low power consumption (90 mW at 3 V supply voltage). This result was achieved by using multi-stage cascode topology and a thin-film microstrip line based design. In addition, the frequency of operation can be easily adjusted within a wide range by changing the length of the matching network (by using focused ion beam or ultrasonic manipulator). A simple but efficient layout technique was used to easily measure single-endedly the differential integrated circuit, also at these high frequencies.
... However, CMOS has lower maximum available gain (MAG) at millimeter-wave band and cannot be applied high supply voltage for obtaining high-power output signal. Therefore, developing a CMOS transceiver at millimeter-wave band is still a challenging task for many researchers [8]- [11]. Since the radar systems built on printed circuit board (PCB) with discrete components are relatively expensive a single chip solution based on SiGe or CMOS can reduce the cost and achieve compact size [12]- [13]. ...
n this article we explore the coming consumer radar era, where tiny single-chip radar systems will be available for just a few dollars. These systems will use sophisticated waveform diversity and adaptive signal processing to optimize performance. Automotive radar concepts developed at the University of Melbourne are discussed, including CMOS RF transceivers, waveform and signal processing, and antennas.
... As mm-wave is finding its way into the portable consumer applications and the battery life is limited, high PAE PA are very desirable since they consume lower dc power. Most of the mm-wave PAs that are reported in the literature have very low reported PAEs[48] [39][40]; however, few PAs also reported to have PAEs above 10% at 60GHz and 77GHz[34][51].As we move toward sub-micron technologies, transistor sizes shrink and the digital portion of the chip becomes smaller and smaller; however, if we are to realize a single chip solution for the mm-wave system, RF part has to scale down too. However, passive structures do not scale with technology nodes. ...
... As an example of a future smart traffic system, an intersection radar system is being studied, which has to detect both cars and pedestrians. Recently, SiGe BiCMOS technology and SiGe HBT technology have been used for the 77 GHz automotive radars [1]- [2]. Since advanced MOSFETs using CMOS technology increase the maximum operation frequency (fmax) and maximum available gain (MAG), CMOS technology makes it possible to realize an automotive radar system [3]. ...
We have developed a 79 GHz CMOS power amplifier (PA) with temperature compensation implemented using 40 nm CMOS technology that suppresses the variation of small-signal gain and the degradation of linearity within 0.8 dB in the temperature range from 0 to 100°C. The PA consists of an on-chip temperature sensor and four-stage common-source NMOS amplifiers. The temperature-compensated PA operating at 100°C achieved a small-signal gain of 15.7 dB, a 12 GHz bandwidth and a saturated output power (Psat) of 6.8 dBm with 96.2 mW power consumption at a supply voltage of 1.1 V.
... I N T R O D U C T I O N In the last decade, integrated mm-wave SiGe circuits found their way from research (e.g. [1, 2] ) to mass-market applications in automotive radar sensors (e.g. [3, 4, 5]). ...
In this paper, radar transmitter circuits for next generation automotive radar sensors are presented. A 79 GHz radar transmitter with an output power of 14.5 dBm consuming only 165 mA (including frequency dividers) from a 3.3 V supply voltage clearly shows the advantage of using an improved SiGe technology with an f max of 380 GHz. In addition, two radar transmitters for higher frequencies (around 150 GHz) based on frequency doubler circuits are showing the potential of SiGe technologies. The first transmitter achieves an output power of 3 dBm (single ended) at 144 GHz, whereas the second transmitters delivers a differential output power of 0 dBm at 150 GHz. Both transmitters achieve an ultra-wide tuning range of about 45 GHz.
... I N T R O D U C T I O N In the last decade, integrated mm-wave SiGe circuits found their way from research (e.g. [1, 2] ) to mass-market applications in automotive radar sensors (e.g. [3, 4, 5]). ...
In this paper, radar transmitter circuits for next generation automotive radar sensors are presented. A 79 GHz radar transmitter with an output power of 14.5 dBm consuming only 165 mA (including frequency dividers) from a 3.3 V supply voltage clearly shows the advantage of using an improved SiGe technology with an f max of 380 GHz. In addition, two radar transmitters for higher frequencies (around 150 GHz) based on frequency doubler circuits are showing the potential of SiGe technologies. The first transmitter achieves an output power of 3 dBm (single ended) at 144 GHz, whereas the second transmitters delivers a differential output power of 0 dBm at 150 GHz. Both transmitters achieve an ultra-wide tuning range of about 45 GHz. In the last decade, integrated mm-wave SiGe circuits found their way from research (e.g. [1, 2]) to mass-market appli-cations in automotive radar sensors (e.g. [3, 4, 5]). For next generation radar sensors, it is important to further improve the performance of these circuits in order to reduce the costs and make them more reliable and more flexible for various sensors around a car. It was the goal of the (radar on chip for cars) RoCC project funded by the German Federal Ministry of Education and Research to further improve radar sensors and their appli-cations. This paper presents the project results of the circuit design work package of this project. One of the focuses was to demonstrate on circuit level, what improvements can be achieved at 79 GHz due to the improved npn-transistor on technology level, which was a focused topic in another work package of this project. These circuit level results at 79 GHz are presented in Section II. In Section III frequency doubler circuits exploiting radar transmitters at higher frequencies (around 150 GHz) are demonstrated. These circuits are based on Infineon's estab-lished B7HF200 production technology.
... Watson Research Center has used this technology and published several papers that present circuits for collision avoidance radar that operates in the 77 GHz range. The circuits in those published papers include a power amplifier (PA) [5], a voltage controlled oscillator (VCO), and a low noise amplifier (LNA) [6]. The circuits utilize on-chip transmission lines and capacitors for matching networks. ...
The paper demonstrates an efficient band CMOS LNA for satellite-based remote sensing application using 45 nm CMOS technology. The designed LNA comprises of a two stage cascode amplifier with shunt resistance feedback and dual inductive peaking (SRF-DIP) technique with source and gate inductive degeneration. The received band is 35.7 GHz that ranges from 61–96.7 GHz. The maximum power gain is 22.2 dB at resonant frequency of 74.7 GHz. The minimum noise figure is 1.25 dB at 60 GHz. The noise figure and power gains are calculated theoretically as well. The DC current Id is measured between 20–25 mA for the drain voltage of 0–1.2 V.
KeywordsTwo stage cascode amplifierShunt resistance feedbackDual inductance peaking
GaN-based high-electron mobility transistors (HEMTs) based power amplifiers (PA) have enjoyed commercial success in the microwave frequency spectrum (3–30 GHz) competing with silicon and silicon carbide-based transistors. However, low thermal conductivity of GaN limits the HEMT performance in the higher frequencies of millimetre-wave regime (30–100 GHz). This chapter uses the 2DEG in the AlN/GaN/AlN heterostructure as a channel in AlN HEMT-based mm-wave PAs. The high thermal conductivity of the AlN buffer layer, coupled with the highly quantum-confined, high-density 2DEG in this heterostructure, provide an advantage for high-power, mm-wave signal amplification. The state-of-art scaled AlN HEMTs demonstrate output powers of ∼2 W/mm at operating frequencies upto 94 GHz. The output powers in these HEMTs in these first-generation devices are limited by ∼ 20% dispersion due to the presence of carrier traps on the epitaxial surface. A path to higher output powers is presented through the demonstration of a unique in-situ AlN passivation technique which drastically reduces the RF-DC dispersion to 2–3%. Furthermore, enhancement-mode operation is demonstrated for the first time in AlN metal-oxide-semiconductor (MOS)-HEMTs for enabling complementary logic and RF circuits on the AlN platform. This is achieved by scaling the GaN channel layer of the AlN/GaN/AlN heterostructure down to 3 nm which results in a unique operation where just a 2DHG is present in the as-grown structure, but upon application of a positive gate bias a 2DEG is induced, which then acts as a channel for E-mode HEMTs. Future directions are provided to improve the performance of current AlN/GaN/AlN HEMTs state-of-art, such as incorporation of scandium aluminum nitride (ScAlN) as a high-K dielectric, AlGaN channels for higher breakdown voltages and utilizing the 2DHG as a backgate.KeywordsMBEGallium nitrideGaNAluminum nitrideAlNn-channelHEMTsElectrons2DEGPolarization-inducedmm-wavePower amplifiersPassivationRF dispersionE-modeD-modeT-gate
Gallium nitride high-electron-mobility transistors (GaN HEMTs) are at a point of rapid growth in defense (radar, SATCOM) and commercial (5G and beyond) industries. This growth also comes at a point at which the standard GaN heterostructures remain unoptimized for maximum performance. For this reason, we propose the shift to the aluminum nitride (AlN) platform. AlN allows for smarter, highly-scaled heterostructure design that will improve the output power and thermal management of III-nitride amplifiers. Beyond improvements over the incumbent amplifier technology, AlN will allow for a level of integration previously unachievable with GaN electronics. State-of-the-art high-current p-channel FETs, mature filter technology, and advanced waveguides, all monolithically integrated with an AlN/GaN/AlN HEMT, is made possible with AlN. It is on this new AlN platform that nitride electronics may maximize their full high-power, high-speed potential for mm-wave communication and high-power logic applications.
This paper evaluates the transformer and capacitor coupling used in W-band broadband CMOS power amplifiers. Therefore two four-stage differential power amplifiers were implemented in 40 nm CMOS technology one with transformer coupling and one with capcitor coupling. In order to achieve broadband performance a complex output matching network consisting either of transmission lines and transformer or transmission lines and capacitor is employed. The power amplifier core and output matching network are optimized for the best compromise between bandwidth, output power and power-added-efficiency. Both implementations are measured and compared to the state-of-the-art. For both cases a bandwith nearly over the whole W-band is realized. The transformer-coupled power amplifier achieves output power of 10 dBm with 10 % power-added-efficiency while the capacitor-coupled power amplifier shows output power of 8 dBm with 8 % power-added-efficiency.
The goal of this thesis is the analysis of the challenges and finding solutions for the design of mm-wave transceivers. The work presented here is focused on design of transmitter (TX) components, which are critical for the performance of the whole analog front-end. Phase-locked loop (PLL) phase noise is optimized, an image-rejection filter and a high 1 dB compression point (P1dB) power amplifier (PA) are designed. The PLL phase noise optimization is presented and different PLL topologies are compared. A new optimized recipe for calculating PLL parameters of a forth order PLL is presented. Using this approach the spurious sidebands can be reduced by up to 10 dB. The image-rejection filter chapter analyzes the challenges related to the design of the integrated image–rejection filter. The analysis presented here is the first on integrated filters for the 60 GHz band, because the previously published work dealt with on-board filters. The main problems related to the design of integrated filters arise from the low quality factor of the integrated resonators. The effects are high insertion loss and low selectivity. Two measures to reduce the insertion loss of the image–rejection filters were suggested. One is to design the filter as broadband. This measure deteriorates selectivity, so the minimum required image–rejection will limit the width of the passband. The second measure is to design the filter as broadband with non-equidistant transmission zeros (i.e. asynchronously tuned filter). This measure will improve both the insertion loss and the image–rejection. The challenges related to the design of mm-wave PAs with high P1dB are analyzed and the procedure of the PA design is presented. The difficulties related to the PA design and layout are discussed and optimum solutions presented. Limits of different power combining techniques for integrated PAs are discussed. Effects of poor on-chip ground connection are analyzed. Different causes for P1dB degradation are analyzed. The produced PA features a differential cascode topology. The layout is symmetrical and presents a virtual ground on the symmetry line for the differential signal. The optimized schematic and a symmetrically drawn layout resulted in a 17 dBm measured P1dB. It was the highest reported P1dB in 60 GHz SiGe PAs when it was published. The fully integrated TX was used for data transmission with data rate of 3.6 Gbit/s (with coding 4.8 Gbit/s) over 15 meters. This is the best result in the class of 60 GHz AFEs without beamforming.
This thesis presents the design and implementation of the RF power amplifiers in modern silicon based technologies. The main challenge is to include power amplifier on a single chip with output power level in watts, operating at high frequencies where the transit frequency (fT) is just a few times higher than the operating frequency. This work describes the design procedure for bipolar and CMOS transformer-based Class-A, Class-AB and Class-B power amplifiers. The design procedure is based on the HICUM for bipolar and BSIM4 for CMOS transistor models and is divided in four parts: •Building a one transistor prototype power amplifier which is based on the analytical analysis of the output characteristics and transistor model. •Load-pull simulation to define the final input and output impedances. •Derivation of the analytical equations for the transformer-based matching network. •Design of the final transformer-based push-pull power amplifier. A good agreement between the proposed analytical analysis and large-signal (harmonic balance) simulation results proofs usefulness of the proposed power amplifier design approach. Additionally, it shows the contribution of the separated devices at the final design that helps to find a technology limits in the current circuit design. The main achievements include: •A 2.4 GHz power amplifier in 0.13 um CMOS technology. An output power of 28 dBm is achieved with a power added efficiency of 48 % at a supply voltage of 1.2 V [Vasylyev 04]. •Two 17 GHz power amplifiers in 0.13 um CMOS technology (one fully integrated while the other with external matching network) with output power exceeding 50 mW. The former exhibits a power added efficiency of 9.3 % while the latter a 15.6 % power added efficiency [Vasylyev 06]. •A fully integrated K and Ka bands power amplifier in 0.13 um CMOS technology. A 13 dBm output power along with power added efficiency of 13 % is achieved at an operating frequency of 25.7 GHz with 1.2 V supply [Vasylyev 05,a]. •A fully integrated power amplifier based on a novel power combining transformer structure in 28 GHz-fT SiGe-bipolar technology. A 32 dBm output power along with power added efficiency of 30 % is achieved at an operating frequency of 2.12 GHz with 3.5 V supply [Vasylyev 05,b].
The emergent systems of “Smart dust” use networks of several hundreds of millimetre scaled devices. Each device integrates sensor and communication functions in order to be consulted by one or more transmitters.Regular progress in micro-technology and circuit's design accelerate the realization of compact devices containing one or more sensors, analogical and numerical circuits, communication systems and power source. One of the critical points of the system, object of many research tasks, is the communication system of the network of sensors. The objective of the thesis is to study a radio frequency communication system adapted to the needs of smart dust network. More precisely, it is a question of studying the feasibility of Emission-Reception devices functioning at the millimetre-length frequencies with principal constraints the reduced size and low power consumption of the system.
The first part provides a state of the art of the various components of a radiofrequency transceiver operating at millimetric frequencies. The second part is devoted to the study of SOI based interconnection structures, including coplanar strip and coplanar waveguide transmission lines. The third part deals with the case of a dipole integrated on SOI and operating at 60 GHz. This last study is based on the parameters of the SOI technology as permittivity, the resistivity and thickness of silicon. A model of the dummies of the SOI technology, based on the dynamic model of Tretyakov is proposed.
The final part is devoted to the design, implementation, and measurement of antennas integrated on SOI and operating in the 60 GHz band. Four types of antennas are presented including an interdigitated dipole, an IFA antenna, a double slot antenna and in the end a spiral antenna. These antennas were characterized and the comparison of the S parameters shows good correspondence between the measured and simulated results. In addition, a device test is presented to measure the gain pattern of these antennas. Finally, in an objective of a front end receiver, a codesign of a Low noise amplifier and an integrated antenna, both operating at 60 GHz, is proceed to eliminate the need of 50 ohms constraint.
This work focuses on the design of a power amplifier (PA) at 79 GHz and the co-integration of the PA and the antenna on SiGe technology. The objective of this thesis is to develop a RF front-end block for radar applications at 79 GHz. This block is compound of a power amplifier, antenna and PA/Antenna inter-stage matching. The inter-stage between the PA and the antenna adds supplementary losses in the global performances, especially prohibitive in integrated technology for high frequencies. The co-design of the antenna and the PA allows to suppress the traditional inter-stage impedance matching between these two blocks. More specifically, it is suitable to design the antenna with the appropriate output impedance of the PA which gives optimal performances for maximum power and efficiency.
Fully integrated chipset at E-band frequencies in a superhetrodyne architecture covering the 81-86 GHz band was designed and fabricated in 0.13 µm SiGe technology. The receiver chip includes an image-reject low-noise amplifier (LNA), RF-to-IF mixer, variable gain IF amplifier, quadrature IF-to-baseband de-modulators, tunable baseband filter, phase-locked loop (PLL), and frequency multiplier by four (quadrupler). The receiver chip achieves maximum gain of 73 dB, 6 dB noise figure, better than-12 dBm IIP3, with more than 65 dB dynamic range, and consumes 600 mW. The transmitter chip includes a power amplifier (PA), image-reject driver, variable RF attenuators, IF-to-RF up-converting mixer, variable gain IF amplifier, quadrature baseband-to-IF modulator, PLL, and frequency quadrupler. It achieves output power at P1dB of 16.6 dBm, Psat of 18.8 dBm on a single-ended output and consumes 1.8 W.
In this paper the small-signal equivalent circuit model of SiGe:C heterojunction bipolar transistors (HBTs) has directly been extracted from S-parameter data. Circuit simulations by the use of neural network architecture and a standard IHP 0.13 um BiCMOS technology confirmed our design goals. To check the capability of the direct approach, scattering parameters were generated and compared with Artificial Neural Network (ANN). Then measured and model-calculated data have represented an excellent agreement with less than 0.166% discrepancy in the frequency range of > 300 GHz over a wide range of bias points.
This paper examines the suitability of advanced SiGe BiCMOS and sub 65nm CMOS technologies for applications beyond 80GHz. System architectures are discussed along with the detailed comparison of VCOs, LNAs, PAs and static frequency dividers fabricated in CMOS and SiGe BiCMOS, as required for automotive cruise-control radar, high data-rate radio, and active and passive imaging in the 80GHz to 160GHz range. It is demonstrated experimentally that prototype SiGe HBT and BiCMOS technologies have adequate performance for all critical 80GHz building blocks, even at temperatures as high as 125 C. Although showing promise, existing 90nm GP CMOS and 65nm LP CMOS circuits at these frequencies remain significantly inferior to their SiGe counterparts.
This letter presents a 77-GHz power amplifier implemented in a SiGe BiCMOS technology featuring bipolar transistors with 160/175-GHz fT/fmax. The circuit adopts a two stage differential topology with integrated input/output matching networks. The amplifier performance is considerably improved thanks to proper input/output LC resonant networks, which cancel out the ground-plane parasitic effect. Matching networks use stacked transformers for impedance matching, differential-to-single-ended conversion, and electro-static discharge protection. The circuit achieves a power gain of 18.5 dB, a maximum output power of 11.6 dBm, with 4.2% power-added efficiency, and an output 1-dB compression point of 9.3 dBm. © 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett 53:1413–1416, 2011; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.25972
A small-signal lumped-element modeling technique for P-I-N photodiodes is presented.The model is extracted by fitting model's components with the accurately measured S parameters using the genetic algorithm. Experimental results indicate the extracted model is well matched to the measured data in the frequency range from 130 MHz to 20 GHz. © 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett 53:1416–1419, 2011; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.25971
In this article, the small-signal equivalent circuit model of SiGe:C heterojunction bipolar transistors (HBTs) has directly been extracted from S-parameter data. Moreover, in this article, we present a new modelling approach using ANFIS (adaptive neuro-fuzzy inference system), which in general has a high degree of accuracy, simplicity and novelty (independent approach). Then measured and model-calculated data show an excellent agreement with less than 1.68 × 10−5% discrepancy in the frequency range of higher than 300 GHz over a wide range of bias points in ANFIS. The results show ANFIS model is better than ANN (artificial neural network) for redeveloping the model and increasing the input parameters.
This article presents the design and implementation of a differential 4-way power-combining amplifier operating at E-band. The proposed 4-way power combiner facilitates short interconnects to the power amplifier (PA) cells, thereby resulting in reduced loss. Simple C-L-C and L-C networks are deployed to compensate inductive loading due to the routing lines that would otherwise introduce mismatch and subsequently increase overall loss. Realized in SiGe technology, the PA prototype delivered 13.2 dBm output-referred 1-dB compression point and 14.3 dBm saturated output power when operated from a single 3.3 V DC supply at 75 GHz. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:1764–1770, 2014
A three-stage, 77/79GHz transformer-coupled differential power amplifier is implemented in 130nm SiGe-BiCMOS. Common-base stages maximize output voltage swing and power, while a cascode first stage enhances gain for greater power-added efficiency (PAE). A frequency-scalable, parasitic-compensated balun combines power from the output stages to the 50Ω load with ;8GHz. Maximum output power and peak-PAE are 18dBm and 9%, respectively, at 84GHz. The 0.23mm2 active area PA consumes 395mW from a 2.5V supply.
This paper presents a fully integrated 81-86 GHz power amplifier (PA) fabricated in a 0.12 μm SiGe BiCMOS technology. Three cascode stages, followed by two common-emitter stages were utilized to achieve power gain of 30dB with 12dBm output power at 1dB compression and saturated power of 14dBm. Small signal characteristics show peak gain achieved at 86GHz with both input and output matching is better than -15dB from 77GHz to 87GHz. A 40dB image rejection is accomplished by a selective notch filter also integrated on chip. The PA's bias is applied by digitally adjustable bias circuits to provide process and temperature compensation and was measured in room temperature, 50°C and 85°C. It consumes quiescent currents of 120mA and 85mA from a 2V and 2.7V supplies respectively at 1dB compression and occupies area of 1.6mm2.
A 77 GHz power amplifier (PA) fabricated in a standard CMOS 65-nm process for radar automotive applications is presented. Based on passive transformer-coupled architectures, a high gain PA has been developed for a 76-77 GHz frequency range. The proposed PA achieves a 18.5 dB gain with output compression point (OP1dB) of +9.5 dBm and a saturated output power of +10.5 dBm for a 1.2 V supply. The isolation between input and output ports is better than 42 dB, and peak power added efficiency (PAE) is 7.1 %. Return losses at the input and output ports are less than -10 dB across the 67-100 GHz band. The PA has a compact size of 0.4 × 0.85 mm2.
In this paper, we present a W-Band load pull test bench used to improve a characterization of Silicon Germanium Heterojunction Bipolar Transistor (SiGe HBT). High accuracy is obtained in Load-pull measurements at 94 GHz on last-generation SiGe HBTs by extracting the input reflection hot S-parameter (S'11), in order to understand the mechanisms of power behavior in the presence of millimeter-wave excitations. The device under test (0.12×4.9μm2) was characterized under large signal load pull showing attractive performance for power amplifier design. A state-of-the-art power density of 22.26 mW/μm2 has been extracted at 94 GHz.
A frequency-scalable, three-stage, transformer-coupled millimeter-wave power amplifier (PA) is implemented in 130 nm SiGe-BiCMOS. Differential common-base gain stages extend collector-emitter breakdown voltage beyond 3 V, while collector-emitter neutralization increases reverse isolation and stability. Monolithic self-shielded transformers designed for low insertion loss and compact dimensions on-chip include: a 2:4 input power splitter, a 4:1 output balun combiner and inter-stage coupling transformers. The balun combiner and fully-differential splitter are compensated for imbalances caused by parasitic interwinding capacitance, and simulations predict better than 3% uniformity between reflected port-to-port impedances at 60 GHz. Simulated impedance uniformity is within 6% from 55-65 GHz, and insertion loss of the 0.015 mm2 combiner prototypes at 60 GHz is below 1 dB. The 0.72 mm2 60 GHz-band PA realizes a measured peak small-signal gain higher than 20 dB with over 10 GHz 3 dB bandwidth. Reverse isolation is better than 51 dB from 50-65 GHz and the PA is unconditionally stable. It consumes 353 mW (quiescent) from a 1.8 V supply and the active area is 0.25 mm2. Maximum output power and peak power-added efficiency (PAE) are 20.1 dBm and 18% at 62 GHz, respectively. An up-banded 79-87.5 GHz PA is also implemented to verify frequency scalability of the design. The 0.23 mm2 active area 79 GHz PA prototype produces 18 dBm saturated output power and 9% peak-PAE at 84 GHz from a 2.5 V supply.
This paper presents holistic design of a novel four-way differential power-combining transformer for use in millimeter-wave power-amplifier (PA). The combiner with an inner radius of 25 μm exhibits a record low insertion loss of 1.25 dB at 83.5 GHz. It is designed to simultaneously act as a balanced-to-unbalanced converter, removing the need for additional BALUNs typically required in differential circuits. A complete circuit comprised of a power splitter, two-stage differential cascode PA array, a power combiner as well as input and output matching elements was designed and realized in SiGe technology with fT/fmax 170/250 GHz. Measured small-signal gain of at least 16.8 dB was obtained from 76.4 to 85.3 GHz with a peak 19.5 dB at 83 GHz. The prototype delivered 12.5 dBm output referred 1 dB compression point and 14 dBm saturated output power when operated from a 3.2 V dc supply voltage at 78 GHz.
An 83-GHz two-stage cascode power amplifier (PA) implemented in a low-cost 200/180-GHz fT/fmax 0.18-μm SiGe BiCMOS technology is presented. The power-combining technique based upon a low-loss two-way transmission-line current combiner has been employed that simultaneously addresses the gain requirement at millimeter wave while delivering a high linear output power, making it a potential contender for multigigabit/second point-to-point data links. The combiner efficiency and large-signal power bandwidth (BW) are improved by the compact output matching network synthesized and excellent amplitude/phase balance of the proposed current combiner, which also considers the reliability issues such as electromigration and built-in redundancy during power device failure. At 83 GHz, the PA achieves a measured saturated power (Psat) of 14.7 dBm, output-referred 1-dB compression point (OP1dB) of 12.5 dBm, peak power-added efficiency of 8.1%, and 1-dB large-signal power BW from 75 to 88 GHz. The measured peak power gain (S21) is 25 dB with a 3-dB small-signal BW from 76.8 to 86.4 GHz while consuming a total dc power of 348 mW from a 4-V supply. The overall chip area is 610 μm × 560 μm (0.34 mm2).
In this letter, we report load pull measurements on SiGe HBTs at 94 GHz. Nowadays, this kind of device exhibits $F_{\rm MAX}$ above 400 GHz and thus has a growing interest for W-band applications. A load pull test bench is developed for the characterization of this device with special care on architecture and calibration procedure for accurate measurements in 75–110 GHz. The device was characterized under large signal operation showing attractive performance for power amplifier design. A state-of-the-art power density of 18.5 $\hbox{mW}/\mu\hbox{m}^{2}$ at 1-dB compression has been obtained at 94 GHz.
of 230/280 GHz. The circuit consists of a two-stage pseudodifferential cascode with fully integrated input/output matching networks. State-of-art performance is achieved with the proposed design algorithm and layout optimization. The amplifier demonstrates a figure-of-merit of 2500 achieving a 22.5-dB power gain and a power-added efficiency of 7.5% at 77 GHz, while drawing 130 mA from a 2.5-V voltage supply. Index Terms—BiCMOS integrated circuits (ICs), electromagnetic (EM) simulations, IC layout, millimeter-wave circuits, power amplifier (PA), transformers.
A +20dBm, 60 GHz power amplifier (PA) with fully-integrated automatic level control is fabricated in a 0.13 mum SiGe BiCMOS process. At 60 GHz, the PA achieves a peak power gain of IS dB with 13.1 dBm output power at a 1-dB compression and a peak power-added efficiency (PAE) of 12.7 %. The PA uses a single-stage push-pull amplifier topology with center-taped microstrip lines. This enables a highly efficient and compact layout of the amplifier core with a small area of 0.075 mm2 . An on-chip power detector circuit uses transmission lines with integrated coupling capacitors for output power detection. All bias voltages are generated on chip and are programmable through a three-wire serial digital interface. The PA quiescent current is 62 mA from a 4 V supply
This paper describes a 60 GHz high gain power amplifiers (PA) designed in a 0.18-μm SiGe BiCMOS technology. It consists of four cascode stages with inter-stage matching implemented by the conductor-backed coplanar waveguide (CBCPW) structures and metal-insulator-metal (MIM) capacitors. A double-stub low Q input matching network is design to achieve wideband input matching. Since one of double-stub is open stub, the S11 can easily be tuned by trimming after fabrication. Load-pull simulation generates the optimal load impedance. A wideband harmonic rejection ESD is introduced to simultaneously reject the harmonics and achieve ESD protection. Simulation result shows that the maximum gain is 35.4 dB with 3 dB bandwidth 55–69 GHz. The S11 is
This paper presents a fully integrated 77GHz power amplifier (PA) fabricated in a 0.13 μm SiGe BiCMOS technology. A 4-stages single ended common-emitter topology was utilized to achieve power gain of 19dB at 77GHz with 14.6dBm output power at 1dB compression, saturated power of 16dBm and 12.5% peak PAE. Small signal characteristics show a wideband behavior - Maximal small signal gain of 23dB achieved at 69 GHz with 3 dB bandwidth of 15GHz (22%) and both input and output matching is better than -10dB from 72 GHz to 90GHz. The PA's bias is applied by adjustable bias circuits to provide process and temperature compensation and was measured in room temperature and at 85°C. It consumes a quiescent current of 100mA from a 2V supply at 1dB compression and occupies area of 1.4mm2.
In this paper, a 60 GHz MMIC down-conversion mixer for 60 GHz WPAN is designed and fabricated on chip using 0.25 mum SiGe:C BiCMOS process technology. This 60 GHz mixer is fully integrated on chip, including active input balun and output balun circuits. The results of the fabricated mixer measured at RF 60 GHz show conversion gain of 10.7 dB, LO to IF isolation and RF to IF isolation of above 30 dB, and input P1dB of -17 dBm. Also, the results of the fabricated mixer measured between RF 57 and 63 GHz show conversion gain of 12.0 ~ 10.7 dB, LO to IF isolation and RF to IF isolation of above 28 dB, and input P1dB of -17 ~ -18 dBm. The chip size of the manufactured mixer is 1.3 mm times 0.8 mm.
This paper presents a pseudodifferential power amplifier for 77-GHz automotive radar. The circuit is fabricated in a SiGe HBT BiCMOS technology featuring bipolar transistors with $f_{T}/f_{\max}$ of 230/280 GHz. The amplifier adopts a transformer-coupling current-reuse approach to improve both gain and efficiency. An interstacked transformer is also profitably adopted to reduce output losses due to the differential-to-single-ended conversion. The amplifier exhibits a saturated power, a peak power-added efficiency, and a gain of 14.5 dBm, 9%, and 25 dB, respectively, thus achieving a first-rate figure-of-merit as high as 4755.
The performance of a SiGe heterojunction bipolar transistor (HBT) millimetre-wave power amplifier (PA) operating at cryogenic temperature was reported and analysed for the first time. A 24 GHz two-stage medium PA employing common-emitter and common-base SiGe power HBTs in the first and the second stage, respectively, showed a significant power gain increase at 77 K in comparison with that measured at room temperature. Detailed analyses indicate that cryogenic operation of SiGe HBT-based PAs mainly affects (improves) the performance of the SiGe HBTs in the circuits due to transconductance enhancement through magnified, favourable changes of SiGe bandgap due to cooling (ΔEg/kT) and minimized thermal effects, with little influence on the passive components of the circuits.
We employ topology optimization with the finite-element method to improve the coupling between a slab waveguide and a photonic crystal waveguide. Here, we apply topology optimization in a small design region to realize the improvement of the coupling. Also, we simplify an optimized structure of the coupling region for easier fabrication and try to find core features of the optimized structure. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 3009–3012, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23886
In this article, a 60 GHz band down-conversion mixer for 60 GHz wireless personal-area network is designed and fabricated on a chip using 0.25 μm SiGe:C BiCMOS process technology. To design this 60 GHz band mixer, architecture of double-balanced mixer is used, including input and output balun circuits, which are composed of active elements. The results of the fabricated mixer measured between RF 57 and 63 GHz show conversion gain of 12.0–10.7 dB, LO to RF isolation and LO to IF isolation of more than 28 dB, and input P1dB of −17 to −18 dBm. The chip size of the manufactured mixer is 1.3 mm × 0.8 mm. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 3007–3009, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23887
Recently, there has been growing interest in using silicon-based integrated circuits at high microwave and millimeter wave
frequencies. The high level of integration offered by silicon enables numerous new topologies and architectures for low-cost
reliable SoC applications at microwave and millimeter wave bands, such as broadband wireless access (e.g., WiMax) [1], vehicular radars at 24GHz and 77GHz [2][3], short range communications at 24GHz and 60GHz [4][5][6], and ultra
narrow pulse generation for UWB radar [7].
A 60GHz LNA, direct-downconverter, PA, and 20GHz VCO are built in a 200GHz f<sub>t</sub>,/f<sub>max</sub>, 0.12μm SiGe technology. The 10.8mW LNA has 15dB gain, 3.4-4.4dB noise figure and -8.5dBm IIP3. The down converter has 16dB gain, >50dB LO-RF isolation, and 13.4-14.8dB noise figure. The PA delivers 10dBm at 9dB gain.
A MMIC 77-GHz two-stage power amplifier (PA) is reported in this letter. This MMIC chip demonstrated a measured small signal gain of over 10 dB from 75 GHz to 80 GHz with 18.5-dBm output power at 1 dB compression. The maximum small signal gain is above 12 dB from 77 to 78 GHz. The saturated output power is better than 21.5 dBm and the maximum power added efficiency is 10% between 75 GHz and 78 GHz. This chip is fabricated using 0.1-/spl mu/m AlGaAs/InGaAs/GaAs PHEMT MMIC process on 4-mil GaAs substrate. The output power performance is the highest among the reported 4-mil MMIC GaAs HEMT PAs at this frequency and therefore it is suitable for the 77-GHz automotive radar systems and related transmitter applications in W-band.
This paper reports on SiGe NPN HBTs with unity gain cutoff frequency (f/sub T/) of 207 GHz and an f/sub MAX/ extrapolated from Mason's unilateral gain of 285 GHz. f/sub MAX/ extrapolated from maximum available gain is 194 GHz. Transistors sized 0.12/spl times/2.5 /spl mu/m/sup 2/ have these characteristics at a linear current of 1.0 mA//spl mu/m (8.3 mA//spl mu/m/sup 2/). Smaller transistors (0.12/spl times/0.5 /spl mu/m/sup 2/) have an f/sub T/ of 180 GHz at 800 /spl mu/A current. The devices have a pinched base sheet resistance of 2.5 k/spl Omega//sq. and an open-base breakdown voltage BV/sub CEO/ of 1.7 V. The improved performance is a result of a new self-aligned device structure that minimizes parasitic resistance and capacitance without affecting f/sub T/ at small lateral dimensions.
It is demonstrated that SiGe bipolar preproduction technologies are well suited for VCOs in 77 GHz automotive radar systems. Due to the relatively high output power aimed at, the designer has to consider the physical transistor limits carefully. The VCOs need a single supply voltage only and have been fully integrated (including resonant circuit and output buffer) on a single small (1 mm<sup>2</sup>) chip, demonstrating their low-cost potential. First experimental results based on a not fully optimized design showed at a center frequency of about 77 GHz, a tuning range of 4.3 GHz, and a phase noise of -95 dBc/Hz at 1 MHz offset frequency. The total signal power of both outputs is 14.3 dBm. Simulations demonstrate a further potential increase of total output power (for two or four outputs) by about 5 dBm.
This paper discusses the effects of process and temperature
variations on the performance of GaAs HBT power amplifier bias circuits.
A novel feedback bias circuit, which overcomes these problems, is
presented. The measured variation from 54 to 60 mA in the bias current,
over the temperature range of -25 to +85°C, agrees well with the
simulations. The circuit is insensitive to variations in the regulated
voltage which is a desirable feature in a case when the amplifier is
biased to a constant current. On the other hand, a smooth bias and gain
control can be achieved by adding an extra resistor connected to a
separate control voltage
A recent effort to design, build and test a 77 GHz radar to be used for adaptive cruise control (ACC) of automobiles is described. The radar requirements are discussed, along with a short description of a radar prototype meeting the requirements. The radar has been tested thoroughly and evaluated both under controlled conditions and on public roads. Some results from the tests are included. Future trends for car radars are discussed briefly. The main trend is more complex systems with the capability to detect stationary objects, eventually making the intelligent cruise controller a collision-warning/avoidance system.
The onset of impact-ionization-induced instabilities limits the
operating range of Si-bipolar transistors, especially in power stages.
Therefore, analytical relations which characterize the onset of
instabilities are derived for different driving conditions (mainly
V<sub>BE</sub>=const. and I<sub>E</sub>=const.) and arbitrary transistor
geometries. They allow the designer and technologist to calculate the
maximum usable dc output voltage in dependence on transistor dimensions
and technological parameters. As a consequence, the voltage range above
BV<sub>CE0</sub> can now be more intensively and reliably used and thus
the performance potential of a given technology can be better exploited.
However, the reduction of the maximum tolerable output voltage with
increasing emitter (or collector) current must be carefully considered.
The presented theory and analytical results are verified by
three-dimensional (3-D) transistor simulations and by measurements
A physics-based scalable transistor model is described which allows accurate consideration of avalanche-breakdown effects in bipolar circuit simulation. The three-dimensional model consists of six lumped transistor elements, which are connected via elements of the base and emitter-contact resistance. Analytical relations are given to calculate the elements of this six-transistor model (6TM) for arbitrary emitter dimensions from measured area- and length-specific transistor parameters. As a core of the transistor elements, all kinds of conventional transistor models can be used provided an adequate avalanche current source is implemented between the internal collector and base nodes. The validity of this 6TM has been verified under dc and fast transient conditions by simulations and measurements.
- R Singh
- D L Harame
- M M Oprysko
- Silimn Gemanium
131 R. Singh, D. L. Harame, and M. M. Oprysko, Silimn Gemanium: Technology, Modeling, and Design, IEEE Press, 2003.