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Baseband processor for IEEE 802.11a standard with embedded BIST

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In this paper results of an IEEE 802.11a compliant low-power baseband processor implementation are presented. The detailed structure of the baseband processor and its constituent blocks is given. A design for testability strategy based on Built-In Self-Test (BIST) is proposed. Finally implementational results and power estimation are reported.
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... The baseband processor blocks can be separated into two different subsets: those that provide 802.11a full compliance and those that enhance the transceiver performance supporting the RF combining concept presented in Section 2. The former is a standard 802.11a baseband processor developed by IHP Electronics [6] while the latter are some newly created MIMAX modules by GTAS group at University of Cantabria [7]. In fact, as the final objective is to emulate the RF antenna combining scheme, the emulator uses only essential parts of that baseband processor. ...
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... Our work in the GALS area is connected to a project that aimed to develop a single-chip WLAN modem compliant to the IEEE 802.11a standard [14]. First, we have implemented the baseband processor for the WLAN modem as a standard synchronous design, as reported by Krstić et al. [15,16] and Grass et al. [17]. It has a complexity of around 700 k gates and uses the clock gating as a power reduction technique. ...
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Vlsi implementation of IEEE 802.11a physical layer
  • L Schwoerer
  • H Wirz
L. Schwoerer and H. Wirz, " Vlsi implementation of IEEE 802.11a physical layer, " in Proc. 6th Int'l. OFDM Workshop, Hamburg, Germany, 2001, pp. 28.1 – 28.4.
Available: http://www.synopsys.com/products
  • Synopsys Inc
Synopsys Inc. [Online]. Available: http://www.synopsys.com/products/power/ primepower ds.pdf