A Novel Energy Efficient 4-bit Vedic Multiplier using Modified GDI Approach at 32 nm Technology

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Heliyon 10 (2024) e31120
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Research article
A novel energy efficient 4-bit vedic multiplier using modified GDI
approach at 32 nm technology
K. Nishanth Rao a, D. Sudha b, Osamah Ibrahim Khalaf c,
Ghaida Muttasher Abdulsaheb d, Aruru Sai Kumar e,∗, S. Siva Priyanka f,
Khmaies Ouahada g, Habib Hamam g,h,i,j
aDepartment of ECE, MLR Institute of Technology, Hyderabad, India
bDepartment of ECE, CMR College of Engineering and Technology, Telangana, India
cDepartment of Solar, Al-Nahrain Research Center for Renewable Energy, Al-Nahrain University, Jadriya, Baghdad, Iraq
dDepartment of Computer Engineering, University of Technology, Baghdad 10066, Iraq
eDepartment of ECE, VNR Vignana Jyothi Institute of Engineering and Technology, Telangana, India
fDepartment of ECE, Chaitanya Bharathi Institute of Technology, Telangana, India
gSchool of Electrical Engineering, University of Johannesburg, Johannesburg 2006, South Africa
hFaculty of Engineering, Université de Moncton, Moncton, NB, E1A3E9, Canada
iHodmas University College, Taleh Area, Mogadishu, Somalia
jBridges for Academic Excellence, Tunis, Tunisia
A R T I C L E I N F O A B S T R A C T
Keywords:
CMOS
Transmission gate
Gate diffusion input
Area
Delay
PDP
Ripple carry adder
Caary skip adder
Carry look ahead adder
Multipliers are essential components within digital signal processing, arithmetic operations,
and various computational tasks, making their design and optimization crucial for improving
the efficiency and performance of integrated circuits. Among multiplier architectures, Vedic
multipliers stand out due to their inherent efficiency and speed, derived from ancient Indian
mathematical principles. This study presents a comprehensive analysis and comparison of 4-
bit Vedic multiplier designs utilizing Gate Diffusion Input (GDI), Complementary Metal-Oxide-
Semiconductor (CMOS), and Transmission Gate (TG) technologies, utilizing different adder
architectures such as Ripple Carry Adder (RCA), and Carry Lookahead Adder (CLA), Carry
Skip Adder (CSA). The objective is to explore the performance, area, and power consumption
characteristics of these multipliers across different technologies and adder implementations. Each
multiplier architecture is meticulously designed and optimized to leverage the unique features of
the respective technology while adhering to the principles of Vedic mathematics. The designs are
evaluated based on parameters such as transistor count, delay, power dissipation, and area. The
results demonstrate the effectiveness of GDI technology in terms of in tems of delay, area, power
and PDP when compared with other technologies. The 4-bit Vedic multiplier has been designed
using 32 nm technology within Tanner EDA software tools.
* Corresponding author.
E-mail address: asaikumar.nitw@gmail.com (A.S. Kumar).
https://doi.org/10.1016/j.heliyon.2024.e31120
Received 5 April 2024; Received in revised form 3 May 2024; Accepted 10 May 2024

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1. Introduction
Multipliers play an essential role in contemporary digital signal processing and related domains. Among the most fundamental
and widely used arithmetic operations in HPS are adding and multiplying two binary values. Multiplication plays a crucial role in
signal processing applications, serving as the fundamental arithmetic operation. In many algorithms, especially in signal processing
tasks like filtering or Fourier transforms, multiplication is a foundational operation. Multipliers drastically speed up these calculations
compared to iterative addition methods, crucial for real-time processing in applications like audio or video processing. Multipliers
also optimize hardware by saving space and power, supporting various data types for flexible computations and ensuring precision
in high-resolution tasks. Digital signal processing and other signal and data processing tasks heavily rely on multiplication [1]. Quick
processing is becoming more important due to the increasing demands of technology and signal processing. Reduced power usage is
another factor to think about while designing multipliers. A high-speed, low-power multiplier has been in high demand recently due
to the fact that dynamic power consumes an excessive amount of power overall [2]. Fast, energy-efficient circuits are a designer’s
primary focus. An ideal multiplier would be a small, quick, and energy-efficient device [3]. The mathematical canon known as Vedic
mathematics was rediscovered in the early 20𝑡ℎ century after having disappeared from Indian culture for centuries. The Sutras are
the sixteen guiding principles, or word-formulae, that are the bedrock of Vedic mathematics. This paper looks at how to make a
basic digital multiplier called a Vedic multiplier using the Urdhva Triyakbhyam (Vertically and Crosswise) Sutra. It is based on how
well the Vedic multiplication algorithm works in digital multipliers [4]. Historically employed for decimal multiplication, this sutra
is adapted for digital circuitry, with a specific focus on its application in the binary number system [5]. The paper delves into the
components of a Vedic multiplier, establishing its correlation with the widely-used array multiplier. A thorough investigation of the
old Vedic literature may also reveal many more technological applications [6].
Urdhvaka Triyakbhyam, a Vedic multiplication technique, deconstructs numbers into components and applies specific rules. In
the context of 2-bit multiplication, the process involves multiplying the rightmost binary digits, where the result becomes the right
part of the answer. Cross-multiplying and summing the results, carrying any excess to the left, yields the left part. Iteratively applying
Urdhvaka Triyakbhyam principles for higher bits ensures efficient mental calculation, facilitating rapid multiplication. A 4-bit Vedic
multiplier employs 2-bit Vedic multiplication units, and the processes of 2-bit Vedic multiplication are depicted in Fig. 1. The design
of a 2-bit vedic multiplier using half adders is shown in Fig. 2.
Fig. 1. 2 x 2 Vedic Multiplication using Urdhvaka Triyakbhyam.
Fig. 2. 2-bit Vedic Mutliplier using Half Adders.

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Fig. 3. 4-bit Vedic Mutliplier using 2-bit Vedic Multiplier.
For effective multiplication, a Vedic multiplier integrates three distinct adder architectures: RCA, CLA, and CSA. Several different
adder architectures can be utilized to maximize speed and performance when utilizing this type of multiplier to multiply two binary
values. The main benefit of this method is that it integrates the best features of RCA, CLA, and CSA adders. While CLA and CSA
adders are more complicated but faster, the RCA is simple to install but slow. The partial products and final addition in the Vedic
multiplier can be accomplished quickly and efficiently with CLAs or CSAs. In traditional CMOS circuits, power is dissipated during
the charging and discharging of the load capacitance associated with each gate. Gate Diffusion Input aims to address this issue
by modifying the standard CMOS structure. Gate Diffusion Input (GDI) is indeed a low-power design technique used in digital
circuit design [7]. It’s particularly advantageous in terms of power efficiency and reduced transistor count compared to traditional
CMOS (Complementary Metal-Oxide-Semiconductor) logic. In GDI, logic functions are implemented using a combination of gates and
diffusion inputs. The basic idea behind GDI is to utilize the gate-to-diffusion capacitance of transistors to achieve logic operations.
By doing so, GDI circuits can achieve improved logic swing (the voltage difference between logic high and logic low) and lower
static power dissipation. Within the realm of digital circuits, there exists a unique approach to multiplication inspired by an ancient
Indian mathematical technique known as the Vedic method. Specifically, a 4-bit multiplier circuit employing Gate Diffusion Input
(GDI) logic harnesses the principles of Vedic mathematics. This innovative design not only enables efficient multiplication but also
leverages the power-saving benefits inherent in GDI technology [8].
In order to design a 4-bit Vedic multiplier using GDI (Gate Diffusion Input) technology, one must create a digital circuit that uses
Vedic math to do the multiplication and GDI to make the logic design more power-efficient. Fig. 3,depicts the architecture of a 4-bit
Vedic multiplier. The setup consists of four 2 x 2 Vedic multipliers and three 4-bit ripple carry adders. Each 2 x 2 Vedic multiplier
is built using four AND gates and two 2-bit adders. It’s noteworthy that the adder blocks shown in Fig. 3,are interchangeable with
various types of adders, including ripple carry adders, carry-select adders, and carry look-ahead adders. This flexibility allows for
customization based on specific performance and design requirements.
The GDI method is employed to decrease power consumption, delay, and area utilization in digital circuits, while keeping logic
design complexity low. A GDI cell comprises three inputs: the gate inputs of PMOS and NMOS (G), the input to the drain/source of
PMOS (P), and the input to the drain/source of NMOS (N). Both the bulk of PMOS and NMOS are linked to their respective diffusion

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Fig. 4. (a) Basic GDI cell (b) Modified GDI (m-GDI) cell.
regions (P and N) to mitigate bulk effects. This approach reduces subthreshold leakage current and gate leakage current compared
to conventional CMOS design, resulting in lower power consumption. The m-GDI technique, derived from GDI, facilitates high-speed
operation, reduced power dissipation, fewer transistors, and minimized circuit area. The m-GDI cell also has three input terminals—
gate inputs of PMOS and NMOS (G), input to the drain/source of PMOS (P), and input to the drain/source of NMOS (N)—with the
bulk of PMOS consistently connected to VDD and the bulk of NMOS to VSS. The fundamental GDI and Modified GDI (m-GDI) cells
are illustrated in Fig. 4(a) and Fig. 4(b) respectively.
The choice of adder architecture, whether it’s a Ripple Carry Adder (RCA), Carry Lookahead Adder (CLA), or Carry Skip Adder
(CSA), has a substantial impact on the performance of Vedic multipliers. The Ripple Carry Adder (RCA) is a basic design but
suffers from slower speeds due to sequential carry bit generation, especially noticeable with larger operands where propagation
delays become significant. On the other hand, the Carry Lookahead Adder (CLA) addresses this issue by pre-computing carry signals
for each bit position, enabling parallel carry generation and reducing propagation delays. This makes CLA a favorable choice for
Vedic multipliers requiring high-speed computations. Similarly, the Carry Skip Adder (CSA) optimizes speed by selectively skipping
carry generation for specific bit positions under certain conditions. This further minimizes delays, particularly beneficial for Vedic
multipliers handling operands where carry predictions or skips are feasible.
When evaluating delay, the Carry Skip Adder (CSA) surpasses both the Ripple Carry Adder (RCA) and the Carry Lookahead Adder
(CLA). This superiority stems from CSA’s ability to enhance speed by intelligently skipping carry generation for select bit positions,
depending on predefined conditions. However, in terms of transistor count, RCA demonstrates an advantage by requiring fewer
transistors than CLA and CSA. This lower transistor count in RCA directly impacts power consumption. With fewer transistors, the
overall circuit complexity and switching activities are reduced, leading to lower power requirements compared to CLA and CSA
implementations.
This paper introduces a highly effective 4-bit Vedic multiplier design realized in 32 nm technology employing a modified GDI
methodology. The salient contributions of the proposed work are as follows:
•The proposed technique outlines the design of a two-bit Vedic multiplier using m-GDI technology, which is utilized in develop-
ment a four-bit multiplier.
•The algorithm used to multiply two four bit numbers uses 4-(n/2) bit vedic multipliers, 2 n-bit adders and one (n/2) bit adder.
•The inclusion of various adder architectures such as Ripple Carry Adder (RCA), Carry Select Adder (CSA), and Carry Look-
Ahead Adder (CLA) allows for a comprehensive comparison of their performance metrics including speed, area, and power
consumption.
•When compared to CMOS and TG Technology, the four-bit vedic multiplier that has been implemented using GDI Technology
performs better in terms of delay, power, PDP, and transistor count.
•In this four-bit Vedic multiplier employing m-GDI, the RCA-based multiplier exhibits smaller area and power consumption,
while the CSA-based multiplier demonstrates reduced delay and power-delay product (PDP), highlighting differing advantages
between the two designs in terms of area, power, delay, and power-delay product.
The organization of this research is determined as follows; Section 2provides the related work, and Section 3details the archi-
tecture of an existing Vedic multiplier using CMOS and TG methods. Section 4explains the details of the proposed work using the
32 nm GDI approach, and the experimental outcomes are represented in Section 5. The research paper concludes with Section 6.
2. Related work
A transmission gate-based Vedic multiplier, as described by Swati T. Mestry et al. [9], and CMOS-based approaches employing a
variety of adders were both mentioned as important technologies. The TG-based CLA adder experiences an average power reduction
of 76.3%, a power delay product reduction of 48.13%, and an energy-delay product reduction of 13.69% when the operating voltage
is reduced by 20%. The average power of the TG-based CLA adder decreases to 41.42% when the temperature rises from 25 to 50
degrees Celsius, considering the power delay product increases to 65.33% and the energy delay product decreases to 93.28%. Aruru
Sai Kumar et al., [10] introduced an innovative 8-bit Vedic multiplier utilizing parallel prefix adders, specifically the Brent Kung
adder, to enhance efficiency. They adopted the Urdhva Tiryagbhyam sutra instead of other multiplication techniques, as it applies
universally to all algorithms for N x N bit integers and provides the shortest latency, thereby justifying its adoption An 8-bit vedic

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multiplier can be built out of one OR gate, two 8-bit Brent Kung adders, one 4-bit Brent Kung adder, and four 4-bit vedic multipliers.
However, by combining the aforementioned elements, this is possible. The newly constructed Vedic Multiplier’s speed is significantly
more effective when compared to earlier attempts with similar features.
Ankit Garg et al., [11] proposed employing GDI logic to make a 4-bit Vedic multiplier. It resembles the rapid responses of two-bit
Vedic multipliers built into CMOS and GDI to see how well the GDI logic works. The goal of this study is to see how well the GDI
method works. Instead of the 4-bit Vedic multiplier, two different versions are now being thought about. These circuit’s average
power consumption, delay, and temperature tolerance are the metrics by which we evaluate their performance. More research is
being done to find out if the power from the source can be changed. In order to look at the device’s properties, this method utilized
the bulk metal oxide semiconductor field effect transistor prediction technology model. The circuit computations are done at a
precision of 130 nm. P. Saritha et al., [12]produced the concepts for a 4-bit Vedic multiplier on 18 nm FinFET, and they utilized
the various design methodologies that we discussed. A GDI-based AND, half adder, and full adder circuit can be utilized to build a
4-bit Vedic multiplier if the first way, which is referred to as Design 1. This must be done in order to bring the job to a successful
conclusion. It is intended that design-2 of 4-bit Vedic multiplier will be created with the assistance of a 2-bit Vedic multiplier that
is based on GDI, a half adder, and a 4-bit Ripple carry circuit. This will be done. Because of this, it will be possible to construct the
multiplier. These take into consideration typical values for things like average power, usual latency, typical transistor density, and
typical board size.
Vahid Foroutan et al., [13] implemented two novel symmetric topologies with a hybrid CMOS logic and a GDI (Gate-Diffusion
Input) structure for low-power full adder cells. These patterns are mirror images of one another. These adder modules were designed
with complete voltage swing support as a main need, along with low power dissipation and high speed. An initial design has been
created using a mixed logic strategy. To create new complete adders with the required performance, the hybrid logic style integrates
aspects of multiple different logic types. This provides the designer with more leeway in their design, letting them optimize for a wider
variety of use cases with less work. The second concept is an innovative take on the standard adder cell layout that eliminates the
need for XOR and XNOR gates. In addition to the complete voltage swing circuit, an ultra-low-power, high-speed digital component
is provided by including the GDI (Gate-Diffusion-Input) approach into the design. Omnia Ali Albadry et al., [14] presented a 4-
bit multiplier using a full adder cell and the full swing gate diffusion input technique. The suggested adder design comprises 18
transistors and underwent comparison with alternative full adders employing various logic styles. This comparison was conducted
through cadence virtuoso simulations utilizing TSMC 65 nm models operating at 250 MHz and 1V. Out of all the designs that were
simulated, the suggested full adder design gives off the least amount of power, makes the area better, and generates a full swing
output voltage. The suggested full adder was used to generate Array, Barun, and Baugh Wooley multipliers. These multipliers had
better energy and number of transistors than CMOS.
3. Existed 4-bit vedic multiplier
The 4-bit Vedic multiplier is a computational circuit based on ancient Vedic mathematics principles, offering a novel approach to
binary multiplication. This multiplier is based on the Urdhva-Tiryakbhyam algorithm, which is a Vedic method for making multipli-
cation easier by using a set of geometric patterns and symmetric operations. The multiplier architecture consists of interconnected
modules that facilitate parallel processing, enhancing its efficiency compared to conventional multipliers. The uniqueness of Vedic
mathematics is that it eliminatesthe lengthy and very simple equations using the Urdhva Triyagbhyam (Vertically and Crosswise)
Sutra one of 16 Vedic mathematical sutras. The Vedic sutra, known as Urdhva Triyagbhyam means both vertically and crosswise.
This sutra is a powerful way to multiply and results in faster multiplication by partial generation of the product and a summing up
in a single iterative step [15,16]. This sutra has the advantage of saving considerable time and effort to solve the problem.
One notable feature of the 4-bit Vedic multiplier is its ability to achieve high-speed multiplication due to parallelism. The
Urdhva-Tiryakbhyam method allows simultaneous processing of multiple bit pairs, reducing the overall computation time. This
makes it particularly suitable for applications where rapid multiplication is crucial, such as digital signal processing and arithmetic-
intensive operations. Moreover, the 4-bit Vedic multiplier exhibits an inherent regularity in its design, which contributes to ease of
implementation and scalability. The modular structure allows for straightforward expansion to higher bit widths, making it adaptable
to varying computational requirements. As researchers delve into exploring novel architectures for efficient arithmetic operations,
the 4-bit Vedic multiplier stands out as a promising candidate with its blend of ancient mathematical principles and contemporary
computing applications [17].
3.1. CMOS based 4-bit vedic multiplier
A CMOS-based 4-bit Vedic multiplier is a digital circuit that performs multiplication using ancient Vedic mathematics techniques
and is implemented with complementary metal-oxide semiconductor (CMOS) technology. The simplicity and efficiency of the Vedic
multiplication technique render it well-suited for implementation in hardware. CMOS is a popular choice for digital circuits due to
its low power consumption and compatibility with integrated circuits. In the context of the 4-bit Vedic multiplier, CMOS technology
allows for the efficient implementation of logic gates, enabling the creation of a compact and power-efficient multiplier circuit. The
4-bit design implies that the multiplier can handle two 4-bit binary numbers, multiplying them together to produce an 8-bit result.
It includes input registers to hold the two 4-bit operands, a series of shift-and-add stages, and an output register to store the result.
As per the “Urdhva Tiryagbhyam” Vedic method of multiplication, CMOS logic gates and multiplexers are used in each shift-and-add
stage to do bit-wise additions, shifts, and carry generation. The final result is obtained after multiple stages of processing, making it an

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Fig. 5. CMOS based Half adder.
Fig. 6. CMOS based Full adder.
efficient and parallel method for 4-bit multiplication in CMOS technology [18]. The Vedic multiplication algorithm is translated into
a series of logic gates and interconnections within the CMOS circuit to achieve the desired functionality. This architecture potentially
offers benefits such as faster computation speed, reduced power consumption, and a compact design. These advantages make it
suitable for applications where efficient hardware multiplication is crucial, such as in digital signal processing or microprocessor
design [19].
In a 4-bit Vedic multiplier, a full adder is crucial for performing addition operations within the multiplication process. Each full
adder takes care of adding two binary digits along with a carry from the previous stage [20]. In the context of a 4-bit Vedic multiplier,
it helps in adding the partial products generated during the multiplication of each pair of bits. The half-adder designed using CMOS
technology is shown in Fig. 5. The CMOS-based full adder designed using two half adders is depicted in Fig. 6.
3.2. TG based 4 bit vedic multiplier
A transmission gate-based 4-bit Vedic multiplier is a digital circuit designed for efficiently multiplying two 4-bit binary numbers
using Vedic mathematics principles. Vedic multiplication relies on specific mathematical sutras or techniques to simplify the multi-
plication process. In this context, transmission gates are used as electronic switches to control the flow of signals through the circuit.
Transmission gates, which are switches based on complementary CMOS, serve to either permit or obstruct signals. In this particular

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Fig. 7. TG based Full adder.
setup, the processing of each bit from two 4-bit numbers is accomplished through a sequence of these transmission gates. These gates
facilitate the passage of inputs, enabling logical operations like AND, XOR, and OR. This, in turn, allows the execution of crosswise
and vertical multiplication steps as outlined in Vedic mathematics. Leveraging transmission gates ensures efficient and low-power
logic operations, with the design being adaptable for optimization in terms of speed and area utilization [21].
The multiplier typically consists of four stages, each dedicated to multiplying a specific pair of bits from the two input numbers.
At each stage, transmission gates are employed to selectively allow or block the passage of signals, implementing the multiplication
and addition operations. The final result is obtained by combining the partial products generated at each stage. The architecture of
the transmission gate-based Vedic multiplier offers advantages such as reduced power consumption and improved speed compared
to traditional multiplication circuits. Transmission gates provide an efficient way to control signal flow, allowing for a streamlined
implementation of Vedic multiplication techniques. One key aspect of the design involves the utilization of Vedic sutras, which are
ancient Indian mathematical formulas. These sutras guide the arrangement of transmission gates and the handling of partial products,
contributing to a more optimized and efficient multiplication process. The combination of transmission gates and Vedic mathematics
principles results in a compact and high-performance 4-bit multiplier suitable for various digital applications. The full adder designed
using transmission gates is depicted in Fig. 7.
4. Proposed 4-bit vedic multiplier using GDI technology
Gate Diffusion Input (GDI) is a low-power design method that reduces static power consumption while simultaneously enhancing
logic swing. This approach enables the implementation of multiple logic functions using fewer transistors. Since fewer transistors
are required in this technique (in comparison to TG and CMOS), it is well-suited to the design of quick, low-power circuits. An
implementation of vedic multiplier with decreased transistor count and appropriate driving capabilities is done with GDI logic [22].
The implementation of a Vedic multiplier with a modified Gate Diffusion Input (GDI) technique and its comparison with multipli-
ers designed using Transmission Gate (TG) and Complementary Metal Oxide Semiconductor (CMOS) techniques in 32 nm technology
has shown notable advantages. The GDI-based Vedic multiplier stands out in terms of area, delay, power delay product, and tran-
sistor count, outperforming both TG and CMOS-based designs. The importance of GDI lies in its ability to enhance the efficiency of
Vedic multiplier implementations. GDI technology offers several advantages such as reduced power consumption, improved speed,

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Fig. 8. m-GDI based Full adder at 32 Technology Node.
and simplified circuit design. By leveraging these benefits, the GDI-based Vedic multiplier achieves superior performance metrics
compared to TG and CMOS designs. The excellence of GDI in Vedic multiplier implementation is evident through its ability to opti-
mize area utilization, reduce delays in signal propagation, minimize power consumption, and decrease the overall transistor count.
These factors contribute to a more efficient and high-performing multiplier circuit, showcasing the effectiveness of GDI technology
in advancing Vedic mathematics-based computational techniques in modern semiconductor technologies like 32 nm processes.
A low-power design method allows any logic function to be implemented with fewer transistors. This logic style may be manufac-
tured using a conventional CMOS process, and it improves upon prior technology in terms of output voltage, power, and power delay
product. A Vedic multiplier employing the Gate Diffusion Input (GDI) technique is a cutting-edge approach to arithmetic operations
[23]. The GDI technique, rooted in CMOS technology, enhances the performance of the multiplier by optimizing gate structures. In
the context of a 4-bit Vedic multiplier, this technique revolutionizes the design by strategically incorporating GDI-based gates. The
core of this multiplier lies in its ability to execute mathematical operations efficiently. Through the GDI technique, the multiplication
of two 4-bit numbers is achieved with reduced power consumption and improved speed. The GDI gates play a pivotal role in shaping
the logical operations involved in the multiplication process. This not only leads to computational efficiency but also addresses power
concerns, making the multiplier suitable for applications where energy efficiency is paramount [24,25]. The full adder designed using
modified GDI technique is shown in Fig. 8.
The ability to construct a wide range of complicated logic functions with just two transistors is a well-known feature of the
Gate Diffusion Input (GDI) technique. When compared to conventional CMOS and current PTL (Pass-Transistor Logic) approaches,
this methodology is exceptionally beneficial for developing fast and low power circuits, while using fewer transistors to accomplish
these goals. GDI also enhances logic level swing and static power characteristics Furthermore, it facilitates simple top-down design
methodologies by utilizing small cell libraries, thereby streamlining the overall design process [26].
A ripple carry adder is a circuit where the carry output from one full adder serves as the carry-in for the subsequent full adder,
causing the carry to ripple through each stage from input to output [27–29]. In a ripple carry adder the sum and carry out bits of
any half adder stage is not valid until the carry in of that stage occurs. The 4-bit Ripple Carry Adder (RCA) implementation involves
four full adders, each handling multiple bits in its operands. It takes three inputs and creates two outputs, a sum and a carry out. The
implementation of a 4-bit Ripple Carry Adder (RCA) based on modified Gate Diffusion Input (mGDI) which involves optimizing the
gate-level design for improved performance is depicted in Fig. 9.

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Fig. 9. mGDI based 4-bit RCA.
Fig. 10. mGDI based 4-bit CLA.
The carry look-ahead adder (CLA) offers a significant advantage over the ripple carry adder (RCA) in terms of speed and par-
allelism. In a ripple carry adder, each bit’s carry depends on the previous bit, causing a sequential carry propagation through the
entire adder. This leads to increased propagation delay, limiting the overall performance of the adder, especially for larger bit-widths
[30–33]. In contrast, a carry look-ahead adder utilizes parallelism by precomputing the carry signals independently of the input bits.
This results in a constant-time carry calculation, allowing for simultaneous determination of all carry bits without waiting for the
sequential carry propagation seen in ripple carry adders. The architecture of a 4-bit carry look-ahead adder typically consists of four
stages: input, generate, propagate, and sum. Each stage involves logic gates to perform specific functions. The architecture of CLA
includes four full adders and a carry look ahead adder generator block as illustrated in Fig. 10. In the carry look-ahead adder (CLA),
the carry generate (G) and carry propagate (P) stages play a crucial role in reducing carry propagation delay. In the carry generate
stage, the G signals (G[3:0] for a 4-bit adder) are generated by performing bitwise AND operations on corresponding input bits. The
carry propagate stage computes the P signals (P[3:0] for a 4-bit adder) through bitwise OR operations on the input bits. Combining
the G and P signals enables the carry look-ahead logic to efficiently determine the carry signals for each stage of the adder without
the need for sequential carry propagation.
A carry skip adder is a parallel adder designed to minimize the propagation delay typically encountered in the carry chain of
conventional adders such as ripple carry adders. It achieves this by introducing “skip logic” to allow for the parallel calculation of
carries across multiple blocks of bits. This design helps in speeding up the addition process, especially for larger bit-widths.
A carry-skip adder, also referred to as a carry-bypass adder, is a specific type of adder design crafted to diminish the propagation
delay that is inherent in ripple-carry adders, while maintaining minimal additional complexity. In an n-bit carry-skip adder, the
architecture typically integrates an n-bit carry-ripple-chain, an n-input AND-gate, and a multiplexer, as depicted in Fig. 11. Each
propagate bit produced by the carry-ripple-chain is directed into the n-input AND-gate. The output of this AND-gate acts as the select

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Fig. 11. mGDI based 4-bit CSA.
Fig. 12. Simulation output of 4-bit Vedic Multiplier using m-GDI Approach.

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Fig. 13. Comparison of Delay(ps) of 4-bit Vedic Multiplier for various Adder architectures.
Fig. 14. Comparison of Average Power (μW) of 4-bit Vedic Multiplier for various Adder architectures.
Fig. 15. Comparison of PDP of 4-bit Vedic Multiplier for various Adder architectures.

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Fig. 16. Comparison of Area (Transistor Count) of 4-bit Vedic Multiplier for various Adder architectures.
Fig. 17. Comparison of Delay(ps) of proposed 4-bit Vedic Multiplier with existed multiplier works.
Fig. 18. Comparison of Average Power (μW) of proposed 4-bit Vedic Multiplier with existed multiplier works.

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Fig. 19. Comparison of PDP of proposed 4-bit Vedic Multiplier with existed multiplier works.
Fig. 20. Comparison of Area (Transistor Count) of proposed 4-bit Vedic Multiplier with existed multiplier works.
bit for a multiplexer, enabling it to choose either the final carry-bit or the carry-in signal as the carry-out signal (c_out). This strategy
effectively circumvents the ripple-carry propagation delay in scenarios where the carry-in signal does not need to propagate through
the entire adder, thereby enhancing overall performance. Consequently, the carry is not obligated to propagate through all stages of
the adder in every input sequence. Carry-skip adders strike a balance between the speed benefits of carry look-ahead adders and the
hardware simplicity of ripple carry adders, rendering them suitable for various applications in arithmetic circuits and processors.
GDI (Gate Diffusion Input) technology, CMOS (Complementary Metal-Oxide-Semiconductor) technology, and TG (Transmission
Gate) technology are all widely used in VLSI (Very Large Scale Integration) design, each with its advantages and trade-offs in terms
of delay, area, power consumption, and PDP (Power-Delay Product).
5. Result analysis
The 4-bit vedic multiplier is designed using CMOS, Transmision gate and Gate Diffusion Input technology and then simulated
using Tanner EDA Tools. The key components and features of Tanner EDA Tools:
S-Edit (Schematic Editor): S-Edit is used for creating and editing schematic diagrams of electronic circuits.
T-Spice (SPICE Simulator): T-Spice is a SPICE (Simulation Program with Integrated Circuit Emphasis) simulator integrated into
Tanner EDA Tools.
W-Edit (Waveform Editor): W-Edit is a waveform editor that allows designers to create and analyze simulation waveforms.
Different adders like Ripple carry adders (RCA), Carry lookahead adders (CLA), and Carry skip adders (CSA) are utilized in the design
of multiplier. Fig. 12,shows a GDI-simulated 4-bit vedic multiplier waveform. Table 1compares the performance parameters such
as Delay, Avg Power, Power Delay Product (PDP), and area in terms of transistor count of the proposed vedic multiplier with CMOS

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K. Nishanth Rao, D. Sudha, O. Ibrahim Khalaf et al.
Table 1
Comparison of Delay, Power and TC for CMOS, TG and GDI based 4-bit Vedic Multiplier.
Parameter CMOS Transmission Gate(TG) Proposed m-GDI
RCA CLA CSA RCA CLA CSA RCA CLA CSA
Delay (ps) 76.3 47.07 45.8 73.8 46.7 41.7 65.6 37.5 32.3
Avg Power (μW) 35.6 105.6 37.3 26.5 87.9 29.6 24.8 78.5 27.3
PDP (𝑒−18 J) 2717 4970 1708 1955 4104 1234 1627 2943 881
Transistor Count(TC) 828 1032 900 444 1104 516 206 386 278
Table 2
Performance Comparison of Proposed 4-bit GDI based multiplier with other multipliers.
Existed Vedic Array Barun Baugh Wooley Proposed GDI
Multiplier Multiplier Multiplier Multiplier Vedic Multilplier
-GDI[12]-GDI[14]-GDI[14]-GDI[14]
Delay (ps) 320 159 189 187 65.6
Avg Power (μW) 58.1 109 78.9 121 24.8
PDP (𝑒−18 J) 18592 17331 14192 22627 1627
Transistor Count (TC) 242 296 296 382 206
and TG based multipiers. Table 2depicts the comparison with respect to parameters such as delay, power, PDP and Transistor Count
of the GDI based multiplier with that of Existed Vedic multiplier, Barun Multiplier array Multiplier and Baugh Wooley Multiplier.
In GDI based 4-bit Vedic multiplier, the total number of transistors is 206, 386, and 278 in the cases of RCA, CLA, CSA respectively,
as depicted in Fig. 16. In comparison to TG technology, the number of transistors used in CMOS technology has decreased by 75%,
whereas the number of transistors used in TG technology has decreased by 53%.
A 4 bit vedic multiplier built with GDI technology has a delay of 65.6 ps for RCA, 37.5 ps for CLA, and 32.3 ps for CSA as shown in
Fig. 13. There is a reduction of 12% delay in the multiplier when compared with TG, and there is a reduction of 14% when compared
with CMOS. Based on the GDI technology, the average power of a four-bit vedic multiplier that has been introduced is 24.8 μW for
RCA, 78.5 μW for CLA, and 27.3 μW for CSA as depicted in Fig. 14. When compared with CMOS technology there is a decrease of
30% and decrement of 6% is observed on comparison with TG Technology.
The designed 4-bit vedic multiplier has a power delay product of 1627𝑒−18 J in case of RCA, 2943𝑒−18 J in case of CLA and
881𝑒−18 J in case of CSA as shown in Fig. 15. There is a decrement of 40% when compared with CMOS and reduction of 16%
in comparison with Transmission gate technology. Comparison of Delay, Power, PDP, Transistor Count of proposed 4-bit Vedic
Multiplier with existed multiplier works are depicted in Fig. 17, Fig. 18, Fig. 19, Fig. 20 respectively.
6. Conclusion
This research explores the utilization of various adders like RCA, CSA, and CLA in the development of a 4-bit Vedic multiplier
employing CMOS, transmission gate, and GDI techniques. The performance of the proposed multiplier is compared to its CMOS and
TG-based counterparts using 32 nm technology. Through meticulous design and optimization, Vedic multipliers exhibit improved
performance metrics, including reduced delay, decreased transistor count, and enhanced power efficiency compared to alternative
designs. Specifically, the proposed GDI-based 4-bit Vedic Multiplier outperforms CMOS and TG circuits in terms of delay, power
consumption, and area utilization. In this Proposed Modified GDI (m-GDI) based four-bit Vedic multiplier, the RCA-based technique
consumes less power and occupies a smaller area, while the CSA-based method demonstrates lower delay and reduced power-delay
product (PDP) requirements.
Funding
The authors thank School of Electrical Engineering, Dept. of Electrical and Electronic Eng. Science, University of Johannesburg,
Johannesburg 2006 South Africa, VAT: 4900127681.
CRediT authorship contribution statement
K. Nishanth Rao: Writing – review & editing, Resources, Formal analysis. D. Sudha: Project administration, Formal analysis.
Osamah Ibrahim Khalaf: Supervision, Funding acquisition, Data curation. Ghaida Muttasher Abdulsaheb: Validation, Resources,
Formal analysis. Aruru Sai Kumar: Writing – original draft, Validation, Software, Methodology, Investigation, Conceptualization.
S. Siva Priyanka: Software, Project administration, Data curation. Khmaies Ouahada: Writing – review & editing, Resources, Project
administration, Funding acquisition. Habib Hamam: Visualization, Validation, Investigation.

Heliyon 10 (2024) e31120
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K. Nishanth Rao, D. Sudha, O. Ibrahim Khalaf et al.
Declaration of competing interest
The authors declare that they have no known competing financial interests or personal relationships that could have appeared to
influence the work reported in this paper.
Data availability
Data will be made available on request.
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