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Efficient Implementation of Multiplexer and Full-Adder Functions Based on Memristor Arrays for In-memory Computing
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The rise of emerging technologies such as Big Data, the Internet of Things, and artificial intelligence, which requires efficient power schemes, is driving brainstorming in data computing and storage technologies. In this study, merely relying on the fundamental structure of two memristors and a resistor, arbitrary Boolean logic can be reconfigured and calculated in two steps, while no additional voltage sources are needed beyond “±VP” and 0, and all state reversals are based on memristor set switching. Utilizing the proposed logic scheme in an elegant form of unity structure and minimum cost, the implementation of a 1‐bit adder is demonstrated economically, and a promising circuit scheme for the N‐bit adder is exhibited. Some critical issues including the crosstalk problem, energy consumption, and peripheral circuits are further simulated and discussed. Compared with existing works on memristive logic, such methods support building a memristor‐based digital in‐memory calculation system with high functional reconfigurability, simple voltage sources, and low power and area consumption. This study proposes and successfully verifies by experiments the 16 Boolean logics with a reconfigurable and uniform logic circuit consisted of two memristors and one resistor, implemented in two steps, demonstrating the advantages in speed, power, area, and implementation efficiency. 1‐bit full adder is demonstrated and N‐bit full adder scheme is proposed and discussed.
Brain‐inspired neural networks can process information with high efficiency, thus providing a powerful tool for pattern recognition and other artificial intelligent tasks. By adopting binary inputs/outputs, neural networks can be used to perform Boolean logic operations, thus potentially surpassing complementary metal–oxide–semiconductor logic in terms of area efficiency, execution time, and computing parallelism. Here, the concept of stateful neural networks consisting of resistive switches, which can perform all logic functions with the same network topology, is introduced. The neural network relies on physical computing according to Ohm's law, Kirchhoff 's law, and the ionic migration within an output switch serving as the highly nonlinear activation function. The input and output are nonvolatile resistance states of the devices, thus enabling stateful and cascadable logic operations. Applied voltages provide the synaptic weights, which enable the convenient reconfiguration of the same circuit to serve various logic functions. The neural network can solve all two‐input logic operations with just one step, except for the exclusive‐OR (XOR) needing two sequential steps. 1‐bit full adder operation is shown to take place with just two steps and five resistive switches, thus highlighting the high efficiencies of space, time, and energy of logic computing with the stateful neural network.
In-Memory computation has received considerable attention in the light of recent advances made in the memristor-based design. Non-volatile memristor devices are compatible with both the crossbar structure, CMOS technology, and can perform logical operations when subjected to suitable voltages. In this work, a generalized synthesis technique is presented to implement the logic functions inside pure memristive-crossbar. To initiate the process, two novel memristive-designs are proposed for 2:1 multiplexer (MUX) that follow Memristor Aided loGIC (MAGIC) design style. Experimental results showed that each design is at least 68.05 %, 35.92 % more energy-efficient than their existing IMPLY, MAGIC-based designs, respectively. One of our proposed MUX designs is optimized in memristor-count, and the other is latency-optimized. The latency-optimized design offers 20 % improvement in performance compared to its existing IMPLY, MAGIC-based peers. Based on the simulation methodology presented in this work, the memristive-MUXes are simulated in Cadence Virtuoso. Subsequently, our proposed MUX designs are used for the technology mapping of the nodes of the Binary Decision Diagrams (optimized in terms of node, path counts) for the logic functions. Our proposed technique optimizes the implemented logic circuits in terms of memristor-count, step-count, and provides the details for – latency, required memristors, energy, area. Comparison of the synthesis results showed that the circuits generated using our proposed MAGIC-MUXes, are at least 82.21 %, 44 % more energy-efficient, and can offer 18.94 %, 18.92 % more performance-improvements than their peers, realized using the existing IMPLY, MAGIC-MUX designs, respectively. Also, our proposed-MUX based circuits need at least 56.73 % lesser crossbar-areas than their existing MAGIC-MUX based peers, which indicates the scope for large scale parallel processing inside a given memristive-memory.
This paper presents and evaluates novel approaches to design efficient Memristor‐based multiplexers. Three novel algorithms and structures are proposed based on IMP logic operation. These novel algorithms and structures are developed based on Memristors and crossbar Nano wires. The proposed Memristor‐based multiplexers can store the output inside the Memristors. So, the proposed multiplexers have the ability to compute in memory. The proposed multiplexers are simulated using Pspice. The number of required Memristors and necessary steps to accumulate the output for the proposed 2 to 1 multiplexers is reduced in comparison with the former best MUXs. Moreover, these novel multiplexers are utilized to design ISCAS'85 benchmark circuits. The results show improvements in terms of total propagation delay and the required layout area. This paper presents and evaluates three new Memristor‐based multiplexers, which are designed based on novel algorithms and architectures. The proposed multiplexers' performances are considerably improved in comparison with former Memristor‐based multiplexers.
This paper proposes a novel memristor-based multiplexer implemented by using NOT-material implication. The proposed design can be extended to arbitrary N-bit inputs and the enable-port can be added to improve its structure. Furthermore, this structure can be applied in the cascade circuit and crossbar array. A novel peripheral read circuit is introduced to overcome the problem that it is difficult to read out the operation results stored in crossbar array with large scales. The feasibility and correctness of our design is verified by the HSPICE simulation results with VTEAM model.
This paper presents and evaluates a novel multiplexer (MUX) composed of memristive devices and nanowire crossbar arrays. The switching behavior of memristors is employed to reveal the desired output state. By applying a sequence of appropriate voltage pulses to the developed MUX, the output is derived and can be transferred through read/write CMOS circuitry. The performance is verified with the SPICE simulator including a threshold-type memristor model. Using the proposed MUXes instead of memristor-based NAND gates, the routing effects that are a major challenge for implementing combinational logic in hybrid circuits can be reduced. Our evaluation results show that both density and delay are effectively improved in pure-MUX-based fabrics.