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Low-Voltage Flip-Flop Operation with Transition Completion Detection
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—With the continuous growth of semiconductor
technologies, the design of high-speed circuits is a need of the
hour. Current Mode Logic (CML), a derivation from Emitter
Coupled Logic (ECL) is such an approach with concerns
present to be improvised. Targeting that, we have come up
with a new design of dynamic CML to structure a power
efficient D-Flipflop. The simulations are carried out for 90nm
CMOS using Synopsys H-Spice platform at a supply voltage
and operating frequency of 1.2V and 10GHz respectively. The
device footprint reads an area requirement of 108.624 µm2
(16.045µm × 6.77µm). This design is noted to dissipate a very
low power of 219.05uW and delay of as small as 31.30ps when
driven with aperiodic data of 2.5GHz.
Design and experimental evaluation of a new sense-amplifier-based
flip-flop (SAFF) is presented. It was found that the main speed
bottleneck of existing SAFF's is the cross-coupled set-reset (SR) latch
in the output stage. The new flip-flop uses a new output stage latch
topology that significantly reduces delay and improves driving
capability. The performance of this flip-flop is verified by
measurements on a test chip implemented in 0.18 μm effective channel
length CMOS. Demonstrated speed places it among the fastest flip-flops
used in the state-of-the-art processors. Measurement techniques employed
in this work as well as the measurement set-up are discussed in this
paper
A novel low-power bipolar circuit for Gb/s LSIs, current mirror
control logic (CMCL), is described. To reduce supply voltage and
currents, the current sources of emitter-coupled-logic (ECL) series gate
circuits are removed and the lower differential pairs are controlled by
current mirror circuits. This enables circuits with the same function as
two-stacked ECL circuits to operate at supply voltage of -2.0 V and
reduces the current drawn through the driving circuits for the
differential pairs to 50% of the conventional level shift circuits
(emitter followers) in ECL. This CMCL circuit achieves 3.1-Gb/s (D-FF)
and 4.3-GHz (T-FF) operation with a power supply voltage of -2.0 V and
power dissipation of only 1.8 mW/(FF)
This paper investigates the metastability of true single-phase clock (TSPC) D flip flops (DFFs) and its impact on the resolution of Vernier time-to-digital converters (TDCs). The mechanisms of the metastability of TSPC DFFs are investigated and the analytical expressions of setup time and hold time are obtained. A shunt capacitor technique capable of reducing setup time and hold time to zero with no power and delay penalty is proposed. The impact of PVT (process, voltage, temperature) on the effectiveness of the proposed technique is quantified using simulation. Vernier TDCs, both right-shifting and left-shifting, with untuned and tuned DFFs are designed in TSMC 130 nm 1.2 V CMOS technology and analyzed using Spectre with BSIM3V3 device models. Simulation results demonstrate TDCs with tuned DFFs enjoy zero conversion error while the right-shifting and left-shifting TDCs with untuned DFFs have 1-bit and 5-bit conversion errors or 11% and 56% error rates, respectively.
As basic components, optimizing power consumption of flip-flops (FFs) can significantly reduce the power of digital systems. In this article, an energy-efficient retentive true-single-phase-clocked (TSPC) FF is proposed. With the employment of input-aware precharge scheme, the proposed TSPC FF precharges only when necessary. In addition, floating node analysis and transistor level optimization are employed to further ensure the high energy efficiency of the FF without significantly increasing the area. Postlayout simulations based on SMIC 55-nm CMOS technology show that at a supply voltage of 1.2 V, the power consumption of the proposed FF is 84.37% lower than that of conventional transmission-gate flip-flop (TGFF) at 10% data activity. The reduction rate is increased to 98.53% as the data activity goes down to 0%. When the supply voltage decreases to 0.6 V, the proposed FF consumes only 0.411 fJ/cycle at 10% data activity, which is 84.23% lower than TGFF. Measurement results of ten test chips demonstrate the great energy efficiency of the proposed FF. Furthermore, the CK-to-Q delay of the proposed FF is 26.18% lower than that of TGFF at a supply voltage of 1.2 V.
Metastability events are common in digital circuits, and synchronizers are necessary to protect us from their deadly effects. Originally synchronizers were necessary when playing an asynchronous input (that is, one synchronized with the clock input so that could change exactly when the sample). Everything changes can easily be metastable. Switch its data input at the same time that the sampling edge of the clock and you get Metastability. The two signals relative duration of each cycle varies a little, and eventually leading to the metastability, close enough to each other switches. This combination of metastability with normal display devices, occur frequently. Recent semiconducting metal oxide progress (CMOS) additionally leads to unprecedented levels of integration in digital logic systems. Due to the propagation delay of the path and timing clock hold time configuration errors failure occurs in digital circuits. Depending on the application, errors are described by number of deferent terms, including “synchronization failure error” and “Metastability error”. The underlying mechanism for all of these problems is the same, and these terms “Metastability error” is the largest, because it describes the failure of the element in the circuit and not to the application. The reference signal may be either a reference voltage on the base, for example a bias voltage or a reference based on the time, as a clock signal.
In this paper, detailed analysis is given on the design of metastable-hardened and soft-error tolerant flip-flops while maintaining the basic characteristics of low-power and high-performance. We also propose two new flip-flop designs: pre-discharge soft-error tolerant flip-flop (PDFF-SE) and sense-amplifier transmission-gate soft-error tolerant flip-flop (SATG-SE). Following our main design approach, both PDFF-SE and SATG-SE use a cross-coupled inverter on the critical path in the master-stage to achieve good metastability while generating differential signals to facilitate the usage of the Quatro cell in the slave-stage to protect against soft-errors. PDFF-SE is designed to achieve very high performance with good metastability while SATG-SE is a low-power design also with good metastability. We also introduce two new design metrics, namely the metastability-delay-product (MDP) and the metastability-power-delay-product (MPDP), to analyze the design tradeoffs between metastability, power, and performance. Simulation results in 65 nm CMOS technology have shown that both proposed designs achieve significant reduction in MDP and MPDP when compared to other flip-flop architectures analyzed in this work. Monte Carlo simulation results also show that these flip-flops are very robust and reliable against process variations and mismatches.
In this paper, we analyze and characterize the metastability of 11 previously proposed high-performance flip-flops, reduced clock-swing flip-flops, and level-converting flip-flops. From extensive simulation results in 65nm CMOS technology, the main metastability parameters of ¿ and T<sub>0</sub> are extracted and analyzed at both nominal and reduced supply voltage. Our simulation results indicate that these flip-flops exhibit a wide range (up to few orders of magnitudes) of metastability windows. In particular, flip-flops with differential and positive feedback configuration such as the sense-amplifier based flip-flops demonstrate the most optimal metastability. Based on this finding, a novel pre-discharge flip-flop (PDFF) with positive feedback configuration is proposed. Extensive simulation results reveal that PDFF achieves better metastability than the previous proposed flip-flops at both nominal voltage supply and nominal voltage supply with reduced clock-swing.
A three-valued D-flip-flop (D-FF) circuit and a two-stage shift register built from InGaAs-based multiple-junction surface tunnel transistors (MJSTT) and Si-based metal-oxide-semiconductor field effect transistors (MOSFET) have been demonstrated. Due to the combination of the MJSTTs latching function and the MOSFETs switching function, the number of devices required for the D-FF circuit was greatly reduced to three from the thirty required for the FET-only circuit.
Design of High-Speed Master – Slave D-Type
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