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Reducing charge noise in quantum dots by using thin silicon quantum wells

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Charge noise in the host semiconductor degrades the performance of spin-qubits and poses an obstacle to control large quantum processors. However, it is challenging to engineer the heterogeneous material stack of gate-defined quantum dots to improve charge noise systematically. Here, we address the semiconductor-dielectric interface and the buried quantum well of a ²⁸Si/SiGe heterostructure and show the connection between charge noise, measured locally in quantum dots, and global disorder in the host semiconductor, measured with macroscopic Hall bars. In 5 nm thick ²⁸Si quantum wells, we find that improvements in the scattering properties and uniformity of the two-dimensional electron gas over a 100 mm wafer correspond to a significant reduction in charge noise, with a minimum value of 0.29 ± 0.02 μeV/Hz½ at 1 Hz averaged over several quantum dots. We extrapolate the measured charge noise to simulated dephasing times to CZ-gate fidelities that improve nearly one order of magnitude. These results point to a clean and quiet crystalline environment for integrating long-lived and high-fidelity spin qubits into a larger system.
Quantum dots and charge noise measurements a False colored SEM-image of a double quantum dot system with a nearby charge sensor. Charge noise is measured in the multi-electron quantum dot defined by accumulation gates SDLAcc and SDRAcc (blue), plunger P (blue), with the current going along the black arrow. In these experiments, the gates defining the double quantum dot (red) are used as screening gates. There is an additional global top gate (not shown) to facilitate charge accumulation when needed. b Source-drain current ISD through a charge sensor device fabricated on heterostructure C against the plunger gate voltage VP. Colored dots mark the position of the flank of the Coulomb peak where charge noise measurements are performed. The inset shows Coulomb diamonds from the same device, plotted as the differential of the current dI/dV as a function of VP and the source drain bias VSD. c Charge noise spectrum Sϵ measured at the Coulomb peak at VP ≃ 360.3 mV in b and extracted using the lever arm from the corresponding Coulomb diamond. The black trendline is proportional to 1/f. dSϵ for the same device in b, plotted in 3D as a function of f and VP. The dark gray plane is a fit through the datasets, i.e. the collection of noise spectra as in c measured at different VP and each obtained using a unique lever arm from the corresponding Coulomb diamond. e Line cut through the data in d at f = 1 Hz, showing the experimental noise Sϵ (colored dots) and fit (dark gray line). The black circled data point (also in d) marks the minimum charge noise measured for this specific device (Sϵ,min) at f = 1 Hz.
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Article https://doi.org/10.1038/s41467-023-36951-w
Reducing charge noise in quantum dots by
using thin silicon quantum wells
Brian Paquelet Wuetz
1
, Davide Degli Esposti
1
, Anne-Marije J. Zwerver
1
,
Sergey V. Amitonov
1,2
, Marc Botifoll
3
, Jordi Arbiol
3,4
, Amir Sammak
2
,
Lieven M. K. Vandersypen
1
, Maximilian Russ
1
& Giordano Scappucci
1
Charge noise in the host semiconductor degrades the performance of spin-
qubits and poses an obstacle to control large quantum processors. However, it
is challenging to engineer the heterogeneous material stack of gate-dened
quantum dots to improve charge noise systematically. Here, we address the
semiconductor-dielectric interface and the buried quantum well of a 28Si/SiGe
heterostructure and show the connection between charge noise, measured
locally in quantum dots, and global disorder in the host semiconductor,
measured with macroscopic Hall bars. In 5 nm thick 28Si quantum wells, we nd
that improvements in the scattering properties and uniformity of the two-
dimensional electron gas over a 100 mm wafer correspond to a signicant
reductioninchargenoise,withaminimumvalueof0.20.02μeV/Hz½at
1 Hz averaged over several quantum dots. We extrapolate the measured charge
noise to simulated dephasing times to CZ-gate delities that improve nearly
one order of magnitude. These results point to a clean and quiet crystalline
environment for integrating long-lived and high-delity spin qubits into a
larger system.
Spin-qubits in silicon quantum dots are a promising platform for
building a scalable quantum processor because they have a small
footprint1, long coherence times2,3, and are compatible with advanced
semiconductor manufacturing4. Furthermore, rudimentary quantum
algorithms have been executed5and quantum logic at high-delity
performed69. As the qubit count is increasing, with a six-qubit pro-
cessor demonstrated10,signicant steps have been taken to couple
silicon spin qubits at a distance, via microwave photons or spin
shuttling1116, towards networked spin-qubit tiles17. However, electrical
uctuations associated with charge noise in the host semiconductor
can decrease qubit readout and control delity18.Reducingcharge
noise independently of the device location on a wafer is pivotal to
achieving the ubiquitous high-delity of quantum operations, within
and across qubit tiles, necessary to execute more complex quantum
algorithms.
Charge noise is commonly associated with two-level uctuators
(TLF)19 in the semiconductor host. In gated heterostructures with
buried quantum wells, TLF may arise from impurities in several
locations: within the quantum well, the semiconductor barrier, the
semiconductor/dielectric interface, and the dielectrics layers
above2026. Furthermore, previous work on strained-Si MOSFETs2729,
with strained-Si channels deposited on SiGe strain relaxed buffers,
has associated charge noise with dislocations arising from strain
relaxation, either deep in the SiGe buffer or at the quantum well/
buffer interface. Since these impurities and dislocations are ran-
domly distributed over the wafer and are also a main scattering
source for electron transport in buried quantum wells30, a holistic
approach to materials engineering should be taken to address dis-
order in two-dimensional electron gases and charge noise in
quantum dots.
Received: 30 September 2022
Accepted: 25 February 2023
Published online: 13 March 2023
Check for updates
1
QuTech and Kavli Institute of Nanoscience, Delft University of Technology, PO Box 5046, 2600 GA Delft, The Netherlands.
2
QuTech and Netherlands
Organisation for Applied Scientic Research (TNO), Delft, The Netherlands.
3
Catalan Institute of Nanoscience and Nanotechnology (ICN2), CSIC and BIST,
Campus UAB, Bellaterra, 08193 Barcelona, Catalonia, Spain.
4
ICREA, Pg. Lluís Companys 23, 08020 Barcelona, Catalonia, Spain.
e-mail: g.scappucci@tudelft.nl
Nature Communications |(2023)14:1385 1
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In this work, we demonstrate thin quantum wells in 28Si/SiGe
heterostructures with low and uniform charge noise, measured over
several gate-dened quantum dot devices. By linking charge noise
measurements to the scattering properties of the two-dimensional
electron gas, we show that a quiet environment for quantum dots is
obtained by improving the semiconductor/dielectric interface and
the crystalline quality of the quantum well. We feed the measured
charge noise into a theoretical model, benchmark the model against
recent experimental results6,10, and predict that these optimized
heterostructures may support long-lived and high-delity spin
qubits.
Results
Description of 28Si/SiGe heterostructures
Figure 1a illustrates the undoped 28Si/SiGe heterostructures, grown
by reduced-pressure chemical vapor deposition, and the gate-stack
above. From bottom to top, the material stack comprises a 100 mm Si
substrate, a strain-relaxed SiGe buffer layer, a strained 28Si quantum
well, a 30 nm thick SiGe barrier, a Si cap oxidized in air to form a SiO
x
layer, an AlO
x
layer formed by atomic layer deposition, and metallic
gates.TheSiGelayersaboveandbelowthequantumwellhaveaGe
concentration of 0.3 (Methods).
We consider three 28Si/SiGe heterostructures (A, B, C) to improve,
in sequence, the semiconductor/dielectric interface (from A to B) and
the crystalline quality of the quantum well (from B to C).
Heterostructure A has an 9 nm thick quantum well and is terminated
with an epitaxial Si cap grown by dichlorosilane at 675°C. This kind of
heterostructure has already produced high performance spin-
qubits6,10,31. Heterostructure B misses a nal epitaxial Si cap but fea-
tures an amorphous Si-rich layer obtainedby exposing the SiGe barrier
to dichlorosilane at 500°C. Compared to A, heterostructure B sup-
ports a two-dimensionalelectron gaswith enhancedand more uniform
transport properties across a 100 mm wafer, owing to a more uniform
SiO
x
layer with less scattering centers32. Finally, we introduce here
heterostructure C, having the same amorphous Si-rich termination as
in heterostructure B, but a thinner quantum well of 5 nm (Supple-
mentary Fig. 1). This is much thinner than the Matthews-Blakeslee
critical thickness33,34, which is 10 nm35 for the relaxation of tensile Si
on Si
0.7
Ge
0.3
via the formation of mist dislocation at the bottom
interface of the quantum well. In light of recent morphological char-
acterization by electron channeling constrast imaging of Si/SiGe het-
erostructures with similar quantum well thickness and SiGe chemical
composition36,weexpectmist dislocation segments in hetero-
structure B because the quantum well approaches the Matthews-
Blakeslee critical thickness. Due to the much thinner quantum well,
instead, the epitaxial planes may adapt to the SiGe buffer much better
in heterostructure C than in heterostructure B, meaning that mist
dislocations are, in principle, suppressed.
Figure 1b, c shows bright-eld scanning transmission electron
microscopy (BF-STEM) images from heterostructure C after
a
28Si
SiOx
SiGe
SiGe
AlOx
z
b
c
10 nm
28Si
SiOx
SiGe
SiGe
SiGe
AlOx
10 nm
0 2 4 6
0.0
0.5
1.0
1.5
2.0
2.5
1 2
10
1
10
2
n (1011 cm-2)n (1011 cm-2)
µ (105 cm2/Vs)
σxx (e2/h)
de
Fig. 1 | Material stack and heterostructure eld effect transistor characteriza-
tion. a Schematics of the 28Si/SiGe heterostructure and dielectric stack above. z
indicates the heterostructure growth direction. Circles represent remoteimpurities
at the semiconductor/dielectric interface and perpendicular symbols represent
mist dislocations that might arise at the quantum well/buffer interface due to
strain relaxation. b,cBF-STEM images from heterostructure C highlighting the
semiconductor/dielectric interface and the 5nm thick 28Si quantum well, respec-
tively. dMobility μand econductivity σ
xx
measured as a function of density nat a
temperature of1.6 K in a Hall bar H-FET from heterostructure C.The red curve in eis
at to percolation theory.
Article https://doi.org/10.1038/s41467-023-36951-w
Nature Communications |(2023)14:1385 2
Content courtesy of Springer Nature, terms of use apply. Rights reserved
fabrication of a Hall bar shaped heterostructure eld effect transistors
(H-FET). We observe a sharp SiGe/SiO
x
semiconductor/dielectric
interface (Fig. 1b), characterized by a minor Ge pile up (dark line) in line
with ref. 32.The5nmthickquantumwell(Fig.1c, Supplementary
Fig. 1) is uniform, has sharp interfaces to the nearby SiGe, and appears
of high crystalline quality.
Electrical characterization of heterostructure eld effect
transistors
We evaluate the scattering properties of the two-dimensional electron
gases by wafer-scale electrical transport measured on Hall-bar shaped
H-FETs operated in accumulation mode (Methods). For each hetero-
structure, multiple H-FETs over a wafer are measured in the same cool-
down at a temperature of 1.7 K in refrigerators equipped with cryo-
multiplexers37. Figure 1d, e shows typical mobility-density and
conductivity-density curves for heterostructure C, from which we
extract the mobility measured athigh density (n=6×10
11 cm2)andthe
percolation density (n
p
)38. The mobility rises steeply at low density due
to progressive screening of scattering from remote impurities and
attens at higher density (n>5×10
11 cm2), limited by scattering from
impurities within or nearby the quantum well, for example uniform
background charges, surface roughness, or crystalline defects such as
threading or mist dislocations30,39.
Charge noise measurements in quantum dots
For charge noise measurements, we use devices comprising a double
quantum dot and a charge sensor quantum dot nearby, illustrated in
Fig. 2a. Using the same device design, two-qubit gates with delity
above 99% were demonstrated6, silicon quantum circuits were con-
trolled by CMOS-based cryogenic electronics31, and energy splittings in
28Si/SiGe heterostructures were studied with statistical signicance40.
Here, we electrostatically dene a multi-electron quantum dot
in the charge sensor by applying gate voltages to the accumulation
gates SDRAcc and SDLAcc, the barriers SDLB and SDRB, and the
plunger gate P. All other gates (red in Fig. 2a) are set to 0 V for
measurements of heterostructure B and C, whereas they are posi-
tively biased in heterostructure A to facilitate charge accumulation
in the sensor (Methods). Figure 2b shows typical Coulomb blockade
oscillations of the source-drain current I
SD
for a charge sensor from
heterostructure C measured at a dilution refrigerator base tem-
perature of 50 mK. We follow the same tune-up procedure (Meth-
ods) consistently for all devices and we measure charge noise at the
ank of each Coulomb peak within the V
P
range dened by the rst
peak observable in transport and the last one before onset of a
background channel (Supplementary Figs. 24). For example, in
Fig. 2b we consider Coulomb peaks within the V
P
range from 260 mV
to 370 mV. The data collected in this systematic way is taken as a
basis for comparison between the three different heterostructures
in this study.
For each charge noise measurement at a given V
P
we acquire
60 s (heterostructure A) or 600 s (heterostructures B, C) long traces
of I
SD
and split them into 10 (heterostructure A) or 15 windows
(heterostructures B, C). We obtain the current noise spectrum S
I
by
averaging over the 10 (15) windows the discrete Fourier transform of
the segments (Methods). We convert S
I
to a charge noise spectrum
S
ϵ
using, for each measurement at a given V
P
, the unique lever arm
c
a
d
SDLB
SDRB
SDLAcc
SDRAcc
P
b
200 nm
z260 280 300 320 340 360 380
50
100
150
200
260 280 300 320 340 360 380
50
100
150
200
VP (mV)
ISD (pA)
340 345 350 355 360
0
500
−2.5
0.0
2.5
1e−12
VP (mV)
VSD (µV)
dI/dV (nA/mV)
10−1 100101
10−14
10−13
10−12
10−11
f (Hz)
Sε (eV2/Hz)
1/f
10−1
100
101
250
300
350
10−14
10−13
10−12
10−11
10−10
V
P
(mV)
f (Hz)
Sε (eV2/Hz)
300 350
10
−13
10
−12
10
−11
Sε (eV2/Hz)
V
P
(mV)
e
Fig. 2 | Quantum dots and charge noise measurements. a False colored SEM-
imageof a double quantumdot system with a nearby chargesensor. Chargenoise is
measured in the multi-electron quantum dot dened by accumulation gates
SDLAccand SDRAcc (blue), plunger P (blue),with the current goingalong the black
arrow. In these experiments, the gates dening the double quantum dot (red) are
used as screening gates. There is an additional global top gate (not shown) to
facilitate charge accumulation when needed. bSource-drain current I
SD
through a
charge sensor device fabricated on heterostructure C against the plunger gate
voltage V
P
. Colored dots mark theposition of the ank of the Coulomb peak where
charge noise measurements are performed. The inset shows Coulomb diamonds
from thesame device, plotted asthe differentialof the currentdI/dV as a functionof
V
P
and the source drain bias V
SD
.cCharge noise spectrum S
ϵ
measured at the
Coulomb peak at V
P
360.3 mV in band extracted using the lever arm from the
corresponding Coulomb diamond. The black trendline is proportional to 1/f.dS
ϵ
for the same device in b, plotted in 3D as a function of fand V
P
. The dark gray plane
is a t through the datasets, i.e. the collection of noise spectra as in cmeasured at
different V
P
and each obtained using a unique lever arm from the corresponding
Coulomb diamond. eLine cut through the data in dat f= 1 Hz, showing the
experimental noise S
ϵ
(colored dots) and t (dark grayline). Theblack circled data
point (also in d) marks the minimumcharge noise measured for this specicdevice
(S
ϵ,min
)atf= 1 Hz.
Article https://doi.org/10.1038/s41467-023-36951-w
Nature Communications |(2023)14:1385 3
Content courtesy of Springer Nature, terms of use apply. Rights reserved
from the corresponding Coulomb diamonds and slope of the Cou-
lomb peak to take into account a possible deformation of the charge
sensor with the increasing electron number (inset Fig. 2b, Methods,
and Supplementary Fig. 5). A representative charge noise spectrum
S
ϵ
measured at V
P
= 360.3 mV is shown in Fig. 2c. We observe an
approximate 1/ftrend at low frequency, pointing towards an
ensemble of TLF with a broad range of activation energies affecting
charge noise around the charge sensor41,42. Figure 2e shows the
charge noise S
ϵ
at 1 Hz as a function of V
P
. The charge noise
decreases, with a linear trend, with increasing V
P
, suggesting that,
similar to scattering in 2D, screening by an increased electron den-
sity shields the electronically active region from noise arising from
the heterostructure and the gate stack43. From this measurement we
extract, for a given device, the minimum measured charge noise at 1
Hz (S
ϵ,min
circled data point in Fig. 2e) upon variation of V
P
in our
experimental range. We use S
ϵ,min
as an informative metric to com-
pare charge noise levels from device to device in a given hetero-
structure. For a given device, all charge noise spectra S
ϵ
are plotted
in 3D as a function of fand V
P
(Fig. 2d). To quantify our observations,
we t the data to the plane log Sϵ=αlog f+βVP+γ(Supplemen-
tary Note 4). Coefcient α= 0.84 ± 0.01 indicates the spectrum
power law exponent and coefcient β=15.6 ± 0.1 mV1quanties
the change in noise spectrum with increasing plunger gate and,
consequently, the susceptibility of charge noise to the increasing
electron number in the sensor.
Distribution of transport properties and charge noise
We have introduced key metrics for 2D electrical transport (μ,n
p
)and
charge noise (α,βand S
ϵ,min
) from Hall bar and quantum dot mea-
surements, respectively. In Fig. 3ae we compare the distributions of
all thesemetrics for the three heterostructures A, B, C. Each box-plot is
obtained from the analysis of measurements in Figs. 1d, e, and 2d
repeated on multiple H-FETs or quantum dots, on dies randomly
selected from different locationsacross the 100 mm wafers(Methods).
To facilitate a comparison with previous studies, the minimum charge
noise at 1 Hz is plotted in Fig. 3easS1=2
ϵ,min and therefore in units of
μeV/Hz½.
As reported earlier in ref. 32, the improvement in both mean values
and spread for μand n
p
was associated with a reduction of remote
impurities when replacing the epitaxial Si cap in heterostructure A
with a Si-rich passivation layer in heterostructure B. Moving to
heterostructure C, we measure a high mean mobility of
(2.10 ± 0.08) × 105cm2/Vs and a low mean percolation density of
(7.68 ± 0.37) × 1010 cm2, representing an improvement by a factor 1.4
and 1.3, respectively (compared to heterostructure A). Most strik-
ingly, the 99% condence intervals of the mean for μand n
p
are dras-
tically reduced by a factor 9.8 and 4.8, respectively. We speculate
that these improvements in heterostructure C are associated with the
suppression of mist dislocations at the quantum well/buffer inter-
face, thereby reducing short range scattering and increasing uni-
formity on a wafer-scale. This interpretation is supported by previous
ba
μ(105cm2/Vs)
n
p
(10
11
cm
−2
)
β(mV
-1
)
S
1/2
εmin
(1 Hz) eV/Hz
1/2
)
ce
α
A B C
0
1
2
3
A B C
0.8
1.0
1.2
1.4
1.6
A B C
0.8
1.0
1.2
1.4
1.6
1.8
A B C
−40
−20
0
A B C
10 −1
10
0
d
Fig. 3 | Distribution oftransport properties and charge noise. a,bDistributions
of mobility μmeasured at n=6×10
11 cm2and percolation density n
p
for hetero-
structure A (red, 20 H-FETs measured, of which 16 reported in ref. 32), B (blue, 16
H-FETs measured of which 14 reported in ref. 32), and C (green, 22 H-FETs mea-
sured). ceDistributions of noise spectrum power law exponent α, coefcient β
indicating the change in noise spectrum with increasing V
P
, and minimum charge
noise S1=2
ϵ,min within therange of V
P
investigated for heterostructure A (red, 4 devices
measured), B (blue, 7 devices measured), and C (green, 5 devices measured).
Quartile box plots, mode (horizontal line), means (diamonds), 99% condence
intervals of the mean (dashed whiskers), and outliers (circles) are shown.
Article https://doi.org/10.1038/s41467-023-36951-w
Nature Communications |(2023)14:1385 4
Content courtesy of Springer Nature, terms of use apply. Rights reserved
studies of mobility limiting mechanisms as a function of the quantum
well thickness in strained Si/SiG e heterostructures39. We speculate that
further reducing the quantum well thickness could increase surface
roughness scattering from the bottom interface, and therefore dis-
order. Instead, ne-tuning the quantum well thickness between 5 nm
and 9 nm might minimize surface roughness scattering whilst still
avoiding the formation of mist dislocations.
We now shift our attention to the results of charge noise mea-
surements. First, the power law exponent α(Fig. 3c) shows a mean value
1, however the 99% condence interval and interquartile range
increase when moving from heterostructure A to B and C. Next, we
observe a decreasing trend for the absolute mean value of coefcient β
(Fig. 3d), meaning that the noise spectrum is less susceptible to changes
in V
P
. Finally, Fig. 3e shows the distributions for S1=2
ϵ,min, the minimum
charge noise at 1 Hz upon varying V
P
.Wend in heterostructure C
an almost order of magnitude reduction in mean S1=2
ϵ,min to 0.29 ± 0.02
μeV/Hz½.Thistrendisconrmed by plotting the distributions of max-
imum charge noise at 1 Hz upon varying V
P
(Supplementary Fig. 4).
Furthermore, within the distribution of S1=2
ϵ,min for heterostructure C, the
minimum value of the measured charge noise as a function of V
P
and
across quantum dots is 0.15 μeV/Hz½. These charge noise values are on
par or compare favorably to the best values reported previously at 1 Hz
in gate dened quantum dots. In multi-electron quantum dots, charge
noise of 0.47 μeV/Hz½was reported for Si/SiGe44,0.6μeV/Hz½
(average value, with a minimum of 0.2 μeV/Hz½)forGe/SiGe
45,
0.49 ± 0.1 μeV/Hz½for Si/SiO
2
46,and1μeV/Hz½for InSb47.Insingle-
electron quantum dots, charge noise of 0.33 μeV/Hz½was reported for
Si/SiGe48 and 7.5 μeV/Hz½for GaAs49.
We understand the charge noise trends in Fig. 3ce by relating
them to the evolution of the disorder landscape moving from het-
erostructures A to B and C, as inferred by the electrical transport
measurements in Fig. 3a, b. The narrow distribution of αin hetero-
structure A points to charge noise being dominated from many TLFs
possibly located at the low quality semiconductor/dielectric interface
and above, albeit other sources of charge noise in the surrounding
environment of the quantum dot may be present, such as highly
localized mist dislocations arising from partial strain relaxation in the
quantum well or other nearby uctuators. With a better semi-
conductor/dielectric interface, the effect of these other nearby uc-
tuators emerges in heterostructure B and C as a larger spread of the
frequency exponent α, indicating a nonuniform distribution of acti-
vation energies according to the Dutta-Horn model50. Yet, the noise
spectra still follow a 1/f-like behavior (Supplementary Fig. 3), sug-
gesting that TLFs also experience slow temperature uctuations42.The
electrical transport measurements support this interpretation: scat-
tering from many remote impurities is dominant in heterostructureA,
whereas with a better semiconductor/dielectric interface remote
scattering has less impact in the transport metrics of hetero-
structures B and C.
The decreasing trend in βis in line with the observation from
electrical transport. As the impurity density decreases from hetero-
structure A to B and C, charge noise is less affected by an increasing V
P
,
since screening of electrical noise through adding electrons to the
chargesensor becomes less effective. While we are notable to measure
directly the electron number in the charge sensor, we deem unlikely
the hypothesis that charge sensors in heterostructure A are operated
with considerably fewer electrons than in heterostructure C. This is
because all operation gate voltages in heterostructure A are con-
sistently larger than in heterostructure C (Supplementary Fig. 4), due
to the higher disorder.
Finally, the drastic reduction in mean value and spread of S1=2
ϵ,min
mirrors the evolution of mean value and spread of n
p
and μ. From
heterostructure A to B, a reduction in scattering from remote impu-
rities is likely to result inless charge noise from long-range TLFs. From
heterostructure B to C, the reduction in the possible number of
dislocations at the quantum well/buffer interface, further reduces the
charge noise picked up by quantum dots. This explanation is based on
earlier studies of charge noise in strained Si-MOSFETs2729,which
showed a correlation between low-frequency noise spectral density
and static device parameters. Dislocations at the bottom of the
strained channel may act as scattering centers that degrade mobility
and as traps for the capture and release of carriers, which causes noise
similarly to traps at the dielectric interface.
Calculated dephasing time and indelity
To emphasize the improvement of the electrical environment in the
semiconductor host, we calculate the dephasing time T?
2of charge and
spin qubits assuming these qubits experience the same uctuations as
our 28Si/SiGe quantum dots. The dephasing time of a qubit (in the
quasistatic limit and far-off from a sweet spot) is given by51,52
T?
2=h
ffiffiffi
2
pπσ ð1Þ
with the Planck constant hand the standard deviation
σ2=E
μ
2
×2Zfhigh
flow
S2
ϵ
fαdf :ð2Þ
Importantly, both the charge noise amplitude S2
ϵðfÞand the
noise exponent αhave a strong impact on the dephasing time while
the low and high frequency cut-off, f
low
and f
high
, given by the
duration of the experiment have a weaker impact. The prefactor E
μ
translates shifts in chemical potential of the charge sensor into
energy shifts of the qubit and depends on many parameters such as
the type of qubit and the device itself. We nd E
μ= 1 for a charge
qubit53 and E
μ105for an uncoupled spin- qubit44 (see Supple-
mentary Note 7 for a derivation of these numbers and the used
frequency bandwidths).
Figure 4a shows the computed dephasing times of charge qubits
(circle) and spin qubits (star) for all three heterostructures. These
calculations represent a best case scenario, since we use the distribu-
tion of measured S
ϵ,min
from Fig. 3as input parameter for each het-
erostructure. The improvements in our material can be best seen by
investigating T?
2of the charge qubit since it is directly affected by
charge noise. Our theoretical extrapolation shows two orders of
magnitude improvement in T?
2by switching from heterostructures A
to heterostructures B and C. One order is gained from the reduced
charge noise amplitude and another order is gained through a more
benecial noise exponent α> 1. Note, that the integration regimes
differ for spin and charge qubits due to the different experimental
setups and operation speeds44,53. For potential spin qubits in hetero-
structure A the calculated T?
2shows an average T?
2=8:4±5:6μs. This
distribution compares well with the distribution T?
2=6:7±5:6μsof
experimental T?
2data from state-of-the-art semiconductor spin qubits
in materials with similar stacks as in heterostructure A6,10.Notethat
while such comparisons oversimplify actual semiconductor spin-qubit
devices by reducing them to a single number, they fulll two aims.
They allow us to benchmark the computed performance of hetero-
structure A to past experiments and provide a prognosis on the qubit
quality in novel material stacks. Heterostructures B and C, in this case,
may support average dephasing times of T?
2=24:3±12:5μsand
T?
2=36:7±18 μs, respectively. The highest values T?
2=70:1μshints
towards a possible longdephasing time for spin qubits, previously only
reported in ref. 2.
Figure 4b shows the simulated indelity, a metric to measure
the closeness to the ideal operation, of a universal CZ-gate between
two spin qubits following ref. 6and Supplementary Note 7. Note that
the device used in ref. 6has the same architecture as our test devices.
In the CZ-gate simulation, noise couples in dominantly via barrier
Article https://doi.org/10.1038/s41467-023-36951-w
Nature Communications |(2023)14:1385 5
Content courtesy of Springer Nature, terms of use apply. Rights reserved
voltage uctuations which affects the interaction between the
electron spins. Again, we use the charge noise amplitude S
ϵ,min
and
exponent αfrom the quantum dot experiments in Fig. 3as input for
the simulations. The simulations show an averaged average gate
indelity 1 FCZ =0:02 ± 0:01% which means on average a single
error every 5000 runs. We also observe a saturation value close to
1F=10
4which arises from single-qubit dephasing T?
2=20 μs used
in the simulations estimated from nuclear spin noise due to a 800
ppm concentration of the 29Si silicon isotope which has a non-zero
nuclear spin44.
Discussion
In summary, we have measured electron transport and charge noise in
28Si/SiGe heterostructures where we improve the semiconductor/
dielectric interface, by adopting an amorphous Si-rich passivation, and
the structural quality of the quantum well, by reducing the quantum
well thickness signicantly below the Matthew-Blakeslee critical
thickness for strain relaxation. We relate disorder in 2D to charge noise
in quantum dots by following a statistical approach to measurements.
A reduction of remote impurities and dislocations nearby the quantum
well is connected with the key improvements in the scattering prop-
erties of the 2D electron gas, such as mobility and percolation density,
and their uniformity across a 100 mm wafer. The trend observed from
electron transport in 2D is compatible with the observations from
measurements of charge noise in quantum dots. As remote impurities
are reduced, charge noise becomes more sensitive to local uctuators
nearby the quantum well and less subject to screening by an increased
number of electrons in the dot. Furthermore, with this materials
optimization, we achieve a statistical improvement of nearly one order
of magnitude in the charge noise supported by quantum dots. Using
the charge noise distribution as input parameter and benchmarking
against published spin-qubit data, we predict that our optimized
semiconductor host could support long-lived and high-delity spin
qubits. We envisage that further materials improvements in the
structural quality of the quantum well, in addition to the commonly
considered semiconductor/dielectric interface, may lead system-
atically to quantum dots with less noise and to better qubit
performance.
Methods
Si/SiGe heterostructure growth
The 28Si/SiGe heterostructures are grown on a 100-mm n-type
Si(001) substrate using an Epsilon 2000 (ASMI) reduced pressure
chemical vapor deposition reactor. The reactor is equipped with a
28SiH
4
gas cylinder (1% dilution in H
2
) for the growth of isotopically
enriched 28Si. The 28SiH
4
gas was obtained by reducing 28SiF
4
with a
residual 29Si concentration of 0.08%54. Starting from the Si substrate,
the layer sequence of all heterostructures comprises a 3 μm step-
graded Si
(1x)
Ge
x
layer with a nal Ge concentration of x= 0.3
achieved in four grading steps (x= 0.07, 0.14, 0.21, and 0.3), fol-
lowed by a 2.4 μmSi
0.7
Ge
0.3
strain-relaxed buffer. The hetero-
structures differ for the active layers on top of the strain-relaxed
buffer. Heterostructure A has a 9 nm tensile strained 28Si quantum
well, a 30 nm Si
0.7
Ge
0.3
barrier, and a sacricial 1 nm epitaxial Si cap.
Heterostructure B has an 9 nm tensile strained 28Si quantum well, a
30 nm Si
0.7
Ge
0.3
barrier, and a sacricial passivated Si cap grown at
500 °C. Heterostructure C has a 5 nm tensile strained 28Si quantum
well, a 30 nm Si
0.7
Ge
0.3
barrier, and a sacricial passivated Si cap
grown at 500 °C. A typical secondary ions mass spectrometry of our
heterostructures is reported in Supplementary Fig. S13 of ref. 40 and
the Ge concentration in the SiGe layers is conrmed by quantitative
electron energy loss spectroscopy (EELS).
ab
T2
(μs)
1-FCZ
A B C
10
−5
10
−4
10
−3
10
−2
10
−1
10
0
10
1
10
2
spin qubit
spin qubit literature
charge qubit
A B C
10
−4
10
−3
10
−2
*
Fig. 4 | Calculated dephasing times and indelity. a Computed dephasing times
T?
2of a charge qubit (circle) and of a spin-qubit (star) using S
ϵ,min
from hetero-
structure A (red), B (blue), C (green).Eq. (1) was used to computeT?
2as a functionof
S
ϵ
and αfrom Fig. 3with frequency cutoffs (f
min
,f
max
) = (1.6 mHz, 33 GHz) and
(f
min
,f
max
) = (1.6 mHz,10 kHz). Literature values (squares) are taken from refs. 6,10.
bSimulated indelity of a CZ-gate between two spin qubi ts following the ref. 6using
S
ϵ
and αfromheterostructure A (red), B (blue),C (green) in Fig. 3as inputfor barrier
uctuations.
Article https://doi.org/10.1038/s41467-023-36951-w
Nature Communications |(2023)14:1385 6
Content courtesy of Springer Nature, terms of use apply. Rights reserved
Device fabrication
The fabricationprocess for Hall-bar shaped heterostructure eld effect
transistors (H-FETs) involves: reactive ion etching of mesa-trench to
isolate the two-dimensional electron gas; P-ion implantation and acti-
vationby rapid thermal annealing at 700 °C; atomiclayer deposition of
a 10-nm-thick Al
2
O
3
gate oxide; deposition of thick dielectric pads to
protect gate oxide during subsequent wire bonding step; sputtering of
Al gate; electron beam evaporation of Ti:Pt to create ohmic contacts to
the two-dimensional electron gas via doped areas. All patterning is
done by optical lithography. Double quantum dot devices are fabri-
cated on wafer coupons from the same H-FET fabrication run and share
the process steps listed above. Double-quantum dot devices feature a
single layer gate metallization and further require electron beam
lithography, evaporation of Al (27 nm) or Ti:Pd (3:17 nm) thin lm
metal gate, lift-off, ALD of a 5 nm thick Al
2
O
3
insulating layer, and a
global top-gate.
Electrical characterization of H-FETs
Hall-bar H-FETs measurements are performed in an attoDRY2100
variable temperature insert refrigerator at a base temperature of
1.7 K32. We apply a source-drain bias of 100 μV and measure the source-
drain current I
SD
, the longitudinal voltage V
xx
, and the transverse Hall
voltage V
xy
as function of the top gate voltage V
g
and the external
perpendicular magnetic eld B. From here we calculate the long-
itudinal resistivity ρ
xx
and transverse Hall resistivity ρ
xy
.TheHall
electron density nis obtained from the linear relationship ρ
xy
=B/en at
low magnetic elds. The carrier mobility μis extracted from the rela-
tionship σ
xx
=neμ,whereeis the electron charge. The percolation
density n
p
is extracted by tting the longitudinal conductivity σ
xx
to
the relation σxx nnpÞ1:31 .Hereσ
xx
is obtained via tensor inversion
of ρ
xx
at B= 0. The box plots in Fig. 3a, b for heterostructure A (red) and
B (blue) expand previously published data in Fig. 2f, e of ref. 32 by
considering measurements of 4 additional H-FETs for heterostructure
A (20 H-FETs in total) and of 2 additional H-FETs for heterostructure B
(16 H-FETs in total).
Electrical characterization of quantum dots
Measurements of the multi-electron quantum dots dened in the
charge sensor are performed in a Leiden cryogenic dilution refrig-
erator with a mixing chamber base temperature T
MC
=50mK
40. The
devices are tuned systematically with the following procedure. We
sweep all gate voltages (V
SDRAcc
,V
SDRB
,V
P
,V
SDLB
, and V
SDLAcc
) from 0 V
towards more positive bias, until a source-drain current I
SD
of 1nAis
measured, indicating that a conductive channel has formed in the
device. We then reduce the barrier voltages to nd the pinch-off
voltages for each barrier. Subsequently, we measure I
SD
as a function
of V
SDLB
and V
SDRB
and from this 2D map we nd a set of gate voltage
parameters so that Coulomb blockade peaks are visible. We then x
the barrier voltages and sweep V
P
to count how many clearly dened
Coulomb peaks are observed before onset of a background current.
The quantum dot is tuned to show at least 9 Coulomb peaks, so that
noise spectra may be tted as in Fig. 2d with meaningful error bars. If
we see less than 9 Coulomb peaks we readjust the accumulation gate
voltages V
SDRAcc
, and V
SDLAcc
, and repeat the 2D scan of V
SDLB
against
V
SDRB
. In one case (device 2 of heterostructure A), we tuned device to
show past 5 Coulomb peaks and still performed the t of the charge
noise spectra similar to the one shown in Fig. 2d. Further details on
the extraction of the lever arms and operation gate voltages of the
devices are provided in Supplementary Figs 4 and 5. We estimate an
electron temperature of 190 mK by tting Coulomb blockade peaks
(see Supplementary Fig. 2 in ref. 32) measured on quantum dot
devices.
For heterostructure A we apply a source drain bias of 100 μV(1
device) or 150 μV (3 devices) across the quantum dot, nite gate vol-
tages across the operation gates of the dot, and nite gate voltages
across the screening gates. We measure the currentI
SD
and the current
noise spectrum S
I
ontheleftsideoftheCoulombpeakwheredI/dV
P
is
largest. We use a sampling rate of 1 kHz for 1 min using a Keithley
DMM6500 multimeter. The spectraare then divided into 10 segments
of equal length and we use a Fourier transform to convert from time-
domain to frequency-domain for a frequency range of
167 mHz500Hz. We set the upper limit of the frequency spectra at
10 Hz, to avoid inuences from a broad peak at around 150 Hz coming
from the setup (Supplementary Fig. 3). A peak in the power spectral
density at 9 Hz is removed from the analysis since it is an artifact of the
pre-amplier. To convert the current noise spectrum to a charge noise
spectrum, we use the formula20
Sϵ=a2SI
dI=dVP2ð3Þ
where ais the lever arm and dI/dV
P
is the slope of the Coulomb peak
at the plunger voltage used to acquire the time trace.
The charge noise measurements conditions have been slightly
modied from sample A to sample B, C to extend the probed fre-
quency range from 100 μHz to 10 μHz. For heterostructures B and C
we apply a source drain bias of 150 μV across the quantum dot, nite
gate voltages across the operation gates of the quantum dot, and we
apply 0 V to all other gates. We measure the current I
SD
and the current
noise spectrum S
I
ontheleftsideoftheCoulombpeakwheredI/dV
P
is
largest. We use a sampling rate of 1 kHz for 10 min using a Keithley
DMM6500 multimeter. The spectra are then divided into 15 segments
of equal length and we use a Fourier transform to convert from time-
domain to frequency-domain for a frequency range of 25 mHz500 Hz.
We set the upper limit of the frequency spectra at 10 Hz, to avoid
inuences from a broad peak at around 150 Hz coming from the setup.
We use Eq. (3) to convert the current noise spectrum to a charge noise
spectrum.
(Scanning) Transmission Electron Microscopy
For structural characterization with (S)TEM, we prepared cross-
sections of the quantum well heterostructures by using a Focused
Ion Beam (Helios 600 dual beam microscope). Atomically resolved
HAADF STEM data was acquired in a probe corrected TITAN micro-
scope operated at 300kV. Quantitative EELS was carried out in a
TECNAI F20 microscope operated at 200 kV with approximately 2 eV
energy resolution and 1 eV energy dispersion. Principal Component
Analysis (PCA) was applied to the spectrum images to enhance
S/N ratio.
Data availability
All data included in this work are available from the 4TU.ResearchData
international data repository at https://doi.org/10.4121/20418579.
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Acknowledgements
We acknowledge helpful discussions with G. Isella, D. Paul, M. Meh-
mandoost, the Scappucci group and the Vandersypen group. This
research was supported by the European Unions Horizon 2020
research and innovation programme under the Grant Agreement No.
951852 (QLSI project) and in part by the Army Research Ofce (Grant
No. W911NF-17-1-0274). The views and conclusions contained in this
Article https://doi.org/10.1038/s41467-023-36951-w
Nature Communications |(2023)14:1385 8
Content courtesy of Springer Nature, terms of use apply. Rights reserved
document are those of the authors and should not be interpreted as
representing the ofcial policies, either expressed or implied, of the
Army Research Ofce (ARO), or the U.S. Government. The U.S. Gov-
ernment is authorized to reproduce and distribute reprints for Gov-
ernment purposes notwithstanding any copyright notation herein.
M.R. acknowledges support from the Netherlands Organization of
Scientic Research (NWO) under Veni grant VI.Veni.212.223. ICN2
acknowledges funding from Generalitat de Catalunya
2021SGR00457. ICN2 is supported by the Severo Ochoa program
from Spanish MCIN / AEI (Grant No.: CEX2021-001214-S) and is funded
by the CERCA Programme / Generalitat de Catalunya and ERDF funds
from EU. Part of the present work has been performed in the frame-
work of Universitat Autònoma de Barcelona Materials Science PhD
program. Authors acknowledge the use of instrumentation as well as
the technical advice provided by the National Facility ELECMI ICTS,
node Laboratorio de Microscopias Avanzadas" at University of Zar-
agoza. M.B. acknowledges support from SUR Generalitat de Catalunya
and the EU Social Fund; project ref. 2020 FI 00103. We acknowledge
support from CSIC Interdisciplinary Thematic Platform (PTI+) on
Quantum Technologies (PTI-QTEP+).
Author contributions
A.S. grew and designed the 28Si/SiGe heterostructures with B.P.W. and
G.S.. M.R. developed the theory. A.S. and D.D.E. fabricated hetero-
structure eld effect transistors measured by B.P.W. and D.D.E.. M.B and
J.A. performed TEM characterization. S.A and D.D.E. fabricated quantum
dot devices. B.P.W. and D.D.E. measured the quantum dot devices with
contributions from A.M.J.Z.. G.S. conceived and supervised the project.
B.P.W, D.D.E, M.R, and G.S. wrote the manuscript with input from all
authors.
Competing interests
The authors declare no competing interests.
Additional information
Supplementary information The online version contains
supplementary material available at
https://doi.org/10.1038/s41467-023-36951-w.
Correspondence and requests for materials should be addressed to
Giordano Scappucci.
Peer review information Nature Communications thanks Yujia Liu and
the other anonymous reviewer(s) for their contribution to the peer
review of this work. Peer reviewer reports are available.
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... This approach can also be regarded as leveraging the screening effect of additional electrons in the device. A recent experimental study indirectly exhibits the screening effect by adding electrons to a charge sensor close to a QD [27]. Other studies show that the coherence of a spin qubit can be enhanced when the qubit is defined with multiple electrons in a QD [28,29]. ...
... For a 10 nm Si QW, which is a typical width for realistic devices, the PSD for the electric potential is decreased by about two orders of magnitude. If we make thin Si QW and SiGe layers of 5 nm thickness each [27], the PSD can be reduced by about three orders of magnitude. The reduction in the PSD for the spin qubit frequency is less than that for the electric potential, which is about two orders of magnitude for d = 5 nm. ...
... The dephasing times for no screening, screening at z = −15 nm, z = −10 nm, and z = −5 nm are 2.1, 7.5, 11.7, and 25.2 µs, respectively. This enhancement can be understood from the relation T * 2 ∼ 1/ S(ω)dω in the quasistatic limit [27]. The simulation parameters and details are given in the Supplemental Material. ...
Preprint
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Semiconductor spin qubits are an attractive platform for quantum computing, but their performance is degraded primarily by fluctuating electromagnetic environments. We introduce the concept of ballast charges, which are induced charges on the surface of an additional screening layer situated below the qubits. The counteractive behavior of these charges can significantly reduce the power spectral density associated with fluctuations from two-level systems that contribute to charge noise. Our simulations show that the dephasing time of a spin qubit in a Si/SiGe device increases by a factor of 4 to 6 on average when using this method. We also discuss the physical implementation and potential challenges of this approach.
... In conventional Si/SiGe heterostructures, a strained Si quantum well is separated from the semiconductor-dielectric interface by an epitaxial SiGe barrier 3 . The buried Si quantum well naturally ensures a quiet environment, away from the impurities at the semiconductor-dielectric interface, leading to lower disorder and charge noise compared to Si-MOS [16][17][18] . However, strain and compositional fluctuations in the SiGe strain-relaxed buffer (SRB) below the quantum well result in band-structure variations and device non-uniformity 19 . ...
... Our growth protocol yields a reproducible quantum well profile with ρ b = 0.31(1) 30,45 , 4τ ≈ 1 nm, and w ≈ 7 nm (see Supplementary Figs. 1 and 2). The quantum well thickness was chosen on purpose to fall within the range of 5-9 nm, which correspond to the thicknesses of quantum wells studied in ref. 18 and used here as a benchmark. We expect a quantum well of about 7 nm to be thin enough to suppress strain-release defects and also increase the valley splitting compared to the results in refs. ...
... At the same time, the quantum well was chosen to be sufficiently thick to mitigate the effect of disorder arising from penetration of the wave function into the SiGe barrier 42 and possibly from the interface roughness 43 . Figure 1d shows aberration corrected (AC) atomic resolution highangle annular dark field (HAADF) scanning transmission electron microscopy (STEM) images and superimposed intensity profiles to validate the thickness of the 28 Si quantum well by counting the (002) horizontal planes as in ref. 18. We estimate that the quantum well is formed by 26 atomic planes, corresponding to a thickness w = 6.9 ± 0.5 nm (see Supplementary Fig. 1). ...
Article
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The electrical characterisation of classical and quantum devices is a critical step in the development cycle of heterogeneous material stacks for semiconductor spin qubits. In the case of silicon, properties such as disorder and energy separation of conduction band valleys are commonly investigated individually upon modifications in selected parameters of the material stack. However, this reductionist approach fails to consider the interdependence between different structural and electronic properties at the danger of optimising one metric at the expense of the others. Here, we achieve a significant improvement in both disorder and valley splitting by taking a co-design approach to the material stack. We demonstrate isotopically purified, strained quantum wells with high mobility of 3.14(8) × 10 ⁵ cm ² V ⁻¹ s ⁻¹ and low percolation density of 6.9(1) × 10 ¹⁰ cm ⁻² . These low disorder quantum wells support quantum dots with low charge noise of 0.9(3) μeV Hz −1/2 and large mean valley splitting energy of 0.24(7) meV, measured in qubit devices. By striking the delicate balance between disorder, charge noise, and valley splitting, these findings provide a benchmark for silicon as a host semiconductor for quantum dot qubits. We foresee the application of these heterostructures in larger, high-performance quantum processors.
... While ongoing improvements in material growth and device fabrication [5,9,16] allow for the mitigation of decoherence, charge noise cannot be completely eliminated, even in the best-quality devices [7,17,18]. Given the many effects that contribute to noise and the heavily device-dependent noise spectra [19], quantum optimal control is necessary to achieve deterministic high-fidelity control with potential for scalability. ...
... Case of α > 1.-In the main text, we established the self-adjoint operator form [Eq. (16)] of auto-correlation function R(τ 1 , τ 2 ) from Eq. (13). Together with the normalization condition (1, S) = 1, it yields a positivedefinite Lagrangian: ...
Preprint
Low-frequency $1/f^\alpha$ charge noise significantly hinders the performance of voltage-controlled spin qubits in quantum dots. Here, we utilize fractional calculus to design voltage control pulses yielding the highest average fidelities for noisy quantum gate operations. We focus specifically on the exponential voltage control of the exchange interaction generating two-spin $\mathrm{SWAP}^k$ gates. When stationary charge noise is the dominant source of gate infidelity, we derive that the optimal exchange pulse is long and weak, with the broad shape of the symmetric beta distribution function with parameter $1-\alpha/2$. The common practice of making exchange pulses fast and high-amplitude still remains beneficial in the case of strongly nonstationary noise dynamics, modeled as fractional Brownian motion. The proposed methods are applicable to the characterization and optimization of quantum gate operations in various voltage-controlled qubit architectures.
... It is well established that the low-frequency noise in interdot energy detuning (i.e., the difference of orbital ground state energies in the two dots, which is controlled by voltages on plunger gates nearby each dot) has power spectral density of 1/ f β form, see Ref. [75] and references therein. As J ∝ e / 0 in GaAs DQDs [57] (and in many other DQD systems, see Table I in Ref. [76]), the spectrum of fluctuations of J has the same 1/ f β -type shape. ...
Article
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We analyze in detail a procedure of entangling of two singlet–triplet (S–T0\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$T_{0}$$\end{document}) qubits operated in a regime when energy associated with the magnetic field gradient, ΔBz\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\Delta B_{z}$$\end{document}, is an order of magnitude smaller than the exchange energy, J, between singlet and triplet states (Shulman et al. in Science 336:202, 2012). We have studied theoretically a single S–T0\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$T_{0}$$\end{document} qubit in free induction decay and spin echo experiments. We have obtained analytical expressions for the time dependence of components of its Bloch vector for quasistatic fluctuations of ΔBz\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\Delta B_{z}$$\end{document} and quasistatic or dynamical 1/fβ\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$1/f^{\beta }$$\end{document}-type fluctuations of J. We have then considered the impact of fluctuations of these parameters on the efficiency of the entangling procedure which uses an Ising-type coupling between two S–T0\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$T_{0}$$\end{document} qubits. In particular, we have obtained an analytical expression for evolution of two qubits affected by 1/fβ\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$1/f^{\beta }$$\end{document}-type fluctuations of J. This expression indicates the maximal level of entanglement that can be generated by performing the entangling procedure. Our results deliver also an evidence that in the above-mentioned experiment S–T0\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$T_{0}$$\end{document} qubits were affected by uncorrelated 1/fβ\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$1/f^{\beta }$$\end{document} charge noises.
... Because of its similarities to a quantum dot charge qubit, we expect the limiting decoherence mechanism to be the same-charge noise [47]. Typical coherence times are of the order of a few nanoseconds [28,[47][48][49]. In comparison, Dvir et al. [23] report CAR/ECT strengths that set a lower bound for gate pulse durations of ħ h/Γ CAR/ECT ≈ 50 ps. ...
Article
Full-text available
We propose a practical implementation of a universal quantum computer that uses local fermionic modes (LFM) rather than qubits. The device consists of quantum dots tunnel-coupled by a hybrid superconducting island and a tunable capacitive coupling between the dots. We show that coherent control of Cooper pair splitting, elastic cotunneling, and Coulomb interactions implements the universal set of quantum gates defined by Bravyi and Kitaev [Ann. Phys. 298, 210 (2002)]. Due to the similarity with charge qubits, we expect charge noise to be the main source of decoherence. For this reason, we also consider an alternative design where the quantum dots have tunable coupling to the superconductor. In this second device design, we show that there is a sweet spot for which the local fermionic modes are charge neutral, making the device insensitive to charge noise effects. Finally, we compare both designs and their experimental limitations and suggest future efforts to overcome them.
... T * 2,GaAs ≈ 2µs, at the cost of continuous estimation of the nuclear field [40]. We compare such a case against isotopically purified Si (with 800 ppm), with an order of magnitude longer T * 2,Si = 20µs [41]. To model experimental scenario we assume the detuning and tunnel coupling are affected by the charge noise of 1/f-type with a value of spectral density at f = 1Hz, i.e. ...
Preprint
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Electron shuttling is one of the currently pursued avenues towards the scalability of semiconductor quantum dot-based spin qubits. We theoretically analyze the dephasing of a spin qubit adiabatically transferred between two tunnel-coupled quantum dots. We focus on the regime where the Zeeman splitting is lower than the tunnel coupling, at which interdot tunneling with spin flip is absent, and analyze the sources of errors in spin-coherent electron transfer for Si- and GaAs-based quantum dots. Apart from the obvious effect of fluctuations in spin splitting in each dot (e.g., due to nuclear Overhauser fields) leading to finite $ T_{2}^{*} $ of the stationary spin qubit, we consider effects activated by detuning sweeps aimed at adiabatic qubit transfer between the dots: failure of charge transfer caused by charge noise and phonons, spin relaxation due to enhancement of spin-orbit mixing of levels, and spin dephasing caused by low- and high-frequency noise coupling to the electron's charge in the presence of differences in Zeeman splittings between the two dots. Our results indicate that achieving coherent transfer of electron spin in a $10\,\mu$m long dot array necessitates a large and uniform tunnel coupling, with a typical value of $ 2t_c \gtrsim 60 \, \mu$eV.
... The filter functions for both the robust and non-robust neural network designed iToffoli gates, F i , are plotted in figure 4. Using the same estimates of A 0 = 1 µV, ω cutoff = 100 MHz [42] and ω ir ≈ 10 −3 Hz for both voltages results in an estimated infidelity as a result of frequency-dependent charge noise of 1.6 × 10 −2 for the robust iToffoli, compared to 9.4 × 10 −2 for the non-robust iToffoli. The robust iToffoli infidelity is almost an order of magnitude lower and this ratio would also be maintained for devices designed to have smaller charge noise strengths [44]. ...
Article
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Spin qubits in semiconductor quantum dots are a promising platform for quantum computing, however, scaling to large systems is hampered by crosstalk and charge noise. Crosstalk here refers to the unwanted off-resonant rotation of idle qubits during the resonant rotation of the target qubit. For a three-qubit system with crosstalk and charge noise, it is difficult to analytically create gate protocols that produce three-qubit gates, such as the Toffoli gate, directly in a single shot instead of through the composition of two-qubit gates. Therefore, we numerically optimize a physics-informed neural network to produce theoretically robust shaped pulses that generate a Toffoli-equivalent gate. Additionally, robust π2 X and Controlled-Z gates are also presented in this work to create a universal set of gates robust against charge noise. The robust pulses maintain an infidelity of 10⁻³ for average quasistatic fluctuations in the voltage of up to a few mV instead of tenths of mV for non-robust pulses.
Article
Si/SiGe heterostructures are of high interest for high-mobility transistor and qubit applications, specifically for operations below 4.2K. In order to optimize parameters such as charge mobility, built-in strain, electrostatic disorder, charge noise, and valley splitting, these heterostructures require Ge concentration profiles close to monolayer precision. Ohmic contacts to undoped heterostructures are usually facilitated by a global annealing step activating implanted dopants, but compromising the carefully engineered layer stack due to atom diffusion and strain relaxation in the active device region. We demonstrate a local laser-based annealing process for recrystallization of ion-implanted contacts in SiGe, greatly reducing the thermal load on the active device area. To quickly adapt this process to the constantly evolving heterostructures, we deploy a calibration procedure based exclusively on optical inspection at room temperature. We measure the electron mobility and contact resistance of laser-annealed Hall bars at temperatures below 4.2K and obtain values similar or superior to that of a globally annealed reference sample. This highlights the usefulness of laser-based annealing to take full advantage of high-performance Si/SiGe heterostructures.
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We theoretically propose a method to perform in situ measurements of charge noise during logical operations in silicon quantum dot spin qubits. Our method does not require ancillary spectator qubits but makes use of the valley degree of freedom in silicon. Sharp interface steps or alloy disorder in the well provide a valley transition dipole element that couples to the field of an on-chip microwave resonator, allowing rapid reflectometry of valley splitting fluctuations caused by charge noise. We derive analytic expressions for the signal-to-noise ratio that can be expected and use tight binding simulations to extract the key parameters (valley splitting and valley dipole elements) under realistic disorder. We find that unity signal-to-noise ratio can often be obtained with measurement times below 1ms, faster than typical decoherence times, opening the potential for closed-loop control, real-time recalibration, and feedforward circuits.
Article
We analyze the dynamics of two-qubit entangled Bell states in coupled quantum dots (QDs) in the presence of both fluctuations and coherent electron hopping between the dots. The explicit expression for time-dependent probability to find the system in the different Bell states was obtained for various initial conditions by means of Keldysh diagram technique. It was revealed that time evolution of one pair of Bell states and its decay rate strongly differs from another one. It was demonstrated that one pair of Bell states is more robust against fluctuations than another one. The stationary occupation of Bell states for different initial conditions was also analyzed. Obtained results are important for the problems where long-living Bell states are needed such as the security of quantum communication and quantum information processing.
Article
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Electron spins in Si/SiGe quantum wells suffer from nearly degenerate conduction band valleys, which compete with the spin degree of freedom in the formation of qubits. Despite attempts to enhance the valley energy splitting deterministically, by engineering a sharp interface, valley splitting fluctuations remain a serious problem for qubit uniformity, needed to scale up to large quantum processors. Here, we elucidate and statistically predict the valley splitting by the holistic integration of 3D atomic-level properties, theory and transport. We find that the concentration fluctuations of Si and Ge atoms within the 3D landscape of Si/SiGe interfaces can explain the observed large spread of valley splitting from measurements on many quantum dot devices. Against the prevailing belief, we propose to boost these random alloy composition fluctuations by incorporating Ge atoms in the Si quantum well to statistically enhance valley splitting. Spin qubits in Si/SiGe quantum dots suffer from variability in the valley splitting which will hinder device scalability. Here, by using 3D atomic characterization, the authors explain this variability by random Si and Ge atomic fluctuations and propose a strategy to statistically enhance the valley splitting
Article
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Control of entanglement between qubits at distant quantum processors using a two-qubit gate is an essential function of a scalable, modular implementation of quantum computation. Among the many qubit platforms, spin qubits in silicon quantum dots are promising for large-scale integration along with their nanofabrication capability. However, linking distant silicon quantum processors is challenging as two-qubit gates in spin qubits typically utilize short-range exchange coupling, which is only effective between nearest-neighbor quantum dots. Here we demonstrate a two-qubit gate between spin qubits via coherent spin shuttling, a key technology for linking distant silicon quantum processors. Coherent shuttling of a spin qubit enables efficient switching of the exchange coupling with an on/off ratio exceeding 1000, while preserving the spin coherence by 99.6% for the single shuttling between neighboring dots. With this shuttling-mode exchange control, we demonstrate a two-qubit controlled-phase gate with a fidelity of 93%, assessed via randomized benchmarking. Combination of our technique and a phase coherent shuttling of a qubit across a large quantum dot array will provide feasible path toward a quantum link between distant silicon quantum processors, a key requirement for large-scale quantum computation.
Article
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Future quantum computers capable of solving relevant problems will require a large number of qubits that can be operated reliably¹. However, the requirements of having a large qubit count and operating with high fidelity are typically conflicting. Spins in semiconductor quantum dots show long-term promise2,3 but demonstrations so far use between one and four qubits and typically optimize the fidelity of either single- or two-qubit operations, or initialization and readout4–11. Here, we increase the number of qubits and simultaneously achieve respectable fidelities for universal operation, state preparation and measurement. We design, fabricate and operate a six-qubit processor with a focus on careful Hamiltonian engineering, on a high level of abstraction to program the quantum circuits, and on efficient background calibration, all of which are essential to achieve high fidelities on this extended system. State preparation combines initialization by measurement and real-time feedback with quantum-non-demolition measurements. These advances will enable testing of increasingly meaningful quantum protocols and constitute a major stepping stone towards large-scale quantum computers.
Article
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We study the critical thickness for the plastic relaxation of the Si quantum well layer embedded in a SiGe/Si/SiGe heterostructure for qubits by plan-view transmission electron microscopy and electron channeling contrast imaging. Misfit dislocation segments form due to the glide of pre-existing threading dislocations at the interface of the Si quantum well layer beyond a critical thickness given by the Matthews–Blakeslee criterion. Misfit dislocations are mostly [Formula: see text] dislocations (b=a/2 <110>) that are split into Shockely partials (b=a/6 <112>) due to the tensile strain field of the Si quantum well layer. By reducing the quantum well thickness below critical thickness, misfit dislocations can be suppressed. A simple model is applied to simulate the misfit dislocation formation and the blocking process. We discuss consequences of our findings for the layer stack design of SiGe/Si/SiGe heterostructures for usage in quantum computing hardware.
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We report the coherent coupling of two electron spins at a distance via virtual microwave photons. Each spin is trapped in a silicon double quantum dot at either end of a superconducting resonator, achieving spin-photon couplings up to around g_{s}/2π=40 MHz. As the two spins are brought into resonance with each other, but detuned from the photons, an avoided crossing larger than the spin linewidths is observed with an exchange splitting around 2J/2π=20 MHz. In addition, photon-number states are resolved from the shift 2χ_{s}/2π=-13 MHz that they induce on the spin frequency. These observations demonstrate that we reach the strong dispersive regime of circuit quantum electrodynamics with spins. Achieving spin-spin coupling without real photons is essential to long-range two-qubit gates between spin qubits and scalable networks of spin qubits on a chip.
Article
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Silicon spin qubits satisfy the necessary criteria for quantum information processing. However, a demonstration of high-fidelity state preparation and readout combined with high-fidelity single- and two-qubit gates, all of which must be present for quantum error correction, has been lacking. We use a two-qubit Si/SiGe quantum processor to demonstrate state preparation and readout with fidelity greater than 97%, combined with both single- and two-qubit control fidelities exceeding 99%. The operation of the quantum processor is quantitatively characterized using gate set tomography and randomized benchmarking. Our results highlight the potential of silicon spin qubits to become a dominant technology in the development of intermediate-scale quantum processors.
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Full-scale quantum computers require the integration of millions of qubits, and the potential of using industrial semiconductor manufacturing to meet this need has driven the development of quantum computing in silicon quantum dots. However, fabrication has so far relied on electron-beam lithography and, with a few exceptions, conventional lift-off processes that suffer from low yield and poor uniformity. Here we report quantum dots that are hosted at a ²⁸ Si/ ²⁸ SiO 2 interface and fabricated in a 300 mm semiconductor manufacturing facility using all-optical lithography and fully industrial processing. With this approach, we achieve nanoscale gate patterns with excellent yield. In the multi-electron regime, the quantum dots allow good tunnel barrier control—a crucial feature for fault-tolerant two-qubit gates. Single-spin qubit operation using magnetic resonance in the few-electron regime reveals relaxation times of over 1 s at 1 T and coherence times of over 3 ms.
Article
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Electron spins in silicon quantum dots are promising qubits due to their long coherence times, scalable fabrication, and potential for all-electrical control. However, charge noise in the host semiconductor presents a major obstacle to achieving high-fidelity single- and two-qubit gates in these devices. In this work, we measure the charge-noise spectrum of a Si/SiGe singlet-triplet qubit over nearly 12 decades in frequency using a combination of methods, including dynamically-decoupled exchange oscillations with up to 512 π pulses during the qubit evolution. The charge noise is colored across the entire frequency range of our measurements, although the spectral exponent changes with frequency. Moreover, the charge-noise spectrum inferred from conductance measurements of a proximal sensor quantum dot agrees with that inferred from coherent oscillations of the singlet-triplet qubit, suggesting that simple transport measurements can accurately characterize the charge noise over a wide frequency range in Si/SiGe quantum dots.
Article
This Technical Review collects values of selected performance characteristics of semiconductor spin qubits defined in electrically controlled nanostructures. The characteristics are envisaged to serve as a community source for the values of figures of merit with agreed definitions allowing the comparison of different spin-qubit platforms. We include characteristics on the qubit coherence, speed, fidelity and qubit size of multi-qubit devices. The focus is on collecting and curating the values of these characteristics as reported in the literature, rather than on their motivation or significance. Spin qubits hosted in semiconducting nanostructures controlled and probed electrically are among platforms pursued to serve as quantum computing hardware. This Technical Review surveys experimentally achieved values on coherence, speed, fidelity and multi-qubit array size, reflecting the progress of semiconducting spin qubits over the past two decades. Spin qubits hosted in semiconducting nanostructures controlled and probed electrically are among platforms pursued to serve as quantum computing hardware.Their prospect for scalability stems from their versatility and compatibility with modern silicon industrial fabrication.To serve as quantum hardware, qubits have to fulfil a number of stringent criteria concerning their operation, stability and interactions.The overview of experimentally achieved values on coherence, speed, fidelity and multi-qubit array size quantifies the progress of semiconducting spin qubits over the past two decades. Spin qubits hosted in semiconducting nanostructures controlled and probed electrically are among platforms pursued to serve as quantum computing hardware. Their prospect for scalability stems from their versatility and compatibility with modern silicon industrial fabrication. To serve as quantum hardware, qubits have to fulfil a number of stringent criteria concerning their operation, stability and interactions. The overview of experimentally achieved values on coherence, speed, fidelity and multi-qubit array size quantifies the progress of semiconducting spin qubits over the past two decades.
Article
We grow ²⁸ Si/SiGe heterostructures by reduced-pressure chemical vapor deposition and terminate the stack without an epitaxial Si cap but with an amorphous Si-rich layer obtained by exposing the SiGe barrier to dichlorosilane at 500 °C. As a result, ²⁸ Si/SiGe heterostructure field-effect transistors feature a sharp semiconductor/dielectric interface and support a two-dimensional electron gas with enhanced and more uniform transport properties across a 100 mm wafer. At T = 1.7 K, we measure a high mean mobility of [Formula: see text] cm ² /V s and a low mean percolation density of [Formula: see text] cm ⁻² . From the analysis of Shubnikov–de Haas oscillations at T = 190 mK, we obtain a long mean single particle relaxation time of [Formula: see text] ps, corresponding to a mean quantum mobility and quantum level broadening of [Formula: see text] cm ² /V s and [Formula: see text] [Formula: see text], respectively, and a small mean Dingle ratio of [Formula: see text], indicating reduced scattering from long range impurities and a low-disorder environment for hosting high-performance spin-qubits.