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Aligned Carbon Nanotube Arrays with Germanium Protective Layers for Improving the Performance of Radio Frequency Transistors
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Aligned carbon nanotube (A‐CNT) films are expected to be an ideal channel material for constructing field‐effect transistors (FETs) that outperform conventional transistors, and multiple methods are developed to fabricate A‐CNT films with high semiconducting purity, good alignment, and high density. However, the reported A‐CNTs‐based FETs are almost all depletion‐mode FETs and suffer from poor subthreshold swing (SS). In this study, enhancement‐mode (E‐mode) FETs based on A‐CNT films are fabricated by systematically optimizing the channel material and CNT/high‐k/metal gate stack. The carrier mobility in top‐gate A‐CNT FETs reaches a maximum value of 1850 cm2 V−1 s−1, which is near that of chemical‐vapor deposition grown individual CNTs and sets a record among A‐CNT films. The fabricated 200 nm‐gate length p‐type A‐CNT FETs present a SS of 73 mV dec−1, the transconductance of 1 mS µm−1, and an on‐current of 1.18 mA µm−1 at a bias of ‐1 V, indicating a real performance exceeding that of commercial Si‐based transistors at a similar gate length. Based on the high‐performance and uniform E‐mode FETs, ring oscillators with stage numbers 5, 7, 9, and 11 are fabricated with an optimized design and high yield, exhibiting a record propagation gate delay of 11.3 ps among CNT‐ and other nanomaterial‐based ICs. Although field‐effect transistors (FETs) based on aligned carbon nanotube (A‐CNT) films are demonstrated, the depletion‐mode and poor subthreshold swing bring difficulty in constructing integrated circuits. The gate stack is systematically optimized and enhancement‐mode p‐type A‐CNT FETs are fabricated. The FETs present a real performance exceeding that of commercial Si‐based transistors at a similar gate length.
The development of next-generation wireless communication technology requires integrated radiofrequency devices capable of operating at frequencies greater than 90 GHz. Carbon nanotube field-effect transistors are promising for such applications, but key performance metrics, including operating frequency, at present fall below theoretical predictions. Here we report radiofrequency transistors based on high-purity carbon nanotube arrays that are fabricated using a double-dispersion sorting and binary liquid interface aligning process. The nanotube arrays exhibit a density of approximately 120 nanotubes per micrometre, a maximum carrier mobility of 1,580 cm² V⁻¹ s⁻¹ and a saturation velocity of up to 3.0 × 10⁷ cm s⁻¹. The resulting field-effect transistors offer high d.c. performance (on-state current of 1.92 mA µm⁻¹ and peak transconductance of 1.40 mS μm⁻¹ at a bias of −0.9 V) for operation at millimetre-wave and terahertz frequencies. Transistors with a 50 nm gate length show current-gain and power-gain cutoff frequencies of up to 540 and 306 GHz, respectively, and radiofrequency amplifiers can exhibit a high power gain (23.2 dB) and inherent linearity (31.2 dBm output power of the third-order intercept point) in the K-band (18 GHz).
Aligning dense carbon nanotube arrays
Although semiconducting carbon nanotubes (CNTs) are promising candidates to replace silicon in transistors at extremely small dimensions, their purity, density, and alignment must be improved. Liu et al. combined a multiple dispersion sorting process, which improves purity, and a dimension-limited self-alignment process to produce well-aligned CNT arrays on a 10-centimeter silicon wafer. The density is sufficiently high (100 to 200 CNTs per micrometer) that large-scale integrated circuits could be fabricated. With ionic liquid gating, the performance metrics exceeded those of conventional silicon transistors with similar dimensions.
Science , this issue p. 850
Wireless device technology operating in the millimetre-wave regime (30 to 300 GHz) increasingly needs to offer both high performance and a high level of integration with complementary metal–oxide–semiconductor (CMOS) technology. Aligned carbon nanotubes are proposed as an alternative to III–V technologies in such applications because of their highly linear signal amplification and compatibility with CMOS. Here we report the wafer-scalable fabrication of aligned carbon nanotube field-effect transistors operating at gigahertz frequencies. The devices have gate lengths of 110 nm and are capable, in distinct devices, of an extrinsic cutoff frequency and maximum frequency of oscillation of over 100 GHz, which surpasses the 90 GHz cutoff frequency of radio-frequency CMOS devices with gate lengths of 100 nm and is close to the performance of GaAs technology. Our devices also offer good linearity, with distinct devices capable of a peak output third-order intercept point of 26.5 dB when normalized to the 1 dB compression power, and 10.4 dB when normalized to d.c. power. Radio-frequency transistors made from aligned carbon nanotubes offer high linearity and an extrinsic cutoff frequency of over 100 GHz.
The interface of the two-dimensional material plays a crucial role in the properties of the material itself. When 2D materials are used as channel for electrical devices, negative influence from surface contaminations during fabrication process should be avoided to ensure the device performance and the reliability. In this article, the impacts as well as its mechanisms of interface contaminations on MoS2 field effect transistors were studied. An effective method using an atomic layer deposition (ALD) grown Al2O3 dielectric layer to reduce exposure time of MoS2 during processing was introduced. Combine with annealing process, the fabricated MoS2 FETs with a Al2O3 protective layer demonstrate a high On/Off current ratio of 5Χ107, and a hysteresis of 80 mV in terms of decent reliability. Sulfur repair mechanism on MoS2/Al2O3 interface during annealing is revealed to explained the enhancement of devices performance. This method can also be adopted in other 2D materials, paving a path for the next generation flexible electronics application.
High-performance logic circuits that are constructed on flexible or unconventional substrates are required for emerging applications such as real-time analytics. Carbon nanotube thin-film transistors (TFTs) are attractive for these applications because of their high mobility and low cost. However, flexible nanotube TFTs usually suffer from much lower performance than those built on rigid substrates, and the resulting flexible integrated circuits typically exhibit low-speed operation with logic gate delays of over 1 μs, which severely limits their practical application. Here we show that high-performance carbon nanotube TFTs and complementary circuits can be fabricated on flexible polyimide substrates using a high-yield, scalable process. Our flexible TFTs exhibit state-of-the-art performance with very high current densities (>17 μA μm−1), large current on/off ratios (>106), small subthreshold slopes (<200 mV dec−1), high field-effect mobilities (~50 cm2 V−1 s−1) and excellent flexibility. We also develop a reliable n-type doping process, which allows us to fabricate complementary logic gates and integrated circuits on flexible substrates. With our approach, we build flexible ring oscillators that have a stage delay of only 5.7 ns. High-performance carbon nanotube thin-film transistors and complementary circuits can be fabricated on flexible substrates, including ring oscillators that have a stage delay of only 5.7 ns.
Cooler electrons for transistors
The operating power of field-effect transistors is constrained in part by the minimum change in voltage needed to change the current output. This subthreshold swing (SS) limit is caused by hotter electrons from a thermal electron source leaking over the potential of the gate electrode. Qiu et al. show that graphene can act as a Dirac source that creates a narrower distribution of electron energies. When coupled to a carbon nanotube channel, the decrease in SS would allow the supply voltage to be decreased from 0.7 to 0.5 volts.
Science , this issue p. 387
We demonstrate the use of germanium (Ge) films as water-soluble features that allow the patterning of proteins onto surfaces with commonly used organic solvents. This technique is scalable for manufacturing and is compatible with nano- and microfabrication processes, including standard lithography. We use Ge as a sacrificial layer to mask and protect areas of the substrate during surface functionalization. Since Ge dissolves in 0.35% hydrogen peroxide (H2O2) in water but not in organic solvents, Ge can be removed after patterning without significantly affecting protein activities. In this paper, we present examples of protein patterning with two different techniques. We show that 50 nm thick Ge layers can be completely removed in 10 min without residues and, importantly, nanoscale resolution and misalignment can be achieved with conventional photolithography equipment. Both biotin and streptavidin maintain ~80% and >50% activity after 10 min and 360 min incubation in 0.35% H2O2, respectively. Lastly, the process can be used to functionalize sidewalls with proteins, a capability of recent interest for cell-cell adhesion studies.
As conventional monolithic silicon technology struggles to meet the requirements for the 7-nm technology node, there has been tremendous progress in demonstrating the scalability of carbon nanotube field-effect transistors down to the size that satisfies the 3-nm node and beyond. However, to date, circuits built with carbon nanotubes have overlooked key aspects of a practical logic technology and have stalled at simple functionality demonstrations. Here, we report high-performance complementary carbon nanotube ring oscillators using fully manufacturable processes, with a stage switching frequency of 2.82 GHz. The circuit was built on solution-processed, self-assembled carbon nanotube arrays with over 99.9% semiconducting purity, and the complementary feature was achieved by employing two different work function electrodes.
Carbon nanotube (CNT) is considered as a promising material for radio frequency (RF) applications owing to its high carrier mobility and saturated drift velocity, as well as ultra-small intrinsic gate capacitance. Here we review the progress on CNT-based devices and integrated circuits for RF applications, including theoretical projection of RF performance of CNT-based devices, preparation of CNT materials, fabrication, optimization of RF field-effect transistors (FETs) structures, ambipolar FET based RF applications, and outline the challenges and prospective of CNT-based RF applications.
Carbon nanotubes (CNTs) are tantalizing candidates for semiconductor electronics because of their exceptional charge transport properties and one-dimensional electrostatics. Ballistic transport approaching the quantum conductance limit of 2G0 = 4e²/h has been achieved in field-effect transistors (FETs) containing one CNT. However, constraints in CNT sorting, processing, alignment, and contacts give rise to nonidealities when CNTs are implemented in densely packed parallel arrays such as those needed for technology, resulting in a conductance per CNT far from 2G0. The consequence has been that, whereas CNTs are ultimately expected to yield FETs that are more conductive than conventional semiconductors, CNTs, instead, have underperformed channel materials, such as Si, by sixfold or more. We report quasi-ballistic CNT array FETs at a density of 47 CNTs μm⁻¹, fabricated through a combination of CNT purification, solution-based assembly, and CNT treatment. The conductance is as high as 0.46 G0 per CNT. In parallel, the conductance of the arrays reaches 1.7 mS μm⁻¹, which is seven times higher than the previous state-of-the-art CNT array FETs made by other methods. The saturated on-state current density is as high as 900 μA μm⁻¹ and is similar to or exceeds that of Si FETs when compared at and equivalent gate oxide thickness and at the same off-state current density. The on-state current density exceeds that of GaAs FETs as well. This breakthrough in CNT array performance is a critical advance toward the exploitation of CNTs in logic, high-speed communications, and other semiconductor electronics technologies.
Recently, the rapid and significant progress in the development of various stretchable electronics has triggered intense research interest. Although the remarkable features of transfer printing processes have enabled the use of inorganic crystalline semiconductors in various types of stretchable devices, including solar cells, light-emitting diodes, circuits, and photodetectors, there are few examples of stretchable electronics using thin film semiconductors. Transfer printing of inorganic amorphous thin film semiconductors remains a challenge because no suitable sacrificial layer is available. To meet this challenge, a water-soluble germanium oxide sacrificial layer is developed. Stretchable inorganic amorphous thin film solar cells are produced using a transfer printing process with a water-soluble sacrificial layer. This first attempt to fabricate stretchable solar cells with inorganic amorphous thin film semiconductors significantly broadens the scope of solar cell applications. Moreover, the germanium oxide sacrificial layer can be used in other thin film electronics applications.
Single-walled carbon nanotube (SWNT)-based electronics have been regarded as one of the most promising candidate technologies to replace or supplement silicon-based electronics in the future. These applications require high-density horizontally aligned SWNT arrays. During the past decade, significant efforts have been directed towards growth of high-density SWNT arrays. However, obtaining SWNT arrays with suitable density and quality still remains a big challenge. Herein, we develop a rational approach to grow SWNT arrays with ultra-high density using Trojan catalysts. The density can be as high as 130 SWNTs μm(-1). Field-effect transistors fabricated with our SWNT arrays exhibit a record drive current density of -467.09 μA μm(-1) and an on-conductance of 233.55 μS μm(-1). Radio frequency transistors fabricated on these samples exhibit high intrinsic fT and fMAX of 6.94 and 14.01 GHz, respectively. These results confirm our high-density SWNT arrays are strong candidates for applications in electronics.
Carbon nanotubes (CNTs) are quasi-one-dimensional materials with unique properties and are ideal materials for applications in electronic devices. Significant progress has been made on CNT electronics, and a doping-free approach has emerged from this research. This approach utilizes the contact control on the properties of field-effect transistors (FETs), preserving the perfect lattice of the CNT making it possible for CNT FETs to outperform state-of-the-art Si devices. Both n-type and p-type CNT FETs with near ballistic performance limits have been fabricated, symmetric CMOS devices have been demonstrated, and pass-transistor-logic, a circuit configuration that is more efficient than CMOS is being explored.
In this paper, the historical effects and benefits of Moore's law for semiconductor technologies are reviewed, and it is offered that the rapid learning curve obtained to the benefit of society by feature size scaling might be continued in several different ways. The problem is that as features approach the range of a few nanometers, electron-based devices depart radically from the ideal switch and, in fact, become very leaky in the off state. It is argued that there are some short-term solutions involving more highly parallel manufacturing, increased design efficiency, and lower cost packaging technologies that could continue the steep learning curve for cost reductions that have historically been achieved via Moore's Law scaling. Another alternative might be to increase chip functionality by integrating devices that offer broadened chip functionality including, e.g., sensors, energy sources, oscillators, etc. A third alternative would be to invent an entirely new information processing state variable based on different physics, using electron spin, magnetic dipoles, photons, etc., to improve the performance and reduce switching energy for devices whose smallest features are on the order of a few nanometers. Each of these alternatives is being actively explored and an overview of each strategy and progress to date is given in the paper. A final alternative offered in the paper is to learn from information processing examples in nature, specifically in living systems. An E.coli cell of about one cubic micrometer volume is shown to be an incredibly powerful and energy-efficient information processor relative to the performance of an end-of-scaling silicon processor of the same volume. The paper concludes by pointing out some of the crucial differences between E.coli information processing and conventional approaches with the hope technologies can be invented using the hints offered by biosystems.
We have developed a photolithographic process for the fabrication of large arrays of single walled carbon nanotube transistors with high quality electronic properties that rival those of transistors fabricated by electron beam lithography. A buffer layer is used to prevent direct contact between the nanotube and the novolac-based photoresist, and a cleaning bake at 300C effectively removes residues that bind to the nanotube sidewall during processing. In situ electrical measurement of a nanotube transistor during a temperature ramp reveals sharp decreases in the ON-state resistance that we associate with the vaporization of components of the photoresist. Data from nearly 2000 measured nanotube transistors show an average ON-state resistance of 250 ± 100 kΩ. This new process represents significant progress towards the goal of high-yield production of large arrays of nanotube transistors for applications including chemical sensors and transducers, as well as integrated circuit components.
Carbon nanotube (CNT) based integrated circuits (ICs) including basic logic and arithmetic circuits were demonstrated working under a supply voltage low as 0.4 V, which is much lower than that used in conventional silicon ICs. The low limit of supply voltage of the CNT circuits is determined by the degraded noise margin originated from the process inducing threshold voltage fluctuation. The power dissipation of CNT ICs can be remarkably reduced by scaling down the supply voltage, and it is of crucial importance for the further developments of nanoelectronics ICs with higher integration density.
Single-walled carbon nanotubes have exceptional electronic properties and have been proposed as a replacement for silicon in applications such as low-cost thin-film transistors and high-performance logic devices. However, practical devices will require dense, aligned arrays of electronically pure nanotubes to optimize performance, maximize device packing density and provide sufficient drive current (or power output) for each transistor. Here, we show that aligned arrays of semiconducting carbon nanotubes can be assembled using the Langmuir-Schaefer method. The arrays have a semiconducting nanotube purity of 99% and can fully cover a surface with a nanotube density of more than 500 tubes/µm. The nanotube pitch is self-limited by the diameter of the nanotube plus the van der Waals separation, and the intrinsic mobility of the nanotubes is preserved after array assembly. Transistors fabricated using this approach exhibit significant device performance characteristics with a drive current density of more than 120 µA µm(-1), transconductance greater than 40 µS µm(-1) and on/off ratios of ∼1 × 10(3).
Carbon electronics based on carbon nanotube array field-effect transistors (AFETs) and 2-D graphene field-effect transistors (GFETs) have recently attracted significant attention for potential RF applications. Here, we explore the ultimate RF performance potential for these two unique devices using semiclassical ballistic transport simulations. It is shown that the intrinsic current-gain and power-gain cutoff frequencies ( fT and f <sub>MAX</sub> ) above 1 THz should be possible in both AFETs and GFETs. Thus, both devices could deliver higher cutoff frequencies than traditional semiconductors such as Si and III-V's. In the case of AFETs, we show that their RF operation is not sensitive to the diameter variation of semiconducting tubes and the presence of metallic tubes in the channel. The ultimate fT and f <sub>MAX</sub> values in AFETs are observed to be higher than that in GFETs. The optimum device biasing conditions for AFETs require smaller biasing currents, and thus, lower power dissipation compared to GFETs. The degradation in high-frequency performance in the presence of external parasitics is also seen to be lower in AFETs compared to GFETs.
Existing models of electrical contacts are often inapplicable at the nanoscale because there are significant differences between nanostructures and bulk materials arising from unique geometries and electrostatics. In this Review, we discuss the physics and materials science of electrical contacts to carbon nanotubes, semiconductor nanowires and graphene, and outline the main research and development challenges in the field. We also include a case study of gold contacts to germanium nanowires to illustrate these concepts.
The semiconductor industry has been able to improve the performance of electronic systems for more than four decades by making ever-smaller devices. However, this approach will soon encounter both scientific and technical limits, which is why the industry is exploring a number of alternative device technologies. Here we review the progress that has been made with carbon nanotubes and, more recently, graphene layers and nanoribbons. Field-effect transistors based on semiconductor nanotubes and graphene nanoribbons have already been demonstrated, and metallic nanotubes could be used as high-performance interconnects. Moreover, owing to the excellent optical properties of nanotubes it could be possible to make both electronic and optoelectronic devices from the same material.
Single-walled carbon nanotubes (SWNTs) have many exceptional electronic properties. Realizing the full potential of SWNTs in realistic electronic systems requires a scalable approach to device and circuit integration. We report the use of dense, perfectly aligned arrays of long, perfectly linear SWNTs as an effective thin-film semiconductor suitable for integration into transistors and other classes of electronic devices. The large number of SWNTs enable excellent device-level performance characteristics and good device-to-device uniformity, even with SWNTs that are electronically heterogeneous. Measurements on p- and n-channel transistors that involve as many as approximately 2,100 SWNTs reveal device-level mobilities and scaled transconductances approaching approximately 1,000 cm(2) V(-1) s(-1) and approximately 3,000 S m(-1), respectively, and with current outputs of up to approximately 1 A in devices that use interdigitated electrodes. PMOS and CMOS logic gates and mechanically flexible transistors on plastic provide examples of devices that can be formed with this approach. Collectively, these results may represent a route to large-scale integrated nanotube electronics.
Electronic devices based on carbon nanotubes are among the candidates to eventually replace silicon-based devices for logic applications. Before then, however, nanotube-based radiofrequency transistors could become competitive for high-performance analogue components such as low-noise amplifiers and power amplifiers in wireless systems. Single-walled nanotubes are well suited for use in radiofrequency transistors because they demonstrate near-ballistic electron transport and are expected to have high cut-off frequencies. To achieve the best possible performance it is necessary to use dense arrays of semiconducting nanotubes with good alignment between the nanotubes, but techniques that can economically manufacture such arrays are needed to realize this potential. Here we review progress towards nanotube electronics for radiofrequency applications in terms of device physics, circuit design and the manufacturing challenges.
DNA bricks build nanotube transistors
Semiconducting carbon nanotubes (CNTs) are an attractive platform for field-effect transistors (FETs) because they potentially can outperform silicon as dimensions shrink. Challenges to achieving superior performance include creating highly aligned and dense arrays of nanotubes as well as removing coatings that increase contact resistance. Sun et al. aligned CNTs by wrapping them with single-stranded DNA handles and binding them into DNA origami bricks that formed an array of channels with precise intertube pitches as small as 10.4 nanometers. Zhao et al. then constructed single and multichannel FETs by attaching the arrays to a polymer-templated silicon wafer. After adding metal contacts across the CNTs to fix them to the substrate, they washed away all of the DNA and then deposited electrodes and gate dielectrics. The FETs showed high on-state performance and fast on-off switching.
Science , this issue p. 874 , p. 878
Carbon nanotubes (CNTs) have been considered a preferred channel material for constructing high-performance radio-frequency (RF) transistors with outstanding current gain cutoff frequency (fT) and power gain cutoff frequency (fmax), but the highest reported fmax is only 70 GHz. Here, we explore how good RF transistors based on solution-derived randomly oriented semiconducting CNT films, which are the most mature CNT materials for scalable fabrication of transistors and integrated circuits (ICs), can be achieved. Owing to the significantly reduced number of CNT/CNT junctions obtained by scaling the channel length down to below 100 nm, we realized RF field-effect transistors (FETs) with maximum transconductance Gm up to 0.38 mS/μm, which is the record among CNT-based RF FETs. After de-embedding the pad-induced capacitances and resistances, the CNT FETs with different gate lengths (Lg) exhibit fT as high as 103 GHz (intrinsically 281 GHz) or fmax up to 107 GHz (intrinsically 190 GHz), which are the records among CNT-based RF FETs. In particular, the CNT FETs with an Lg of 50 nm present pad de-embedding fT of 86 GHz and fmax of 85 GHz and represent the best CNT RF transistor in terms of comprehensive performance to date. To demonstrate the actual high speed and scalable fabrication of our CNT RF FETs, we fabricated CNT FET-based five-stage ring oscillators (ROs) with oscillation frequencies above 5 GHz.
Semiconducting single-walled carbon nanotube (SWCNT) thin film can be obtained by conjugated polymer wrapping sorting technique followed by solution deposition and can be utilized as channel materials of field-effect transistors and absorbing layer of photodiodes. However, after deposition process, there are still polymer molecules wrapping around nanotubes, remaining between nanotubes and remaining on the thin film surface, which will cause large nanotube-electrode resistance and tube-tube resistance. Here, we demonstrate an Yttrium oxide coating-and-decoating technique that can removes polymers only under electrodes and thus improves the performance of photodiodes without inducing new defects in device channel. Treating only contact area, the average short-circuit current of photodiode increases from 9.1 nA to 10.7 nA while the average open-circuit voltage increases from 0.25 V to 0.30 V. This method also improves device uniformity significantly.
Carbon nanotubes on the roadmap
The formal challenge for high-performance transistors is to fit within ever smaller devices. They need to shrink from a lateral dimension of about 100 to 40 nanometers. Cao et al. fabricated tiny devices by using a single semiconducting carbon nanotubes, as well as arrays of these nanotubes. High performance (a high saturation on-state current >1.2 milliamperes per micrometer and a conductance >2 millisiemens per micrometer) was delivered by making end-bonded contacts to the nanotubes with cobalt-molybdenum alloys.
Science , this issue p. 1369
Graphene technology has made great strides since the material was isolated more than a decade ago. However, despite improvements in growth quality and numerous 'hero' devices, challenges of uniformity remain, restricting large-scale development of graphene-based technologies. Here we investigate and reduce the variability of graphene transistors by studying the effects of contact metals (with and without Ti layer), resist, and yttrium (Y) sacrificial layers during the fabrication of hundreds of devices. We find that with optical photolithography, residual resist and process contamination is unavoidable, ultimately limiting device performance and yield. However, using Y sacrificial layers to isolate the graphene from processing conditions improves the yield (from 73% to 97%), average device performance (three-fold increase of mobility, 58% lower contact resistance), and the device-to-device variability (standard deviation of Dirac voltage reduced by 20%). In contrast to other sacrificial layer techniques, removal of the Y sacrificial layer with HCl does not harm surrounding materials, simplifying large-scale graphene fabrication.
In this paper, we report record radio frequency (RF) performance of carbon nanotube transistors based on combined use of a self-aligned T-shape gate structure, and well-aligned, high-semiconducting-purity, high-density polyfluorene-sorted semiconducting carbon nanotubes, which were deposited using dose-controlled, floating evaporative self-assembly method. These transistors show outstanding direct current (DC) performance with on-current density of 350 μA/μm, transconductance as high as 310 μS/μm, and superior current saturation with normalized output resistance greater than 100 kΩ·μm. These transistors create a record as carbon nanotube RF transistors that demonstrate both the current-gain cutoff frequency (ft) and the maximum oscillation frequency (fmax) greater than 70 GHz. Furthermore, these transistors exhibit good linearity performance with 1 dB gain compression point (P1dB) of 14 dBm and input third-order intercept point (IIP3) of 22 dBm. Our study advances state-of-the-art of carbon nanotube RF electronics, which have the potential to be made flexible and may find broad applications for signal amplification, wireless communication, and wearable/flexible electronics.
For the large-area fabrication of thin-film transistors (TFTs), a new conjugated polymer poly[9-(1-octylonoyl)-9H-carbazole-2,7-diyl] is developed to harvest ultrahigh-purity semiconducting single-walled carbon nanotubes. Combined with spectral and nanodevice characterization, the purity is estimated up to 99.9%. High density and uniform network formed by dip-coating process is liable to fabricate high-performance TFTs on a wafer-scale and the as-fabricated TFTs exhibit a high degree of uniformity.
Complementary logic gates based on chemically assisted directed assembly of solution carbon nanotubes with a high semiconducting purity (~91%) are demonstrated. Air stable, high quality carbon nanotube NFETs have been fabricated with low work function Erbium contacts, enabling an inverter gain of > 7 from transistors with 50 nm channel lengths. The substantial device yields of both NFET (~31%) and PFET (~44%) on the same chip allow us to construct and test a large number of CNT complementary logic gates for the first time. > 11% inverter yield from over 400 circuits tested along with fully functional NAND2 gates show promise of our fabrication scheme. This study points out several key directions for further yield enhancement, in which increasing the successful rate of CNT deposition into the trench plays a major role.
We have statistically studied the suppression of hysteresis in carbon nanotube field-effect transistors. The effect of the device fabrication process on the hysteresis has been investigated. The results show that contamination induced by the fabrication process impedes the suppression of hysteresis in device passivation. To remove the contamination, we have introduced a cleaning process as a treatment before passivation. The effectiveness of passivation with polymethylmetacrylate has been improved by the cleaning process using H2SO4/H2O2 solution.
Inductive coupled rf-plasma at 13.56 MHz was used to modify multiwalled carbon nanotubes (MWCNTs). This technique can be easily used to tailor the chemical composition of carbon nanotubes by attaching a wide variety of functional groups at their surface: oxygen-, nitrogen-, and fluorine-containing groups have been grafted. The influence of various plasma conditions (power, type of gas, treatment time, pressure, position of the CNT sample inside the chamber) on the functionalization of the MWCNT surface was analyzed by x-ray photoelectron spectroscopy. The results show that for too high oxygen plasma power, chemical etching occurs at the surface of the CNT, thus destroying its structure. On the other hand, for optimal values of the plasma parameters, functional groups (hydroxide, carbonyl, carboxyl, amine, fluorine, etc.) were found to bond to the CNT surface, suggesting that both the concentration and type of the functional groups are in close connection with the plasma conditions. These results were compared to interaction energies predicted by ab initio calculations for different functional groups under consideration, showing that functionalization by oxygen plasma produces mainly functional groups with lower interaction energy.
The effects of residues introduced during the transfer of chemical vapor deposited graphene from a Cu substrate to an insulating (SiO2) substrate on the physical and electrical of the transferred graphene are studied. X-ray photoelectron spectroscopy and atomic force microscopy show that this residue can be substantially reduced by annealing in vacuum. The impact of the removal of poly(methyl methacrylate) residue on the electrical properties of graphene field effect devices is demonstrated, including a nearly 2 x increase in average mobility from 1400 to 2700 cm(2)/Vs. The electrical results are compared with graphene doping measurements by Raman spectroscopy. (C) 2011 American Institute of Physics. [doi: 0.1063/1.3643444]
We have fabricated ballistic n-type carbon nanotube (CNT)-based field-effect transistors (FETs) by contacting semiconducting single wall CNTs using Sc. Together with the demonstrated ballistic p-type CNT FETs using Pd contacts, our work closes the gap for doping-free fabrication of CNT-based ballistic complementary metal-oxide semiconductor (CMOS) devices and circuits. We demonstrated the feasibility of this doping-free CMOS technology by fabricating a simple CMOS inverter on a SiO2/Si substrate using the back-gate geometry, but in principle much more complicated CMOS circuits may be integrated on a CNT on any suitable insulator substrate using the top-gate geometry and high-κ dielectrics. This CNT-based CMOS technology only requires the patterning of arrays of parallel semiconducting CNTs with moderately narrow diameter range, for example, 1.6−2.4 nm, which is within the reach of current nanotechnology. This may lead to the integration of CNT-based CMOS devices with increasing complexity and possibly find its way into the computers brain: the logic circuit.
The development of guided chemical vapor deposition (CVD) growth of single-walled carbon nanotubes provides a great platform for wafer-scale integration of aligned nanotubes into circuits and functional electronic systems. However, the coexistence of metallic and semiconducting nanotubes is still a major obstacle for the development of carbon-nanotube-based nanoelectronics. To address this problem, we have developed a method to obtain predominantly semiconducting nanotubes from direct CVD growth. By using isopropyl alcohol (IPA) as the carbon feedstock, a semiconducting nanotube purity of above 90% is achieved, which is unambiguously confirmed by both electrical and micro-Raman measurements. Mass spectrometric study was performed to elucidate the underlying chemical mechanism. Furthermore, high performance thin-film transistors with an on/off ratio above 10(4) and mobility up to 116 cm(2)/(V·s) have been achieved using the IPA-synthesized nanotube networks grown on silicon substrate. The method reported in this contribution is easy to operate and the results are highly reproducible. Therefore, such semiconducting predominated single-walled carbon nanotubes could serve as an important building block for future practical and scalable carbon nanotube electronics.
Polymers which enrich semiconducting single-walled carbon nanotubes (SWNTs) and are also removable after enrichment are highly desirable for achieving high-performance field-effect transistors (FETs). We have designed and synthesized a new class of alternating copolymers containing main-chain fluorene and hydrofluoric acid (HF) degradable disilane for sorting and preferentially suspending semiconducting nanotube species. The results of optical absorbance, photoluminescence emission, and resonant Raman scattering show that poly[(9,9-dioctylfluorenyl-2,7-diyl)-alt-co-1,1,2,2-tetramethyl-disilane] preferentially suspends semiconducting nanotubes with larger chiral angle (25°–28°) and larger diameter (1.03 nm–1.17 nm) (specifically (8,7), (9,7) and (9,8) species) present in HiPCO nanotube samples. Computer simulation shows that P1 preferentially interacts with (8,7) (semiconducting) over (7,7) (metallic) species, confirming that P1 selects larger diameter, larger chiral angle semiconducting tubes. P1 wrapped on the surface of SWNTs is easily washed off through degradation of the disilane bond of the alternating polymer main chain in HF, yielding “clean” purified SWNTs. We have applied the semiconducting species enriched SWNTs to prepare solution-processed FET devices with random nanotube network active channels. The devices exhibit stable p-type semiconductor behavior in air with very promising characteristics. The on/off current ratio reaches up to 15 000, with on-current level of around 10 μA and estimated hole mobility of 5.2 cm2 V−1 s−1.
Solution-processed single-walled carbon nanotubes (SWNTs) offer many unique processing advantages over nanotubes grown by the chemical vapor deposition (CVD) method, including capabilities of separating the nanotubes by electronic type and depositing them onto various substrates in the form of ultradensely aligned arrays at low temperature. However, long-channel transistors that use solution-processed SWNTs generally demonstrate inferior device performance, which poses concerns over the feasibility of using these nanotubes in high-performance logic applications. This paper presents the first systematic study of contact resistance, intrinsic field-effect mobility (μ(FE)), and conductivity (σ(m)) of solution-processed SWNTs based on both the transmission line method and the Y function method. The results indicate that, compared to CVD nanotubes, although solution-processed SWNTs have much lower μ(FE) for semiconducting nanotubes and lower σ(m) for metallic nanotubes due to the presence of a higher level of structural defects, such defects do not affect the quality of electric contacts between the nanotube and metal source/drain electrodes. Therefore, solution-processed SWNTs are expected to offer performance comparable to that of CVD nanotubes in ultimately scaled field-effect transistors, where contacts will dominate electron transport instead of electron scattering in the channel region. These results show promise for using solution-processed SWNTs for high-performance nanoelectronic devices.
The effect of source/drain (S/D) parasitic resistance has been experimentally investigated for amorphous silicon (a‐Si:H) thin film transistors (TFTs). In general, the apparent field effect mobility decreases with decreasing channel length. However, the apparent threshold voltage is relatively constant. This may be attributed to an ohmic parasitic resistance due to the use of ion‐implanted n<sup>+</sup> S/D regions. Self‐consistent results were obtained from both TFTs and from independent test structures for the TFT parasitic resistance, contact resistance, and sheet resistance. The results showed that the current spreading under the S/D regions is most critical in determining the magnitude of the total parasitic resistance. In this regard, both the S/D ion implantation and the S/D to gate overlap reduce the total parasitic resistance. Finally, the parasitic resistance is modeled as a gate voltage‐modulated channel resistance, under the gate overlap, in series with a constant minimum contact resistance.
This letter demonstrates the importance of the graphene/metal interface on the ohmic contacts of high-frequency graphene transistors grown by chemical vapor deposition (CVD) on copper. Using an Al sacrificial layer during ohmic lithography, the graphene surface roughness underneath the ohmic contacts is reduced by fourfold, resulting in an improvement in the contact resistance from 2.0 to 0.2-0.5 kΩ·μm. Using this technology, top-gated CVD graphene transistors achieved direct-current transconductances of 200 mS/mm, maximum on current densities in excess of 1000 mA/mm, and hole mobilities ~ 1500-3000 cm<sup>2</sup>/(V·s) on silicon substrates. Radio-frequency device performance yielded an extrinsic current-gain cutoff frequency f <sub>T</sub> of 12 GHz after pad capacitance de-embedding resulting in an f <sub>T</sub> - L <sub>G</sub> product of 24 GHz·μm.
A distributed contact model is presented for a 1-D quasi-ballistic conductor deriving a contact resistance versus contact length as a hyperbolic cotangent relationship in terms of the quantum of resistance, the coupling conductance g<sub>c</sub> of the contact, and the ballistic mean free path (λ<sub>b</sub>). The model gave excellent fits to recent contact resistance-versus-contact length data for carbon nanotubes giving g<sub>c</sub> = 2 μS/nm and λ<sub>b</sub> = 380 nm.
We present phenomenological predictions for the cutoff frequency of carbon nanotube transistors. We also present predictions of the effects parasitic capacitances on AC nanotube transistor performance. The influence of quantum capacitance, kinetic inductance, and ballistic transport on the high-frequency properties of nanotube transistors is analyzed. We discuss the challenges of impedance matching for ac nano-electronics in general, and show how integrated nanosystems can solve this challenge. Our calculations show that carbon nano-electronics may be faster than conventional Si, SiGe, GaAs, or InP semiconductor technologies. We predict a cutoff frequency of 80 GHz/L, where L is the gate length in microns, opening up the possibility of a ballistic THz nanotube transistor.
Two basic models for rectangular contacts to planar devices, the Kennedy-Murley Model (KMM) and the Transmission Line Model (TLM) are discussed and compared. The KMM does not take into account the interface resistance between metal and semiconductor, whereas the TLM disregards the vertical structure of the semiconductor layer. An extension of the TLM is derived (ETLM), which approximately considers this vertical structure. KMM and TLM thus appear as special cases of the ETLM. The calibration of the latter on the KMM then yields a simple quantitative criterion for the applicability of the KMM or the pure TLM. Measurement results on typical aluminum-silicon contacts are described satisfactorily by the (E)TLM. Concurrently with the applicability criterion, the KMM proves inadequate for these contacts due to the disregard of interface resistance. Conclusions are derived from the TLM pertaining to current distribution over the contact area and to contact resistance. In particular, the contacts are classified according to their operation mode. Finally, the TLM approach is applied also to circular contacts.
The preparation of a new type of finite carbon structure consisting of
needlelike tubes is reported. Produced using an arc-discharge
evaporation method similar to that used for fullerene sythesis, the
needles grow at the negative end of the electrode used for the arc
discharge. Electron microscopy reveals that each needle comprises
coaxial tubes of graphitic sheets ranging in number from two up to about
50. On each tube the carbon-atom hexagons are arranged in a helical
fashion about the needle axis. The helical pitch varies from needle to
needle and from tube to tube within a single needle. It appears that
this helical structure may aid the growth process. The formation of
these needles, ranging from a few to a few tens of nanometers in
diameter, suggests that engineering of carbon structures should be
possible on scales considerably greater than those relevant to the
fullerenes.
In this article, the authors investigate the formation and removal of resist residues with the main objective to improve the reliability of transistor gate fabrication. Device performance is strongly dependent on the quality of metal contacts and the interface between gate metal and substrates. Reliable transistor fabrication becomes increasingly difficult as transistor dimensions shrink. Residual resist layers can become significant if wet or dry etching steps are required for gate recessing, e.g., for high electron mobility transistors or the removal of thin oxide layers in III-V metal oxide semiconductor field effect transistor fabrication. They observe two sorts of residual resist layers in polymethyl methacrylate (PMMA): exposed and nonexposed. Exposed residuals have been observed by many groups in electron beam exposed and developed regions of PMMA. In this article, they show that the observed granularity lies on top of a continuous residual film and consider this effect on gate fabrication. They also present evidence of a nonexposed residual layer observed in regions of unexposed resist which have been subject to a standard solvent based resist strip and cleaning procedure. They further demonstrate that CV measurement techniques can be used to detect the presence of residual layers of resist.
Recent studies and device demonstrations indicate that horizontally aligned arrays of linearly configured single-walled carbon nanotubes (SWNTs) can serve as an effective thin film semiconductor material, suitable for scalable use in high-performance transistors. This paper presents the results of systematic investigations of the dependence of device properties on channel length, to reveal the role of channel and contact resistance in the operation. The results indicate that, for the range of channel lengths and SWNT diameters studied here, source and drain contacts of Pd yield transistors with effectively Ohmic contacts that exhibit negligible dependence of their resistances on gate voltage. For devices that use Au, modulation of the resistance of the contacts represents a significant contribution to the response. Extracted values of the mobilities of the semiconducting SWNTs and the contact resistances associated with metallic and semiconducting SWNTs are consistent with previous reports on single tube test structures.
Graphene is a two-dimensional material with extremely favorable chemical sensor properties. Conventional nanolithography typically leaves a resist residue on the graphene surface, whose impact on the sensor characteristics has not yet been determined. Here we show that the contamination layer chemically dopes the graphene, enhances carrier scattering, and acts as an absorbent layer that concentrates analyte molecules at the graphene surface, thereby enhancing the sensor response. We demonstrate a cleaning process that verifiably removes the contamination on the device structure and allows the intrinsic chemical responses of the graphene monolayer to be measured. These intrinsic responses are surprisingly small, even upon exposure to strong analytes such as ammonia vapor.