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Design and Implementation of a High-Performance
4-bit Vedic Multiplier Using a Novel 5-bit Adder in
90nm Technology
Hemanshi Chugh
Electronic & Comm. Engineering
Delhi Technological University
Delhi, India
hemanshichugh_2k20phdec508@dtu.ac.in
Sonal Singh
Electronic & Comm. Engineering
Delhi Technological University
Delhi, India
sonalsingh@dtu.ac.in
Abstract— A multiplier is an essential component in high-
performance systems including digital signal processors,
arithmetic & logical units (ALU), and various other
communication systems. The multiplication method essentially
needs a lot of hardware resources and more computation time
than the other arithmetic operations such as addition and
subtraction. In recent years, the development of portable
electronics has compelled developers to enhance the existing
multiplier designs for improved performance. Vedic
mathematics consists of five sutras(formulas) for
multiplication; however, the Urdhva Tiryagbhyam sutra is
principally utilized as it is a general sutra suited for all types of
multiplication providing faster computation with minimum
delay time. The proposed architecture in this work uses a novel
5-bit special adder along with conventional full adders and half
adders for implementing the 4*4 multiplier using the Urdhva
Tiryagbhyam technique of Vedic Mathematic. The multiplier
modules are designed in the Cadence Virtuoso System design
platform. Subsequently, the conventional and proposed 4- bit
multiplier designs are simulated and verified in the Cadence
spectre simulation platform in a 90nm CMOS technology
library file. The results show an overall improvement for the
proposed 4*4 Vedic multiplier with a 52.2% reduction in
power, 48.6% reduction in delay, and 75% decrease in the
power-delay product (PDP) of the circuit against the
conventional CMOS Vedic multiplier.
Keywords— Cadence Virtuoso, Urdhva Tiryagbhyam (UT)
Sutra, Vedic Multiplier (VM), 5-bit adder, 90nm CMOS.
I. INTRODUCTION
Multiplication is a significant arithmetic function in
digital system designs as multipliers are used extensively in
integrated circuits such as FIR filters, communication
systems, signal processors etc. There are three major
classifications in the multiplier architectures – serial
multipliers, parallel multipliers and serial-parallel multipliers
(Fig. 1). Several algorithms for implementing fast multipliers
have been described in the literature. An efficient multiplier
architecture is often designed to offer either of the following
design target: low power, high speed and less area in the
circuit. However, the combination of these design targets
makes them even more suitable for low-power VLSI
applications. Multiplication using Vedic mathematics [1] has
proved to be advantageous over the other multiplication
algorithms due to their architectural regularity, reduced
hardware requirements, low power and less delay of the
circuit.
Veda is a Sanskrit word signifying ‘Knowledge’. In
Vedic mathematics, various principle techniques are put
together to perform multiple calculations in simple and
robust way [2]. There are sixteen sutras and thirteen upa
Fig. 1. Classifications of multiplier architectures with their characteristics
sutras (sub sutras) in total that are utilized for various
arithmetical operations, geometry, conics, calculus, and
algebra. Multiplication can be performed by using five
sutras/sub-sutras from these techniques. Fig. 2 illustrates the
two approaches of Vedic multiplication. The general
approach is suitable for all sets of numbers in any number
system whereas a specific approach is suitable only for some
particular multiplication sets.
Fig. 2. General and specific approaches of Vedic multiplication sutras
For instance, Nikhilam sutra (all from 9, last from 10) is a
Vedic technique for multiplication of numbers closest to any
power of 10 [2]. Anurupyena (meaning proportionately) is a
sub-sutra to Nikhilam sutra which is used when the operands
are not close to the power of 10 [3]. A convenient multiple of
the suitable base is taken as the working base to perform the
multiplication similar to Nikhilam sutra and the result is then
multiplied/divided proportionately. The sutra Ekanyunena
Purvena (one less than the one before) is utilized when one
2022 10th International Conference on Reliability, Infocom Technologies and Optimization (Trends and Future Directions) (ICRITO)
Amity University, Noida, India. Oct 13-14, 2022
978-1-6654-7433-7/22/$31.00 ©2022 IEEE
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2022 10th International Conference on Reliability, Infocom Technologies and Optimization (Trends and Future Directions) (ICRITO) | 978-1-6654-7433-7/22/$31.00 ©2022 IEEE | DOI: 10.1109/ICRITO56286.2022.9964936
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operand is 9 or an array of 9 [4]. Antyayordashake'pi (by
completion or non-completion) is a shortcut technique
applicable to operands if the addition of last digits of
operands is 10 and the remaining digits are same [5]. The UT
(vertical & crosswise) technique is the most powerful
technique of Vedic multiplication [6] as it can be applied to
any set of operands in the number system. Hence, it is widely
utilized in digital systems for multiplication.
The paper consists of sections described as follows.
Section II describes the UT sutra in detail. Section III
provides detailed description of the architecture modules of
the 2*2 VM, conventional 4-bit VM and the proposed 4-bit
VM. Section IV shows the implementation and simulation
results of the architectures in Cadence Virtuoso. Section V
gives a performance comparative study of the conventional
and proposed 4-bit Vedic multiplier whereas Section VI
provides a power comparison analysis of the Vedic
multiplier in this work with other related works. Section VII
summarizes and concludes the work.
II. URDHVA TIRYAGBHYAM TECHNIQUE
A Urdhva Tiryagbhyam (UT) sutra uses a vertical and
crosswise technique for the multiplication of any integral
number [7]. This sutra can be used for various bit lengths
such as 2, 4, 8, 16…. N for binary multiplication. This paper
comprises the design and implementation of the 4-bit
multiplier through the UT technique.
The line diagram of 2-bit binary numbers 01 (decimal 1)
and 10 (decimal 2) is displayed in Fig. 3 to illustrate the UT
algorithm. The LSBs are vertically multiplied in step 1
followed by crosswise multiplication and addition of the two
bits in step 2. Further, vertical multiplication of the MSBs is
done to get the final product as 010 (decimal 2).
Fig. 3. Illustrative depiction of 2-bit UT based Vedic multiplication(adapted
from [7])
Similarly, the fundamentals of this sutra can be applied
for higher-order binary multiplication [8]. Fig. 4 clearly
illustrates a step-wise multiplication of a 4-bit VM.
Fig. 4. llustrative depiction of 4-bit Vedic multiplication with UT sutra
The 4-bit binary operands are taken for illustration as
1010(decimal 10) and 1011(decimal 11). The partial
products are produced using the vertical and crosswise
process in 7 steps and the final product is displayed in Step
8: 01101110(decimal 110).
III. ARCHITECTURE MODULES
The below sections display the conventional CMOS
architecture modules of 2-bit and 4-bit VM and the proposed
novel architecture for 4-bit binary multiplication using a
special 5-bit adder with basic gates, full adder and half adder
utilizing the UT algorithm. The sutra is well designed for
parallel processing as the partial product generation and
additions are carried out simultaneously thereby reducing the
overall delay of the circuit and hence making it very efficient
for binary multiplications.
A. 2-bit Vedic Multiplier using UT sutra
The multiplication technique for two operands A and B
such that A = A1A0 and B = B1B0, where A0 and B0 signify
the LSBs and A1 and B1 are the MSBs. The LSB of the
product (Q0) is generated by the vertical multiplication of A0
and B0 (LSBs) followed by crosswise multiplication of the
bits of A and B (A1B0, A0B1). The next bit of the product (Q1)
is generated by the addition of these bits. Thereafter, vertical
multiplication of the MSBs (A1B1) is done. The third and
fourth bit of the final product (Q2Q3) are sum and carry of the
addition of the previous carry to this partial product
respectively(A1B1) [9].
The 2-bit architecture of the VM comprises of 4 AND
gates with 2 Half Adders; depicted in Fig. 5.
Fig. 5. Conventional CMOS 2-bit Vedic multiplier
B. 4-bit Vedic Multiplier using UT sutra
The implementation of the conventional CMOS 4*4
multiplier module is illustrated in Fig. 5. Let A and B be
binary numbers of four bits each such that A0 and B0 are the
LSBs and A3 and B3 are the MSBs. The final 8-bit product is
defined as Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0. To generate the LSB of
the product(Q0), multiply A0 and B0. Now, the operands A
and B, split as A3A2; A1A0, B3B2; B1B0, are multiplied
crosswise and vertically (similar to 2*2 Vedic module) to
yield partial products which are added using 4-bit ripple
carry adders (RCA), resulting in final product bits, namely,
Q7 to Q1.
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Fig. 6. Conventional CMOS 4-bit Vedic multiplier
C. Proposed architecture of 4-bit Vedic Multiplier
In an effort to enhance the overall working of the
multiplier, certain modifications in the initial building blocks
of architectural design are proposed. Fig. 7 illustrates the use
of sixteen AND gates, six full adders, three half adders,
with a special 5-bit adder for making an efficient multiplier
architecture. A special 5-bit adder is designed such that it
takes 5 bits of binary data and generates a 3-bit output. The
internal architecture of a 5-bit adder (Fig. 8) comprises of
two full adders to generate the sum and a half adder to
generate the carry bits C0 and C1.
Fig.7. Architecture of the proposed 4*4 VM module using a 5- bit adder
Fig.8. Internal architecture of the 5- bit special adder
The truth table comprising of all the possible input-output
combinations for the novel 5-bit special adder are tabulated.
Table I consists of 32 different combinations of inputs (x, y,
z, w, ca) represented as a three-bit output (C1, C0, Sum).
TABLE I. TRUTH TABLE OF NOVEL 5-BIT SPECIAL ADDER
Sno.
Inputs
Outputs
x
y
z
w
Ca
C1
C0
Sum
1
0
0
0
0
0
0
0
0
2
0
0
0
0
1
0
0
1
3
0
0
0
1
0
0
0
1
4
0
0
0
1
1
0
1
0
5
0
0
1
0
0
0
0
1
6
0
0
1
0
1
0
1
0
7
0
0
1
1
0
0
1
0
8
0
0
1
1
1
0
1
1
9
0
1
0
0
0
0
0
1
10
0
1
0
0
1
0
1
0
11
0
1
0
1
0
0
1
0
12
0
1
0
1
1
0
1
1
13
0
1
1
0
0
0
1
0
14
0
1
1
0
1
0
1
1
15
0
1
1
1
0
0
1
1
16
0
1
1
1
1
1
0
0
17
1
0
0
0
0
0
0
1
18
1
0
0
0
1
0
1
0
19
1
0
0
1
0
0
1
0
20
1
0
0
1
1
0
1
1
21
1
0
1
0
0
0
1
0
22
1
0
1
0
1
0
1
1
23
1
0
1
1
0
0
1
1
24
1
0
1
1
1
1
0
0
25
1
1
0
0
0
0
1
0
26
1
1
0
0
1
0
1
1
27
1
1
0
1
0
0
1
1
28
1
1
0
1
1
1
0
0
29
1
1
1
0
0
0
1
1
30
1
1
1
0
1
1
0
0
31
1
1
1
1
0
1
0
0
32
1
1
1
1
1
1
0
1
IV. SCHEMATIC DESIGNS & SIMULATION
RESULTS
This section presents the schematic designs and
simulation results of the architecture modules described in
the above sections.
A. Schematic Designs
The schematics designs presented here are implemented
in Cadence Virtuoso Design platform v6.1.5.
The CMOS implementation of the schematic design of
the novel 5-bit special adder is presented in Fig. 9 which
takes 5 bits of data as input and gives a 3-bit output. Further,
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Fig. 10 represents the CMOS implementation of the
conventional 2- bit VM comprising of AND gates and Half
Adder circuit to generate a 4-bit product.
Fig. 9. Schematic of the Novel 5-bit Special Adder
Fig. 10. Schematic of CMOS 2-bit VM
Fig. 11 presents the implementation of the schematic
design of the conventional CMOS VM of 4 bits (Fig. 6). The
design is made using four blocks of 2-bit Vedic multiplier
(Fig. 5) together with three four-bit RCAs.
Fig. 11. Schematic of the conventional CMOS 4-bit VM
Fig. 12 presents the schematic design for the novel 4-bit
VM. The circuit comprises of 16 AND gates, 6 Full Adders,
3 Half adders and one 5-bit special adder combined together
(Fig. 5) to propose a comparatively low power and faster
VM.
Fig. 12. Schematic of the Novel 4*4 Vedic Multiplier using a 5-bit adder
B. Simulation Waveforms in ADEL
The schematics are verified and simulated in the Analog
Design Environment (ADEL) using the spectre simulation
platform using 90nm technology at 2 V power supply. The
input-output waveforms of the novel 5-bit special adder are
shown in Fig. 13. x, y, z, w and ca are the inputs to the adder
and C1, C0 and Sum are the outputs of the adder.
Fig. 13. Input output waveform of 5-bit novel adder
Further, Fig. 14 shows the simulation waveform of the
CMOS implementation of the 2-bit VM. The input output
waveforms of the conventional 4-bit VM are as shown in
Fig. 15 where A3 A2 A1 A0 and B3 B2 B1 B0 are fed as
inputs to the multiplier and Q7Q6Q5Q4Q3Q2Q1Q0 display the
output of the multiplier and C represents the output carry.
Fig. 14. Input Output Waveform of Conventional 2-bit Vedic multiplier
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Fig. 15. Input Output Waveform of Conventional 4-bit Vedic multiplier
The simulated waveforms of the novel 4-bit Vedic
multiplier are as shown in Fig. 16 where A3A2A1A0 and
B3B2B1B0 are inputs to the multiplier and
Q7Q6Q5Q4Q3Q2Q1Q0 display the output(8-bit) of the
multiplier. The proposed multiplier is verified for all
possible input combinations. Some of the multiplication
results (Fig. 16) are also tabulated in Table II for the
different input combinations to the multiplier.
Fig. 16. Input Output Waveform of Proposed 4-bit Vedic multiplier
TABLE II. MULTIPLICATION RESULTS OF THE 4*4 VM
Sno.
A
decimal
A
binary
B
decimal
B
binary
Q
decimal
Q
binary
1
15
1111
15
1111
225
11100001
2
13
1101
07
0111
91
01011011
3
07
0111
15
1111
105
01101001
4
01
0001
02
0010
02
00000010
5
10
1010
10
1010
100
01100100
6
08
1000
00
0000
00
00000000
7
06
0110
13
1101
78
01001110
8
04
0100
05
0101
20
00010100
V. COMPARATIVE ANALYSIS OF THE
CONVENTIONAL AND PROPOSED VEDIC
MULTIPLIER
The following observations are tabulated in Table III for
the conventional and proposed 4-bit multiplier when the
conventional and proposed multiplier schematics are
simulated for a transition time of 90 ns. The number of
accepted transient steps, peak resident memory used and
processor time required is observed from the netlist after
simulation and the comparative analysis of the
conventional 4*4 Vedic multiplier with the proposed
design is shown via the column chart in Fig. 17. Table IV
analyses the transistor count, average power, overall
propagation delay and power delay product (PDP) for the
conventional and proposed 4*4 Vedic multipliers. The
compared outcome is also displayed through a column
chart (Fig. 18). PDP (also known as switching energy) is
associated with the energy efficiency of the system. It is
noted that there is a 52.2% reduction in power, 48.6%
reduction in delay, and 75% decrease in the PDP of the
circuit for the proposed 4*4 Vedic multiplier in contrast to
the conventional 4*4 Vedic multiplier.
TABLE III. COMPARATIVE ANALYSIS OF THE ADE NETLIST
4*4 Vedic
Multiplier
Number of
accepted
trans steps
Peak
resident
memory
used
(MB)
Processor
time (sec)
Conventional
1568
57.5
24.32
Proposed
1329
50.5
13.95
TABLE IV. COMPARATIVE ANALYSIS OF 4*4 VM
4*4 VM
Power
(uW)
Delay(ps)
Transistor
Count
PDP
Conventional
143.6
341.7
762
49.06
Proposed
68.5
175.4
504
12.01
Fig. 17. Graphical representation of netlist analysis for 4-bit VM
Fig. 18. Graphical representation of performance analysis for 4-bit VM
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VI. RELATED WORKS
Table V summarizes the obtained results of power
dissipation of the 4-bit Vedic multiplier against the
conventional and modified versions of 4-bit Vedic, Array,
Wallace tree and Hybrid Dadda multiplier implementations
on Cadence Virtuoso in 90 nm technology carried out in the
literature. It can be clearly observed that the Vedic
mathematics approach in our work is much advantageous as
the results of the proposed VM are promising in comparison
to other multipliers implemented on the same technology.
Fig. 18 depicts the graphical representation of the power
analysis of the proposed 4-bit VM design with other 4-bit
multiplier designs. It is observed that the proposed design is
beneficial concerning the power dissipation in the system.
TABLE V: POWER ANALYSIS OF DIFFERENT 4*4 MULTIPLIERS
Sno.
Multipliers
Power
(uW)
1.
Conventional Array [10]
389
2.
Modified Array [10]
170
3.
Conventional Wallace tree [10]
2283
4.
Modified Wallace tree [10]
192
5.
Hybrid Dadda [11]
184.3
6.
Conventional Vedic [12]
361.2
7.
Modified Vedic [12]
290.2
8.
Conventional Vedic (this work)
143.6
9.
Proposed Vedic (this work)
68.5
Fig. 19. Graphical Representation of Power Analysis of Different 4*4
Multipliers
VII. CONCLUSION
This work puts forward a proficient 4*4 multiplier
utilizing UT Vedic sutra which uses a novel 5-bit special
adder in its schematic design. All the schematics have been
designed in Cadence Virtuoso v6.1.5 and simulated in the
ADEL environment using the spectre simulation platform in
a 90nm CMOS technology library file. A comparison of
delay, average power, transistor count, and PDP is carried
out in this work. The design implementation and results
show 52.2% of the power reduction and 48.6% reduction in
delay in the novel design in contrast to the conventional 4-bit
Vedic multiplier. The power delay product also decreases to
75% in the novel design. Notably, the time consumption of
the processor significantly reduces from 24.32 seconds to
13.95 seconds and the complexity in computation is also
reduced as it requires a smaller number of steps in
comparison to the conventional VM. Further, it is observed
that the VM outperforms other implementations of
conventional and modified multipliers namely Array
multiplier, Wallace tree multiplier, Hybrid Dadda multiplier,
Vedic multiplier in similar technology. Thus, the suggested
4*4 VM will prove beneficial in any ALU, VLSI application,
DSP structures or processor [7].
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