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Low Power, Noise-Immune High Performance Arithmetic Adder Circuit Design Using Modified Parallel Prefix Adders
Abstract
Low power arithmetic adders are very important circuits in any computing device such as signal processing, image processing and other fields of VLSI, etc. At present, high performance computing devices and the scaling of CMOS technology are becoming less effective in improving the system performance. Either we should wait until the breakthrough in CMOS technology or should look for alternative technologies to improve the system performance. Previous works have designed approximate parallel prefix adders (PPA) using CMOS technology. But, where the performance of the adders decreases as we go to higher order bits, because of area consumption. To decrease power consumption and delay, we are introducing “Pass Transistor Logic” to reduce the number of transistors. The analysis is being done using Cadence Design Framework at 45 nm and the values of power, delay are compared with various other designs. To examine the performance of the proposed adder, approximate Kogge-Stone PPA adder using PTL technology. Simulation results have been shown that the proposed adder has better performance as the delay is reduced by 82.4% when compared to traditional adders. In terms of power consumption, the proposed design ends up with 49.3% less power.KeywordsParallel prefix adder (PPA)Pass transistor logic (PTL)Kogge-Stone adder (KSA)Ladner-Fischer adder (LFA)Error tolerant adder (ETA)Carry look ahead adder (CLA)
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In conventional approach for VLSI, implementing large numbers of operations in parallel is possible with NN. The fundamental task of a neural network hardware is not dependent on the implementation technology and are quite constructive in simulating the digital circuits. These NN representations can be incorporated in various applications where in the behaviour of these circuits are essential to get a solution for discrete problems. Therefore, supervised learning algorithms are used to train the computer software. One such algorithm is the L-M method which is one of the powerful and widely used approaches. This paper accounts to the designing and training of a neural network model as computing technique in 5:3 compressor with Lavenberg-Marquardt Algorithm. The performance parameters are significantly remarkable for real time implementation, are presented in the paper.
The basic processes like addition, subtraction can be done using various types of binary adders with dissimilar addition times (delay), area and power consumption in any digital processing applications. To minimize the Power Delay Product (PDP) of Digital Signal Processing (DSP) processors is necessary for high performance in Very Large Scale Integration (VLSI) applications. In this paper, a 32–bit various Parallel Prefix adders design is proposed and compared the performance results on the aspects of area, delay and power. Implementation (Simulation and Synthesis) results really achieve significant improvement in power and power-delay product when compared with the previous bit adders which is used in processors. To reduce the power, here apply the energy recovery logic like power gating technique for all three adders. All the simulations and synthesis results can be noted using Xilinx ISE 14.2i tool.
All modern processor, including
microprocessor, digital signal processor contain
Arithmetic Logic Unit [ALU]. The computing
efficiency of these modern processor mainly
depended on efficiency of ALU. An adder is the
basic building block for an ALU which performs
arithmetic as well as logic operation. The existing
adders like half adder, full adder, ripple carry
adder, carry skip adder and carry lookahead adders
cannot meet the expected optimization goals, so in
this paper proposed four type of Parallel prefix
adder [PPA] like Sklansky adder, Kogge-Stone
adder, Brent-Kung adder, and Ladner-Fischer
adder. Parallel prefix adder [PPA] are kind of adder
that uses prefix operation in order to do efficient
addition. These adders are suited for binary
addition with wide word. The Parallel prefix adders
are derived from the carry look ahead adder. The
performance analysis of PPA considered on area,
delay and power consumption and simulation are
carried out for 8bit input data width.
This paper presents a VLSI implementation of a high speed Kogge-Stone adder (KSA) using 0.18µm process technology. The adder is known to be one of the fastest adder architectures, and this is validated through a comparison with other adder architectures including the standard ripple carry adder and the carry look ahead adder. Furthermore, our KSA adder is also compared with a default optmized adder from the Artisan standard cell library. The adders are compared for bit widths of 8, 16, and 32. The adders are designed using Verilog and synthesized using both front-end and back-end tools, with complete validation and verification stages, including analysis for performance, power, and area. Results show that in terms of performance, KSA results in the lowest propagation delay with almost constant delay for all bit widths, with up to 70% less delay as compared to all other architectures. Area and power penalty is found to also increase by roughly 59%. In terms of energy usage, the KSA adder results in up to 64% less. In the case when speed and energy are critical, this fast and energy efficient KSA adder can be readily integrated into custom VLSI designs.
In Very Large Scale Integration (VLSI) designs, Parallel prefix adders (PPA) have the better delay
performance. A parallel prefix adder involves the execution of the operation in parallel which can be obtained by
segmentation into smaller pieces. The binary addition is the basic arithmetic operation in digital circuits and it became
essential in most of the digital systems including Arithmetic and Logic Unit (ALU), microprocessors and Digital Signal
Processing (DSP). At present, the research continues on increasing the adder’s delay performance.In this paper the
investigation of four types of PPA’s (Kogge Stone Adder (KSA), Spanning Tree Adder (STA), Brent Kung Adder
(BKA) and Sparse Kogge Stone Adder (SKA)) is done. Additionally Ripple Carry Adder (RCA), Carry Lookahead
Adder (CLA) and Carry Skip Adder (CSA) are also investigated. These adders are implemented in verilog Hardware
Description Language (HDL) using Xilinx Integrated Software Environment (ISE) 13.4 Design Suite. The area, delay
and power consumed by all types of PPA’s are analyzed. The area of the adder design are given in terms of Look Up
Tables (LUT’s) and Input Output bounds (IOB’s). The adder designs are implemented and delay, power and area of all
the adders are investigated.
Adders form an almost obligatory component of every contemporary integrated circuit. The prerequisite of the adder is that it is primarily fast and secondarily efficient in terms of power consumption and chip area. This paper presents the pertinent choice for selecting the adder topology with the trade off between delay, power consumption and area. The adder topology used in this work are ripple carry adder, carry look ahead adder, carry skip adder, carry select adder, carry increment adder, carry save adder and carry bypass adder. The module functionality and performance issues like area, power dissipation and propagation delay are analyzed at 0.12µm 6 metal layer CMOS technology using micro wind tool.
Automation techniques and machine learning algorithms are playing a crucial role in almostall fields in recent times. In this research, a 4:2 compressor circuit is approximated using theprobabilistic pruning technique. An artificial neural network is designed for the proposed 4:2compressor and is trained to obtain the train and test accuracies. The neural network withequal train and test accuracies has been considered as the best approximate circuit. The trainingof the neural network has been performed using a supervised machine learning algorithm byapplying truth table of the proposed approximate 4:2 compressor as the dataset. The proposedcompressor has only 19 transistors and consumes less energyi.e.,0.2015 nJ with less silicon areaof 14.36 um2. The performance of the Dadda multiplier is improved by replacing the proposedapproximate 4:2 compressor into its partial product reduction stage.
Approximate ripple carry adders (RCAs) and carry lookahead adders (CLAs) are presented which are compared with accurate RCAs and CLAs for performing a 32-bit addition. The accurate and approximate RCAs and CLAs are implemented using a 32/28nm CMOS process. Approximations ranging from 4- to 20-bits are considered for the less significant adder bit positions. The simulation results show that approximate RCAs report reductions in the power-delay product (PDP) ranging from 19.5% to 82% than the accurate RCA for approximation sizes varying from 4- to 20-bits. Also, approximate CLAs report reductions in PDP ranging from 16.7% to 74.2% than the accurate CLA for approximation sizes varying from 4- to 20-bits. On average, for the approximation sizes considered, it is observed that approximate CLAs achieve a 46.5% reduction in PDP compared to the approximate RCAs. Hence, approximate CLAs are preferable over approximate RCAs for the low power implementation of approximate computer arithmetic.
Approximate computing has become a well-known computing technique in recent years. It relies on the ability of many systems and applications to self-heal or to tolerate some loss of quality or optimality in the computed result. The main idea is to exploit the inherent error resiliency or error tolerance of the system to achieve energy efficiency, or in other words, trading accuracy with energy consumption. Such trade-off, in most cases, is also associated with performance improvements like faster operations, area reduction etc. Fortunately, most of the heavy workloads nowadays exhibit intrinsic application resilience [1],[2]. In most multimedia applications, the final output is interpreted by human senses, which are not perfect. This fact averts the need to produce exact outputs. Recent research efforts have quantitatively ascertained the high degree of inherent resilience in many applications. For example, our analysis of a benchmark suite of 12 recognition, vision and multimedia applications shows that on average, 83% of the runtime is spent in computations that can tolerate at least some degree of approximation [3]. Therefore, there is a potential to leverage inherent resilience in a broad context. Let us consider digital signal processing (DSP). In multi-media applications, DSP blocks implement image, sound and video processing algorithms, where the final output is either an image or sound or a video for human senses. When interpreting an image or a sound or a video, human beings have limited perceptual capacities. This allows the system to be flexible in producing quality outputs. As an example, the relaxation on numerical precision provides some freedom to carry out imprecise or approximate computation. Another example of approximate signal processing is the utilization of incremental refinement. In [4], number of ideas and approaches regarding the use of incremental refinement to develop energy efficient structures for the basic application-specific DSP systems such as FFT, DFT, DCT, FIR, IIR etc. have been discussed. It is evident that the tradeoffs may allow approximate computing to handle tasks beyond what we can do with traditional computing.There are different levels of design abstraction where approximate computing methods can be implemented [4]- [10]. In this paper we will briefly describe different approaches that we have developed to implement approximate hardware for error resilient applications.
This paper primarily discusses the construction of different high speed adders using very high speed integrated circuit hardware design in the platform Modelsim 5.5c. The reason for this investigation is that adders are the most important circuits requiring improved designs in order to obtain maximum gain possible. In any digital system adders are the most fundamental unit. Addition is an indispensible operation in any Digital, Analog, or Control system. They are not only as arithmetic logic unit in computers and some processors but used in some other kind of processors too, where they are used to calculate addresses, table indices, and similar operations [6]. Today technology in measured by its ability to measure computational algorithms. This paper discusses the drawbacks and gains of ripple carry, carry look ahead, carry select and kogges stone in terms of area, speed, delay. This paper focuses on implementation and simulation of 64 bit full adder using very high speed integrated circuit hardware description language(VHDL).
In Very Large Scale Integration (VLSI) designs, Parallel prefix adders (PPA) have the better delay performance. This paper investigates four types of PPA's (Kogge Stone Adder (KSA), Spanning Tree Adder (STA), Brent Kung Adder (BKA) and Sparse Kogge Stone Adder (SKA)). Additionally Ripple Carry Adder (RCA), Carry Lookahead Adder (CLA) and Carry Skip Adder (CSA) are also investigated. These adders are implemented in verilog Hardware Description Language (HDL) using Xilinx Integrated Software Environment (ISE) 13.2 Design Suite. These designs are implemented in Xilinx Virtex 5 Field Programmable Gate Arrays (FPGA) and delays are measured using Agilent 1692A logic analyzer and all these adder's delay, power and area are investigated and compared finally.
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