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A transconductor-based field-programmable analog array
Abstract
Field-programmable gate arrays for prototyping digital circuits
are a widely endorsed approach for reducing time-to-market. Offering
similar advantages, a field-programmable analog array (FPAA) for
prototyping continuous-time analog circuits is reported here.
Conceptually, a FPAA consists of configurable analog blocks (CABs) and
interconnects. The function of each CAB and the connections among CABs
are determined by the contents of an on-chip shift register. Different
circuits can be instantiated using a FPAA by loading in different
configuration bits. This IC strategy offers simplified analog circuit
design with the advantages of instant prototyping, programmable
topology, programmable parameters, CAD compatibility, and testability
... The final FPAA design featured two CABs and one interconnect switch block [9]. Further development on the design focused on decreasing the parasitic effect of the switching blocks through the use of transconductor based connection cell in place of pass-transistor switches [10]. The transconductor was used as a switch/linear resistor. ...
... The previously mentioned op-amp based FPAA in [10] was further developed to improve the bandwidth from few M Hz to more than 10 M Hz through the use of current conveyor (CC) and programmable capacitors [27]. The CAB was made of second generation current conveyors (CCII+), OTA based resistors, and CCII+ based capacitor. ...
... Op-amp based FPAA architecture (a) FPAA architecture (b) CAB structure[10]. ...
This work focuses on reviewing the field programmable analog array (FPAA) architectures that eliminate the use of switches in signal path. The conventional FPAA architecture is composed of configurable analog blocks (CABs) connected together through switches in routing networks.The architectures covered in this survey have replaced the use of routing network by direct connection between CABs, and use of programmable analog building blocks. The first architecture covered is presented by Becker
et al.
with a hexagonal topology using operational transconductance amplifier (OTA) as a building block. The second architecture is presented by Mahmoud and Soliman, which uses the second generation current conveyor (CCII+) as a building block for their CABs arranged in a hexagonal architecture as well. Lastly, a more recent FPAA with a rectangular architecture proposed by Diab and Mahmoud is discussed, it uses the OTA as a building block for their rectangular architecture. The three FPAAs targeted continuous-time analog signal processing, having two architectures targeting high frequency applications, while the last targeting low frequency applications. The architectures, CAB structures, and the applications of each FPAA is covered separately in each section.
... Advantages of using the FPAA not only include instant prototyping but also recon®gurability, CAD compatibility, parameter programmability and testability [2]. Different FPAA design techniques have been proposed including operating MOSFETs in the subthreshold region [1,2,7], the use of MOSFET transconductors [3,4] , and the use of bipolar currentmode techniques [5,6]. Recently, switched-capacitor (SC) techniques for implementing FPAAs have been explored in research laboratories [8] and have found application in commercial products [9±12]. ...
... Circuit parameter programming is usually achieved by changing the capacitance values of the programmable capacitor arrays (PCAs), an approach that requires large area for high resolution. Despite these draw backs, SC techniques can provide high accuracy and do not require the multi-valued memories for storing circuit parameters that are usually required in FPAAs implemented using other techniques [2,4]. In this paper, a new FPAA architecture based on the SC technique that achieves high ¯exibility, area ef®cient and high speed operation is proposed. ...
... Different ®lter transfer characteristics can be programmed by loading different con®guration bits into the PCAs. Since the ®lter transfer characteristics are dependent on the capacitor ratios and clock frequency, the transfer characteristics are very accurate and do not require tuning of circuit parameters as in the case of other FPAA implementation techniques [4]. If some capacitors in the SC ®lter are larger than the value provided by a single PCA, the proposed architecture allows for the connection of a few PCAs in parallel to provide the required capacitance value. ...
A novel field-programmable analog array (FPAA) architecture based on switched-capacitor techniques is proposed. Each configurable analog block (CAB) in the proposed architecture is an opamp with feedback switches which are controlled by configuration bits. Interconnection networks are used to connect programmable capacitor arrays (PCAs) and the CABs. The routing switches in the interconnection networks not only function as interconnection elements but also switches for the charge transfer required in switched-capacitor circuits. This scheme minimizes the number of connecting switches between CABs and PCAs, thereby, it reduces the settling time of the resultant SC circuits and thus achieving high speed operation. The architecture is highly flexible and provides for the implementation of various A/D and D/A converters when the FPAA is connected with external digital circuits or field-programmable gate arrays (FPGAs).
... 3. Programmable analog neural network research has yielded several commercial programmable neural network chips and systems [48±51], along with circuit techniques, IC implementations and experimental results for programmable analog functions and interconnect, that have been valuable to the development of more general programmable analog circuits. In particular, the storage of analog circuit coef®cients on local capacitors refreshed with the results of a digital to analog conversion of the contents of digital memories [26,27], has provided means for parametric programming of analog circuits that have been used in other implementations of programmable analog circuits [52,53]. The core of the analog circuitry in one neural network processor [20] was a programmable resistor chip, containing ®ve-bit programmable resistor networks used to implement the synapses. ...
... FPAA. A MOS-Transconductor based FPAA has recently been described in the literature [8,53]. It consists of operational ampli®ers and programmable capacitors linked by a transconductor based interconnection array. ...
... opamp, MOS transconductor, capacitor, diode) emerged as a good candidate for FPAA granularity because of the high versatility of the blocks, the area ef®ciency and moderate routing resource requirements when compared to other granularity levels for implementations of the benchmark circuits. A fully functional prototype, fabricated in a 1.2 mm CMOS process, was reported in [53]. Functionality and programmability were veri®ed for the con®gurable analog blocks and interconnect, and several ...
The drive towards shorter design cycles for analog integrated circuits has given impetus to several developments in the area of Field-Programmable Analog Arrays (FPAAs). Various approaches have been taken in implementing structural and parametric programmability of analog circuits. Recent extensions of this work have married FPAAs to their digital counterparts (FPGAs) along with data conversion interfaces, to form Field-Programmable Mixed-Signal Arrays (FPMAs). This survey paper reviews work to date in the area of programmable analog and mixed-signal circuits. The body of work reviewed includes university and industrial research, commercial products and patents. A time-line of important achievements in the area is drawn, the status of various activities is summarized, and some directions for future research are suggested.
... Unfortunately, switch resistance in these devices can range from 1000 to 5000 Ω making them a limiting factor in designing large, complex FPAAs [21]. Lee and Gulak used this type of pass-transistor switch in [55,58]; however, the parasitic effects of these switches greatly limited the performance and capability of their FPAA [59]. As a result, they replaced the pass transistors with four-transistor transconductors, which increased the performance and functionality of their FPAA [56]. ...
... In addition, a transconductor switch exhibits a linear resistance, thus each switch can also be used as a variable resistor by driving the gate voltage with a multi-valued memory (or another internal or external signal). However, the large transistors needed for low-frequency operation and the addition of a multi-valued memory for each switch greatly increases the area required for the interconnects [59]. ...
... Large-scale FPAAs are feasible. While previous FPAAs have suffered from their small size and lack of functionality/generality [4,49,54,59], next-generation FPAAs based on the architecture introduced in this thesis can overcome these challenges, thereby extending the usefulness and acceptance of FPAAs. In addition, large-scale FPAA designs with computational logic included at multiple levels of granularity will address the complex design space that analog designs entail (including a wide-range of linear and non-linear functions) while keeping switch parasitics minimized. ...
Floating-gate analog circuits are being used to implement advanced signal processing functions and are very useful for process- ing analog signals prior to analog to digital conversion. We present an architecture analogous to FPGA architectures for rapid prototyping of analog signal processing systems. These systems go beyond simple pro- grammable ampliflers and fllters to include programmable and adaptive fllters, multipliers, gains, winner-take-all circuits, and matrix{array sig- nal operations. We discuss architecture as well as details such as switch- ing characteristics and interfacing to digital circuits or FPGAs.
... Lee and Gulak used this type of pass transistor switch in Lee and Gulak (1991a, 1991b); however, the parasitic effects of these switches greatly limited the performance and capability of their FPAA (Lee and Gulak, 1995). So, they replaced the pass transistors with four transistor transconductors, which increased the performance and functionality of their FPAA (Lee, 1995). The new design reduced the parasitic effects, increased the linearity, and increased the noise immunity. ...
... Unfortunately, switch resistance in these devices can be high and can vary dramatically, based on the DC bias of the signal making them a limiting factor in designing large, complex FPAAs (Edwards et al., 2000). Lee and Gulak used this type of pass transistor switch in Gulak (1991a, 1991b); however, the parasitic effects of these switches greatly limited the performance and capability of their FPAA (Lee and Gulak, 1995). So, they replaced the pass transistors with four transistor transconductors, which increased the performance and functionality of their FPAA (). ...
... In addition, a transconductor switch exhibits a linear resistance, so each switch can also be used as a variable resistor by driving the gate voltage with a multivalued memory (or other internal or external signal). However, the large transistors needed for low frequency operation and the addition of a multivalued memory for each switch greatly increases the area required for the interconnects (Lee and Gulak, 1995). Other switch designs have been proposed as well. ...
Field-programmable analog arrays (FPAAs) provide a method for rapidly prototyping analog systems. While currently available FPAAs vary in architecture and interconnect design, they are often limited in size and flexibility. For FPAAs to be as useful and marketable as modern digital reconfigurable devices, new technologies must be explored to provide area efficient, accurately programmable analog circuitry that can be easily integrated into a larger digital/mixed signal system. By leveraging recent advances in floating gate transistors, a new generation of FPAAs are achievable that will dramatically advance the current state of the art in terms of size, functionality, and flexibility.
... Field programmable analog arrays (FPAA) are integrated circuit devices with a programmable platform for implementation of analog signal processing units. The general architecture is based on configurable analog blocks (CABs) that are arranged in certain structures with interconnections between them [1]. Different FPAA architectures were proposed over the years owing to the various analog blocks available for use in the CAB. ...
... Based on the application and the specifications of the FPAA, multiple designs were presented and developed. Some designs were based on the current conveyor (CC) as the active block for the CAB [2][3][4][5], operational amplifiers (op-amps) [1,[6][7][8][9],current feedback operational amplifiers (CFOAs) [10]. and operational transconductance amplifiers (OTAs) [11][12][13][14][15][16]. ...
This study presents a new architecture for a field programmable analog array (FPAA) for use in low‐frequency applications, and a generalized circuit realization method for the implementation of nth‐order elliptic filters. The proposed designs of both the FPAA and elliptic filters are based on the operational transconductance amplifier (OTA) used in implementing OTA‐C filters for biopotential signal processing. The proposed FPAA architecture has a flexible, expandable structure with direct connections between configurable analog blocks (CABs) that eliminates the use of switches. The generalized elliptic filter circuit realization provides a simplified, direct synthetic method for an OTA‐C symmetric balanced structure for even/odd‐nth‐order low‐pass filters (LPFs) and notch filters with minimum number of components, using grounded capacitors. The filters are mapped on the FPAA, and both architectures are validated with simulations in LTspice using 90‐nm complementary metal‐oxide semiconductor (CMOS) technology. Both proposed FPAA and filters generalized synthetic method achieve simple, flexible, low‐power designs for implementation of biopotential signal processing systems.
... During the past decade, a great number of studies on continuous-time FPAAs have been reported. Lee and Gulak describe the basic idea of FPAAs [15] where CABs, capacitors, and resistors can be connected by a routing network in 1991. In 2002, a FPAA designed using chessboard layout was presented by Pankiewicz et al. [16]. ...
... The complete CDTA circuit is shown in Fig. 4. The CDTA is designed such that all PMOS transistors only serve as current sources so that the signal has an all NMOS The current differencing circuit is formed by NMOS transistors MN 1 -MN 15 [44]. Since the drain electrodes of NMOS transistors MN 1 , MN 2 and MN 6 are biased by the same current source I B , the voltage of two current input node p and n are forced to track the grounded source electrode of MN 1 , and then the input terminal can be considered as the virtual ground. ...
In this paper, a NMOS-based wideband low power and linear tunable transconductance current differencing transconductance amplifier (CDTA) is presented. Based on the NMOS CDTA, a novel simple and easily reconfigurable configurable analogue block (CAB) is designed. Moreover, using the novel CAB, a simple and versatile butterfly-shaped FPAA structure is introduced. The FPAA consists of six identical CABs, and it could realize six order current-mode low pass filter, second order current-mode universal filter, current-mode quadrature oscillator, current-mode multi-phase oscillator and current-mode multiplier for analog signal processing. The Cadence IC Design Tools 5.1.41 post-layout simulation and measurement results are included to confirm the theory.
... The motivation for significant research in the design of power efficient signal processing systems has stemmed from the growing demand for complex information processing on portable devices.To retain such rapid-prototyping capability and flexibility of FPGAs, previous commercial and academic efforts focused on an analog counterpart of the FPGA, namely field programmable analog arrays (FPAAs)[7]. Typical building blocks in an FPAA range from analog macros, such as switched capacitor circuits[8],[9], operational amplifiers and transconductance amplifiers[10],[11], to mega-modules like ADCs, DACs, track and hold circuits[2]. In certain applications, floating-gate transistors were used as reconfiguration switches for the FPAA[12]–[14]. ...
... However, limited by the type and number of these primitives, FPAAs still do not have sufficient functionality and versatility for large-scale analog applications. Their performance is further degraded by low implementation density and high interconnect parasitics[10],[11],[14],[15]. In this paper, a technique for transistor-level programmable analog design, named Programmable ANalog Device Array (PANDA) is proposed[16]. ...
Reconfigurable analog/mixed signal (AMS) platforms in scaled CMOS technology nodes are gaining importance due to the increased design cost, effort and shrinking time-to-market. Similar to field programmable gate arrays (FPGA) for digital designs, a Programmable ANalog Device Array (PANDA) provides a flexible and versatile solution with transistor-level granularity and reconfiguration capability for rapid prototyping and validation of analog circuits. This paper presents design and synthesis methodology of a PANDA design on 65 nm CMOS technology, consisting of a 24 × 25 cell array, reconfigurable interconnect, configuration memory and serial programming interface. To implement AMS circuits on the PANDA platform, this paper further proposes a CAD tool for technology mapping, placement, routing and configuration bit-stream generation. Several representative building blocks of AMS circuits, such as amplifiers, voltage and current references, filters, are successfully implemented on the PANDA platform. Dynamic reconfiguration capability of PANDA is demonstrated through input offset cancellation of an operational amplifier using an FPGA in a closed loop. Initial measurement results of PANDA implemented circuits demonstrate the potential of the methodology for rapid prototyping and hardware validation of analog circuits.
... In general, an FPAA is a monolithic collection of configurable analog building blocks (i.e., CABs), a programmable routing network used for passing signals between CABs, and a block of memory (for SRAM based FPAA) storing configuration data [2]. Alternatively, the circuit topologies may be defined by other methods such as antifuse technologies. ...
... This has been the motivation for research in the area of Field Programmable Analog Arrays [1]. In general, an FPAA is a monolithic collection of configurable analog building blocks (i.e., CABs), a programmable routing network used for passing signals between CABs, and a block of memory (for SRAM based FPAA) storing configuration data [2]. Alternatively, the circuit topologies may be defined by other methods such as antifuse technologies. ...
This paper presents the design of a high performance, radiation hard Laser Programmable Analog Array (LPAA) using LaserLink's MakeLink™ technology. Radiation hardness is achieved through the use of an advanced Silicon-on-Sapphire (SOS) fabrication process. The programming of the analog array is achieved through the use of laser via formation, which has extremely low resistance, negligible capacitance and full compatibility with commercial CMOS processes. The proposed LPAA consists of a 4 x 2 array of Configurable Analog Blocks (CABs) surrounded by abundant interconnect resources. There are 12 PAD groups around the chip, and 8 tracks per X/Y channel. Each CAB has 4 input and 4 output pins with internal circuit operating in fully differential mode. The high performance amplifier provides a usable bandwidth of 12MHz. With appropriate programming, the LPAA can provide an accurate, low-cost and rapid-prototyping analog ASIC solution.
... To date, general purpose FPAAs have tackled these problems using transconductor[3, 4] or switched-capacitor techniques[5, 6]. This paper describes a routing method that achieves wide bandwidth due to continuous-time operation. ...
... Therefore this design method takes advantage of the matching devices available in IC technology. The transconductor approach[4, 8] is a continuous time one and the transconductor is part of the transfer function. As such, there is no loss due to Ron but the voltage range is limited by transconductor linearity while the overall transfer function depends on active device transconductance and passive device impedance, the product of which is unlikely to be controlled in a given process or environment. ...
A circuit design for a Field Programmable Analog Array is presented which improves accuracy and repeatability compared to previous designs. Controlled by a configuration register, continuous-time signals are routed among programmable analog blocks to imple-ment the user's chosen circuit. The configurable connections are realised by CMOS switches and a new innovation is that these are either buffered or nulled to cancel parasitic error. The function blocks are Op-Amps combined with passive networks which al-low programmable transfer functions with accuracy insensitive to variations in process parameters and environment. The intended application area is the rapid development of analog circuits which are presently prototyped by PCBs stuffed with Op-Amp and passive components. The concept has been demonstrated on a CMOS IC and the resulting performance shows the feasibility of this approach to general purpose FPAA technology.
... While every new generation of FPGAs steadily integrates more resources and raises speed, the FPAA counterpart has followed a much more irregular trajectory, despite many research efforts, due to the holistic nature of analog design. Since the first FPAAs in the early 90's123 , a number of different architectures has been proposed. Also, several commercial attempts456 took place with different degree of success–impossible to compare with FPGAs, in any case. ...
... Also, several commercial attempts456 took place with different degree of success–impossible to compare with FPGAs, in any case. In the continuous-time domain, opamp- based [7], gm − C [2, 8], current-conveyor [9] and floating-gate translinear [10] architectures have been reported. In discrete-time, proposals of switched-capacitor [3, 11, 12] and switched-current [13] devices have been developed. ...
This paper presents a CMOS reconfigurable translinear cell intended to be part of a field programmable analog array. The cell is composed of a recently developed wide dynamic range translinear element and programmable current sources, current mirrors and capacitors. An FPAA built with this cell is able to implement the most common primitives of translinear design, such as, multiplication, division and log-domain filtering. An application example, consisting in a two quadrant multiplier, is presented in this paper.
... However, transistor-based switches with small-footprint (i.e. small channel width and length), including CMOS transmission gates [20], transconductors [22] and current conveyors [23], show typically a relatively high ON resistance of some tens of kΩ [10] to hundrets of kΩ and/or require a relatively large chip area to increase the channel width [18]. For example, Z. Chen et al. report on small ON resistances of only 150 Ω [15]. ...
A novel concept for programmable mixed-signal circuits is presented based on programmable transmission gates. For implementation, memristively switching devices are suggested as the most promising candidates for realization of fast and small-footprint signal routing switches with small resistance and capacity. As a proof-of-concept, LT Spice simulations of digital and analogue example circuits implemented by the new concept are demonstrated. It is discussed how important design parameters can be tuned in the circuity. Compared to competing technologies such as Field Programmable Analogue Arrays or Application-Specific Integrated Circuits, the presented concept allows for development of ultra-flexible, reconfigurable, and cheap embedded mixed-signal circuits for applications where only limited space is available or high bandwidth is required.
... However, transistor-based switches with small-footprint (i.e. small channel width and length), including CMOS transmission gates [20], transconductors [22] and current conveyors [23], show typically a relatively high ON resistance of some tens of kΩ [10] to hundrets of kΩ and/or require a relatively large chip area to increase the channel width [18]. For example, Z. Chen et al. report on small ON resistances of only 150 Ω [15]. ...
A novel concept for programmable mixed-signal circuits is presented based on programmable transmission gates. For implementation, memristively switching devices are suggested as the most promising candidates for realization of fast and small-footprint signal routing switches with small resistance and capacity. As a proof-of-concept, LT Spice simulations of digital and analogue example circuits implemented by the new concept are demonstrated. It is discussed how important design parameters can be tuned in the circuity. Compared to competing technologies such as Field Programmable Analogue Arrays or Application-Specific Integrated Circuits, the presented concept allows for development of ultra-flexible, reconfigurable, and cheap embedded mixed-signal circuits for applications where only limited space is available or high bandwidth is required.
... Two distinct approaches can be found in the history of the field. The first one relates to fault-tolerance and circuit creation or synthesis in the widest sense and is primarily pursued in the fields of Evolvable Hardware and Evolutionary Electronics based on reconfigurable analog arrays, predominantly on transistor level granularity [40][41][42][43][44][45][46][47][48], combined with algorithms of evolutionary optimization to configure and reconfigure the degrees of freedom of the given hardware for continued goal or specification fulfillment [19,20,[49][50][51][52][53][54][55][56][57][58][59][60][61][62][63][64]. These approaches allow both the compensation of static instance issues, e.g., defects and mismatch from manufacturing, as well as dynamic compensation of temporal phenomena such as drift, aging, or damage of defect suffered in electronics' service time. ...
The ongoing vivid advance in integration technologies is giving leverage both to computing systems as well as to sensors and sensor systems. Both conventional computing systems as well as innovative computing systems, e.g., following bio-inspiration from nervous systems or neural networks, require efficient interfacing to an increasing diversity of sensors under the constraints of metrology. The realization of sufficiently accurate, robust, and flexible analog front-ends (AFE) is decisive for the overall application system and quality and requires substantial design expertise both for cells in System-on-Chip (SoC) or chips in System-in-Package (SiP) realizations. Adding robustness and flexibility to sensory systems, e.g., for Industry 4.0., by self-X or self-* features, e.g., self-monitoring, -trimming, or -healing (AFEX) approaches the capabilities met in living beings and is pursued in our research. This paper summarizes on two chips, denoted as Universal-Sensor-Interface-with-self-X-properties (USIX) based on amplitude representation and reports on recently identified challenges and corresponding advanced solutions, e.g., on circuit assessment as well as observer robustness for classic amplitude-based AFE, and transition activities to spike domain representation spiking-analog-front-ends with self-X properties (SAFEX) based on adaptive spiking electronics as the next evolutionary step in AFE development. Key cells for AFEX and SAFEX have been designed in XFAB xh035 CMOS technology and have been subject to extrinsic optimization and/or adaptation. The submitted chip features 62,921 transistors, a total area of 10.89 mm2 (74% analog, 26% digital), and 66 bytes of the configuration memory. The prepared demonstrator will allow intrinsic optimization and/or adaptation for the developed technology agnostic concepts and chip instances. In future work, confirmed cells will be moved to complete versatile and robust AFEs, which can serve both for conventional as well as innovative computing systems, e.g., spiking neurocomputers, as well as to leading-edge technologies to serve in SOCs.
... The FPAA was introduced in 1991 by Lee and Gulak [8]. The idea was further enhanced by the same authors in 1992 [9] and 1995 [10] where op-amps, capacitors, and resistors could be connected to form a biquad filter, for example. In 1995, a similar idea, the electronically-programmable analogue circuit (EPAC) was presented in [17]. ...
This paper re-appraises the role of analogue computers within electronic and computer music and provides some pointers to future areas of research. It begins by introducing the idea of analogue computing and placing in the context of sound and music applications. This is followed by a brief examination of the classic constituents of an analogue computer, contrasting these with the typical modular voltage-controlled synthesiser. Two examples are presented, leading to a discussion on some parallels between these two technologies. This is followed by an examination of the current state-of-the-art in analogue computation and its prospects for applications in computer and electronic music.
... In electronics, this concept is sustained by Field Programmable Gate Arrays (FPGAs) [11,12] and Field Programmable Analog Arrays (FPAAs) [13][14][15][16] and following a similar rationale behind the principles of these devices we propose here the implementation of a similar concept in integrated photonics, that can be realized by combining a set of Programmable Photonics Analog Blocks (PPABs) and a set of Reconfigurable Photonic Interconnects (RPIs) implemented over a photonic chip. This element, which we call Field Programmable Photonic Array (FPPA), can be able of implementing one or various simultaneous photonics circuits and/or linear multiport transformations by the appropriate programming of its resources (i.e. ...
We propose a new programmable integrated photonic device, the Field Programmable Photonic Array, which follows a similar rationale as that of Field Programmable Gate Arrays and Field Programmable Analog Arrays in electronics. This high-level concept, basic photonic building blocks, design principles, and technology and physical implementation are discussed. Experimental evidence of its feasibility is also provided.
... Digital Object Identifier 10.1109/TCSI.2010.2071950 power consumption, an analog counterpart of the FPGA, namely a field-programmable analog array (FPAA), was proposed in [3], followed by several different FPAA realizations using a switched capacitor [4], [5], a transconductor [6], or an operational transconductance amplifier (OTA) with a capacitor [7]. The early FPAAs, however, contained only a few computational elements, and their applications were restricted to analog filters, until floating-gate transistors were used as switches of the FPAA to enable large-scale analog circuit design [2], [8]. ...
... Previous academic and industrial efforts focused on field programmable analog arrays (FPAA) with a wide range of configurable analog blocks (CAB) ranging from coarse grained macros such as operational amplifiers [1], operational transconductance amplifiers [2]- [4], switched capacitor circuits [5], ADCs and DACs [6] to medium grained primitives such as differential pairs and transconductors [7], [8]. FPAAs with transistor-level CABs known as field programmable transistors arrays (FPTAs) are explored in [9], [10] for evolvable hardware applications. ...
The design and development of analog/mixed-signal (AMS) integrated circuits (ICs) is becoming increasingly expensive, complex, and lengthy. Rapid prototyping and emulation of analog ICs will be significant in the design and testing of complex analog systems. A new approach, Programmable ANalog Device Array (PANDA) that maps any AMS design problem to a transistor-level programmable hardware, is proposed. This approach enables fast system level validation and a reduction in post-silicon bugs, minimizing design risk and cost. The unique features of the approach include: 1) transistor-level programmability that emulates each transistor behavior in an analog design, achieving very fine granularity of reconfiguration; 2) programmable switches that are treated as a design component during analog transistor emulating, and optimized with the reconfiguration matrix; and 3) compensation of ac performance degradation through boosting the bias current. Based on these principles, a digitally controlled PANDA platform is designed at 45 nm node that can map AMS modules across 22-90 nm technology nodes. A systematic emulation approach to map any analog transistor to 45 nm PANDA cell is proposed, which achieves transistor level matching accuracy of less than 5% for
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. Circuit level analog metrics of a voltage-controlled oscillator (VCO) emulated by PANDA, match to those of the original designs in 22 and 90 nm nodes with less than a 5% error. Several other 90 and 22 nm analog blocks are successfully emulated by the 45 nm PANDA platform, including a folded-cascode operational amplifier and a sample-and-hold module (S/H).
... Digital Object Identifier 10.1109/TCSI.2010.2071950 power consumption, an analog counterpart of the FPGA, namely a field-programmable analog array (FPAA), was proposed in [3], followed by several different FPAA realizations using a switched capacitor [4], [5], a transconductor [6], or an operational transconductance amplifier (OTA) with a capacitor [7]. The early FPAAs, however, contained only a few computational elements, and their applications were restricted to analog filters, until floating-gate transistors were used as switches of the FPAA to enable large-scale analog circuit design [2], [8]. ...
The modulation and demodulation blocks in an orthogonal frequency-division multiplexing (OFDM) system are typically implemented digitally using a fast Fourier transform circuit. We propose an analog implementation of an OFDM demodulator as a means for reducing power consumption. The proposed receiver implements the discrete Fourier transform (DFT) as a vector-matrix multiplier using floating-gate transistors on a field-programmable analog array (FPAA). The DFT coefficients can be tuned to counteract an inherent device mismatch by adjusting the amount of electrical charge stored in the floating-gate transistors. When compared to a digital field-programmable gate array implementation, the analog FPAA implementation of the DFT reduces power consumption at the cost of a slight performance degradation. Considering the errors in the DFT coefficients as intersymbol interference, the performance degradation can be further mitigated by employing a least mean-square or minimum mean-square-error equalizer.
... FPAAs basically consist of an array of configurable analog blocks and they can be classified in several types depending on their operation mode, being either continuous-time or discretetime and either voltage-mode or current-mode. Continuoustime devices can be implemented by means of translinear elements [1, 2], transconductors [3], current integrators [4] or current conveyors [5], while discrete-time implementations may use switched capacitor topologies [6, 7] or switched current circuits. The FPAAs can be configured for applications such as filtering [8], neural networks [9] , industrial con- trol [10], signal processing [11], V-F converters and aerospace communications [12], among others. ...
In this paper, the implementation of signal processing circuits on a novel translinear Field-Programmable Analog Array (FPAA) testchip is reported. The FPAA testchip is based on a 0.35-micron, fully CMOS translinear element, which is the core block of a reconfigurable analog cell. The FPAA embeds a 5 Ã 5 cell array. As implementation examples, a four-quadrant multiplier with five decade dynamic range and a programmable fourth-order low-pass filter with up to 7 MHz bandwidth have been mapped on the translinear FPAA. 14 cells have been used for the four-quadrant multiplier while 18 cells were needed for the fourth-order low-pass filter.
... The arrays of analog circuits on which the FPAAs are based consist of matrix/vector multiplies, filtering, and so forth-not just a few op-amps with passive elements as with commercial and other research FPAAs [13,14,15,16,17,18,19]. Relative to custom-designed analog circuits, a design implemented in an FPAA will always result in higher parasitics as well as increased die area for a given design; therefore, the design will always possess some inefficiencies. ...
Machine perception is a difficult problem both from a practical or implementation point of view as well as from a theoretical or algorithmic point of view. Machine perception systems based on biological perception systems show great promise in many areas but they often have processing requirements and/or data flow requirements that are difficult to implement, especially in small or low-power systems. We propose a system design approach that makes it possible to implement complex functionality using cooperative analog-digital signal processing to lower power requirements dramatically over digital-only systems, as well as provide an architecture facilitating the development of biologically motivated perception systems. We show the architecture and application development approach. We also present several reference systems for speech recognition, noise suppression, and audio classification.
... This architecture was capable of storing circuit parameters in multi-valued memories as well. These research efforts produced further results as a MOS transconductor-based FPAA [21, 22] enabled by the programmable resistors used in the reconfigurable interconnect circuitry. These programmable resistors are essentially matched MOS transistors that are cross-coupled to eliminate the non-linear components in differential signals [23]. ...
Field-programmable analog arrays (FPAA) are integrated circuits with a collection of analog building blocks connected through a wire and switch fabric to achieve reconfigurability similar to the FPGAs of the digital domain. Like FPGAs, FPAAs can help reduce the time and money costs of the integrated circuit design cycle and make analog design much easier. In recent years, several types of FPAAs have been developed. Among these, FPAAs that use floating-gate transistors as programming elements have shown great potential in scalability because of the simplicity they provide in configuring the chip. Existing tools for programming FPAAs tend to be device specific and aimed at specific tasks such as filter design. To move FPAAs to the next step, more powerful and generic placement and routing tools are necessary. This thesis presents a placement and routing tool for large-scale floating-gate-based FPAAs. A topology independent routing resource graph (RRG) was used to model the FPAA routing topology, which enables generic description of any FPAA architecture with arbitrary connectivity including possible FPGA support in the future as well. So far, different FPAA architectures have been specified and routed successfully. The tool is already in use in classes and workshops for analog circuit and system design. Efficient ways to describe circuits and user constraints were developed to allow easy integration with other tools. Analog circuit performance was optimized by taking into account the routing parasitic effects on interconnects under various device-related constraints. Parasitic modeling allows simulation and evaluation of circuits routed on FPAA. Finally, a methodology was developed to explore the optimum architecture for a set of circuit classes by evaluating the efficiency of different architectures for each circuit class.
... Figure 2.2 Réseau d'interconnexions avec des résistances programmables (Lee et Gulak, 1995).... ...
"Mémoire présenté en vue de l'obtention du diplôme de maîtrise ès sciences appliquées (génie électrique)" Thèse (M. Sc. A.)--École polytechnique, 2006.
... On the other end of the granularity spectrum are Field Programmable Transistor Arrays (FPTAs) which use transistors that must be connected together with switches to realize the user's circuit [3]. In addition there are FPAAs that are built using only gm-C filters [4, 5] , opamps and passive compo- nents [6], and transconductors [7]. There are also FPAAs that try to solve this problem by using a mixture of analog blocks to realize circuits. ...
While the development of reconfigurable analog platforms is a blossoming field, the tradeoff between usability and flexibility continues to be a major barrier. Field Programmable Analog Arrays (FPAAs) built with translinear elements offer a promising solution to this problem. These FPAAs can be built to use previously developed synthesis procedures for translinear circuits. Furthermore, large-scale translinear FPAAs can be built using floating-gate transistors as both the computational elements and the reconfigurable interconnect network. Two FPAAs, built using Multiple Input Translinear Elements (MITEs), have been designed, fabricated, and tested. These devices have been programmed to implement various circuits including multipliers, squaring circuits, current splitters, and filters. In addition, synthesis, place-and-route, and programming tools have been created in order to implement a reconfigurable system where the circuits implemented are described only by equations. Supporting circuitry for interfacing with current-mode, translinear FPAAs has also been developed. This circuitry included a voltage-to-current converter, a current-to-voltage converter, and a pipelined analog-to-digital converter. The continued development of translinear FPAAs will lead to a reconfigurable analog system that allows for a large portion of the design to be abstracted away from the user. Ph.D. Committee Chair: Hasler, Paul; Committee Member: Anderson, David; Committee Member: Ghovanloo, Maysam; Committee Member: Hamblen, James; Committee Member: Minch, Bradley
... FPAAs are most commonly use MOS transistor switches driven by digital memory[14]. Alternatives to pass-FETs include G m -C amplifiers, 4-transistor transconductors, and current conveyors[13][20][2]. All of the listed alternatives trade area for improved switch characteristics, and still require physical memory for maintaining connectivity. ...
Floating-gate transistors similar to those used in FLASH and EEPROM can be used to build reconfigurable analog arrays. The charge on the floating gate can be modified to pass or block a signal in a cross-bar switch matrix, or it can be finely tuned to eliminate a threshold difference across a chip or set a bias. By using such a compact and versatile reconfigurable analog memory element, the number of analog circuit components included on an integrated circuit that is field-programmable is significantly higher. As a result, large-scale FPAAs can be built with the same impact on analog design that FPGAs have had on digital design. In my research, I investigate the areas floating-gate transistors can be used to impact FPAA design and implementation. An FPAA can be broken up into two basic components, elements of connection and elements of computation. With respect to connection, I show that a floating-gate switch can be used in a cross-bar matrix in place of a transmission gate resulting in less parasitic capacitance and a more linear resistance for the same size transistor. I illuminate the programming issues relating to injecting a floating-gate for use as a switch, including the drain selection circuitry and rogue injection due to gate induced drain leakage. With respect to computation, I explain how a Multiple-Input Translinear Element, or MITE, can be augmented to fit in an FPAA framework. I also discuss two different MITE implementations compatible with CMOS technology, a subthreshold MOS design and a BJT MITE that uses a lateral BJT. Beyond FPAA components, I present two alternative FPAA systems. The first is a general purpose reconfigurable analog system that uses standard analog design components that have been augmented with floating-gates. The second FPAA is built upon MITE circuits, and is focused on supporting direct system synthesis. I conclude with a discussion of a future large-scale MITE FPAA. M.S. Committee Chair: Hasler, Paul; Committee Member: Anderson, Dave; Committee Member: Ayazi, Farrokh
This work focuses on proposing FPAA architecture based on operational transconductance amplifier (OTA) as the basic block for low frequency continuous time signal processing. Two FPAA architectures are presented after a step by step development of the design structure. The architectures eliminate the use of switches for signal routing, instead they allow reconfigurability using a selecting network composed of OTAs. The proposed architectures demonstrate flexibility in architecture allowing the expansion of the basic structure. Both architectures allow the implementation of individual independent circuits with an option of cascading if required. Multiple filter circuits can be mapped on the FPAA with independent control and reconfigurability of gain, bandwidth, and notch frequency, thus allowing the use of the FPAA as a filter bank. As for the provided cascading feature, it allows the implementation of a system or a set of cascaded filters as desired by designer. Validation of proposed FPAA architecture and its characteristics is examined through simulation on LTspice using 90 nm CMOS technology with supply voltage of ± 0.6 V. A single 4th-order lowpass filter is implemented first and then a combination of amplifier, notch filter and lowpass filter is implemented. Simulation results of the filters on proposed FPAA is compared to results acquired from simulation of the circuits alone (off-FPAA) showing excellent agreement between both results, hence confirming the proposed FPAA architecture.
Programmable integrated photonics is an emerging new paradigm that aims at designing common integrated optical hardware resource configurations, capable of implementing an unconstrained variety of functionalities by suitable programming, following a parallel but not identical path to that of integrated electronics in the past two decades of the last century. Programmable integrated photonics is raising considerable interest, as it is driven by the surge of a considerable number of new applications in the fields of telecommunications, quantum information processing, sensing, and neurophotonics, calling for flexible, reconfigurable, low-cost, compact, and low-power-consuming devices that can cooperate with integrated electronic devices to overcome the limitation expected by the demise of Moore’s Law. Integrated photonic devices exploiting full programmability are expected to scale from application-specific photonic chips (featuring a relatively low number of functionalities) up to very complex application-agnostic complex subsystems much in the same way as field programmable gate arrays and microprocessors operate in electronics. Two main differences need to be considered. First, as opposed to integrated electronics, programmable integrated photonics will carry analog operations over the signals to be processed. Second, the scale of integration density will be several orders of magnitude smaller due to the physical limitations imposed by the wavelength ratio of electrons and light wave photons. The success of programmable integrated photonics will depend on leveraging the properties of integrated photonic devices and, in particular, on research into suitable interconnection hardware architectures that can offer a very high spatial regularity as well as the possibility of independently setting (with a very low power consumption) the interconnection state of each connecting element. Integrated multiport interferometers and waveguide meshes provide regular and periodic geometries, formed by replicating unit elements and cells, respectively. In the case of waveguide meshes, the cells can take the form of a square, hexagon, or triangle, among other configurations. Each side of the cell is formed by two integrated waveguides connected by means of a Mach–Zehnder interferometer or a tunable directional coupler that can be operated by means of an output control signal as a crossbar switch or as a variable coupler with independent power division ratio and phase shift. In this paper, we provide the basic foundations and principles behind the construction of these complex programmable circuits. We also review some practical aspects that limit the programming and scalability of programmable integrated photonics and provide an overview of some of the most salient applications demonstrated so far.
This work presents a reconfigurable mixed-signal system-on-chip (SoC), which integrates switched-capacitor-based field programmable analog arrays (FPAA), analog-to-digital converter (ADC), digital-to-analog converter, digital down converter , digital up converter, 32-bit reduced instruction-set computer central processing unit (CPU) and other digital IPs on a single chip with 0.18 μm CMOS technology. The FPAA intellectual property could be reconfigured as different function circuits, such as gain amplifier, divider, sine generator, and so on. This single-chip integrated mixed-signal system is a complete modern signal processing system, occupying a die area of 7 × 8 mm ² and consuming 719 mW with a clock frequency of 150 MHz for CPU and 200 MHz for ADC/DAC. This SoC chip can help customers to shorten design cycles, save board area, reduce the system power consumption and depress the system integration risk, which would afford a big prospect of application for wireless communication.
Layout for analog circuits has historically been a time-consuming, manual, trial-and-error task. The problem is not so much the size (in terms of the number of active devices) of these designs, but rather the plethora of possible circuit and device interactions: from the chip substrate, from the devices and interconnects themselves, and from the chip package. In this short survey, we enumerate briefly the basic problems faced by those who need to do layout for analog and mixed-signal designs, and survey the evolution of the design tools and geometric/electrical optimization algorithms that have been directed at these problems.
We present a large-scale field programmable analog array that enables floating-gate (FG) adaptive circuits using FG-based switch technology. We present a novel architecture technology that enables switch routing with FG elements for signals resulting from high voltage adapting FG elements. We present careful analysis and characterization of the FG structure, including programming ranges, electron tunneling paths, to show the indirect programming structure involving an nFET device can handle the signals. We present the experimental data (350-nm commercial CMOS process) for a single-transistor adaptive structure, for a compiled autozeroing amplifier, and for multiple adaptive FG circuits.
form only given. Field-programmable analog arrays (FPAAs) provide a method for rapidly prototyping analog systems. Currently available commercial and academic FPAAs are typically based on operational amplifiers (or other similar analog primitives) with only a few computational elements per chip. While their specific architectures vary, their small sizes and often restrictive interconnect designs leave current FPAAs limited in functionality, flexibility, and usefulness. We explore the use of floating-gate devices as the core programmable element in a large-scale FPAA with applications in signal processing emphasized. An FPAA architecture is presented that offers increased functionality and flexibility in realizing analog signal processing systems, and experimental data from a testbed FPAA is shown. In addition, mainstream signal processing systems are discussed that can be effectively implemented on large-scale reconfigurable analog devices thereby realizing dramatic savings in power over traditional digital solutions and improved time-to-market over traditional analog designs.
We present the field programmable array of analog and digital devices (FPAADD) as a novel implementation of a field programmable mixed-signal array (FPMA). The FPAADD is a hybrid combination of a field programmable analog array (FPAA) and a field programmable gate array (FPGA). Unlike other FPMAs where the FPGA and FPAA portions are kept separate, this architecture closely integrates the two in a fine-grained interleaved array. Instead of using hard-coded data converters, the FPAADD synthesizes data converters out of its reconfigurable fabric. The analog and digital portions share a common global interconnect. Floating gate (FG) transistors are used as the switch and memory elements of the chip, providing better switch performance and power over traditional static random-access memory-based approaches. The precise programmability of the FG switches also allows for computation to take place in the interconnect. These key differences make the FPAADD much more general purpose than previous FPMA architectures. The FPAADD consists of 27 × 8 array of 108 digital and 108 analog tiles and peripheral circuitry on 5 × 5 mm2 die fabricated in a 0.35- μm CMOS process, and contains more than 130 000 FG transistors.
Field programmable analogue array (FPAA) technologies can offer an analogue platform for a vast number of applications, including communication circuits requiring adaptive processing. The subject of this paper deals with the problem of generating and processing of base-band communication signals using a reconfigurable platform based on FPAA technology. In the experiments it was used AN221E04 circuit included in Anadigmvortex-AN221K04 development board and connected to PC through a serial interface. Also it was used the software tools from AnadigmDesignerreg2 that allows complex circuits to be designed with a simple drag-and-drop graphical interface. Especially analog modulators and demodulator were implemented, but the capabilities of the circuits offer great possibilities for more elaborated modulation schemes.
This paper presents a variety of applications of an FPAA based on a regular pattern of signal-processing cells and primarily local signal interconnections. Despite the limitations introduced by local interconnections, the presented architecture accommodates a wide variety of linear and nonlinear circuits found in many signal processing systems. Thus it effectively proves that it is possible to improve the performance of an FPAA by means of constraining the interconnection pattern, without significantly limiting the class of circuits it can implement.
This paper presents a new approach to develop Field Programmable Analog Arrays (FPAAs),1 which avoids excessive number of programming elements in the signal path, thus enhancing the performance. The paper also introduces a novel FPAA architecture, devoid of the conventional switching and connection modules. The proposed FPAA is based on simple current mode sub-circuits. An uncompounded methodology has been employed for the programming of the Configurable Analog Cell (CAC). Current mode approach has enabled the operation of the FPAA presented here, over almost three decades of frequency range. We have demonstrated the feasibility of the FPAA by implementing some signal processing functions.
The design of a high-frequency field-programmable analog array (FPAA) is presented. The FPAA is based on a regular pattern of cells interconnected locally for high frequency performance. No switches of any kind are used in the signal path of a cell: programming of the functions, parameters, and interconnections is achieved solely by modifying cells'' bias conditions digitally. Limited global signal interconnections are also available for those application circuits which cannot be mapped onto locally-only interconnected structure. Key circuits of the FPAA have been fabricated in a CPI transistor-array bipolar technology.
An approach for designing a Field Programmable Analog Array (FPAA) is described. The analog array is based on current conveyors and benefits from two major interests: a large bandwidth and a low number of discrete components needed for the implementation of analog functions. An Analog Elementary Cell (AEC), based on current conveyors has been developed, and it is associated with programmable resistors and capacitors. Analog functions can be performed programming several AECs as current-mode amplifiers, analog multipliers, etc. The main purpose of this paper is to introduce current conveyor based analog blocks which are very-well suited for the implementation of FPAA. A particular interconnection architecture is addressed using current conveyors as switches. The major key feature of the proposed approach is that current conveyors are used as active elements and switching elements. A new topology based on the developed AEC is proposed and should be shortly validated.
While the development of reconfigurable analog platforms is a blossoming field, the tradeoff between usability and flexibility continues to be a major barrier. Field Programmable Analog Arrays (FPAAs) built with translinear elements offer a promising solution to this problem. These FPAAs can be built to use previously developed synthesis procedures for translinear circuits. Furthermore, large-scale translinear FPAAs can be built using floating-gate transistors as both the computational elements and the reconfigurable interconnect network. An FPAA built using Multiple Input Translinear Elements (MITEs) has been designed, fabricated in 0.35 μ m CMOS, and tested. These devices have been programmed to implement various circuits including multipliers, squaring circuits, RMS-to-DC converters, and filters. In addition, synthesis, place-and-route, and programming tools have been created in order to implement a reconfigurable system where the circuits implemented are described only by equations. The continued development of translinear FPAAs will lead to a reconfigurable analog system that allows for a large portion of the design to be abstracted away from the user.
A BiCMOS field programmable analog cell array with continuous time fully differential analog signal processing is presented. As a counterpart to digital FPGAs it can be configured by software and enables fast prototyping and evaluation of analog and mixed signal systems with frequencies up to 100kHz. The device offers different I/O-cells and in the analog core several flexible analog cells including a novel multiplier/amplifier/integrator cell. Measurements on design examples realized with a test version show excellent performance. The influence of the switching arrays in the signal path is neglible.
The reconfigurable analog signal processor (RASP), one of the first large-scale field-programmable analog arrays (FPAAs), is composed of 56 computational analog blocks (CABs). Each CAB contains various levels of analog computational granularity utilizing over 50,000 programmable analog elements. Bias currents are programmable to within 0.2% from 100 pA to greater than 3 muA. Internal bandwidths are greater than 50 MHz, and the kT/C noise can be adjusted using the drawn capacitances and routing network parasitics. A range of compiled circuits and resulting signal processing systems are presented
We present a viewpoint showing that analog signal processing approaches are becoming configurable and programmable like their digital counterparts, while retaining a huge computational efficiency, for a given power budget, compared to their digital counterparts. We present recent results in programmable and configurable analog signal processing describing the widespread potential of these approaches. We discuss issues with configurable systems, including size, power, and computational tradeoffs, as well as address the computational efficiency of these approaches. Analog circuits and systems research and education can significantly benefit from the computational flexibility provided by large-scale FPAAs. The component density of these devices is sufficient to synthesize large systems in a short period of time. However, this level of reconfigurable and programmable complexity requires a development platform and CAD tools to demonstrate the capabilities of large-scale FPAAs before they will be widely accepted. To address this need, a self-contained FPAA setup has been developed along with an integrated software design flow. With only an Ethernet connection and an AC power outlet, a researcher or student can explore the numerous analog circuit possibilities provided by large-scale FPAAs.
A field-programmable analog array (FPAA) using a standard-CMOS wide-dynamic-range translinear element (TE) is introduced. The FPAA configurable analog blocks (CABs) are based on a reconfigurable translinear cell (RTC), capable of implementing the basic circuit elements required by translinear and log-domain circuit design. The interfacing is provided by an I/O programmable cell, which allows for easier connectivity between the signal-processing core and the external circuitry. As a proof-of-concept, a 5 $\times$ 5 RTC FPAA testchip was implemented in 0.35- $\mu{\hbox {m}}$ CMOS technology. A set of various circuit primitives, such as one- and four-quadrant multipliers, an Euclidean distance operator and a fourth-order log-domain filter, were mapped on the chip in order to demonstrate the versatility of the approach. FPAA bandwidth reaches 20 MHz with a power consumption of 30 $\mu\hbox{W/TE}$ and precision errors below 3%.
This paper is a tutorial introduction to field-programmable analog arrays, as well as a review of existing field-programmable analog array architectures, of both educational and industrial origin. Circuit issues relevant to the development of high-bandwidt h FPAAs are presented. A current conveyor-based architecture, which promises to achieve video bandwidths, is described. Test results are presented for the CMOS current conveyor-based FPAA building block, with programmable transconductors and capacitors. Measurements indicate bandwidths in excess of 10MHz, and functionality of amplifiers, integrators, differentiators, and adders. The die area is 1.5mm x 3.5mm in a 0.8μm CMOS technology.
Large-scale reconfigurable and programmable analog devices provide a new option for prototyping and synthesizing analog circuits for analog signal processing and beyond. Field-programmable analog arrays (FPAAs) built upon floating gate transistor technologies provide the analog reconfigurability and programmability density required for large-scale devices on a single integrated circuit (IC). A wide variety of synthesized circuits, such as OTA followers, band-pass filters, and capacitively coupled summation/difference circuits, were measured to demonstrate the flexibility of FPAAs. Three generations of devices were designed and tested to verify the viability of such floating gate based large-scale FPAAs. Various architectures and circuit topologies were also designed and tested to explore the trade-offs present in reconfigurable analog systems. In addition, large-scale FPAAs have been incorporated into class laboratory exercises, which provide students with a much broader range of circuit and IC design experiences than have been previously possible. By combining reconfigurable analog technologies with an equivalent large-scale digital device, such as a field-programmable gate array (FPGA), an extremely powerful and flexible mixed signal development system can be produced that will enable all of the benefits possible through cooperative analog/digital signal processing (CADSP). David V. Anderson, Committee Member ; Dr. Paul Hasler, Committee Chair ; John B. Peatman, Committee Member ; Aaron D. Lanterman, Committee Member. Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2007.
Field-programmable analog arrays (FPAAs) provide a method for rapidly prototyping analog systems. Currently available commercial and academic FPAAs are typically based on operational amplifiers (or other similar analog primitives) with only a few computational elements per chip. While their specific architectures vary, their small sizes and often restrictive interconnect designs leave current FPAAs limited in functionality, flexibility, and usefulness. Recent advances in the area of floating-gate transistors have led to an analog technology that is very small, accurately programmable, and extremely low in power consumption. By leveraging the advantages of floating-gate devices, a large-scale FPAA is designed that dramatically advances the current state of the art in terms of size, functionality, and flexibility. A large-scale FPAA is used as part of a mixed-signal prototyping platform to demonstrate the viability and benefits of cooperative analog/digital signal processing. This work serves as a roadmap for future FPAA research. While current FPAAs can be compared with the small, relatively limited, digital, programmable logic devices (PLDs) of the 1970s and 1980s, the floating-gate FPAAs introduced here are the first step in enabling FPAAs to support large-scale, full-system prototyping of analog designs similar to modern FPGAs. Ph.D. Committee Chair: Anderson, David; Committee Member: Citrin, David; Committee Member: Hasler, Paul; Committee Member: Lanterman, Aaron; Committee Member: Prvulovic, Milos; Committee Member: Yalamanchili, Sudhakar
This book is the first unified treatment of the analysis and design methods for protection of principally electronic systems from the deleterious effects of nuclear and electro-magnetic radiation. Coverage spans from a detailed description of the nuclear radiation sources to pertinent semiconductor physics, then to hardness assurance. This work combines the disciplines of solid state physics, semiconductor physics, circuit engineering, nuclear physics, together with electronics and electromagnetic theory into a book that can be used as a text with problems at the end of the majority of the chapters. Written by veterans in the field, the most significant feature of this book is its comprehensive treatment of the phenomena involved. This treatment includes the analysis and design of the effect of nuclear radiation on electronic systems from the experimental, theoretical, and engineering viewpoints. Unique pedagogical attempts are employed to make the material more understandable from the position of an enlightened engineering and scientific readership whose task is the design and analysis of radiation hardened electronic systems.
The best way of assessing semiconductor susceptibility to Single Event Phenomena (SEP) would be to measure their response while operating in the actual space environment. However, this a very expensive way to characterise semiconductors and has only been carried out on a very limited number of device types. Generally, the space radiation environment has been simulated in the laboratory and semiconductor characterisation has been carried out using differenct test systems and operating conditions. Where orbital upset data and ground simulation data exist, large variations were often found between observed and predicted upset rates. Better Single Event Upset (SEU) data and device technology information would help improve the prediction process. Here we concentrate on the ground testing itself and only touch on the prediction versus observation of a few devices. Heavy ion and proton test facilities used by ESA will be described together with test techniques and test procedures. Examples of Californium-252, recent heavy ion and proton SEU data on memories and microprocesors will also be presented.
An area efficient and parasitic insensitive technique for the implementation of a field programmable analogue array is proposed. The connections between configurable analogue blocks are realised using MOSFET transconductors. The conductance is controlled by varying the gate voltages defined by a multivalued memory system or external/internal signals.
Four types of frequency dividers were fabricated on SIMOX/SOI
(separation by implanted oxygen/silicon on insulator) substrates. A
novel circuit among these four circuits showed the highest operation
frequency of 1.2 GHz under 1-V supply voltage, with gate lengths of 0.15
and 0.1 μm. Power consumption was no more than 50 and 62 μW for
both 0.15- and 0.1-μm gate designs, respectively
An extremely low-power CMOS/SIMOX divide-by-128/129 dual-modulus
prescaler that operates at up to 1 GHz and dissipates 0.9 mW at a supply
voltage of 1 V is presented. The prescaler is capable of 2-GHz
performance with dissipation of 7.2 mW at 2 V. This superior performance
is primarily achieved by using an advanced ultrathin-film CMOS/SIMOX
process technology combined with a circuit configuration that uses a
divide-by-2/3 synchronous counter. Using these same technologies, a
single-chip CMOS phase-locked-loop (PLL) LSI that uses the developed
prescaler was fabricated. It can operate at up to 2 GHz while
dissipating only 8.4 mW at a supply voltage of 2 V. Even at a lower
supply voltage of 1.2 V, 1-GHz operation can be obtained with a
corresponding power consumption of 1.4 mW. These results indicate that
the high-speed and very-low-power features of CMOS/SIMOX technology
could have an important impact on the development of future personal
communication systems
A monolithic high-speed sample-and-hold amplifier is described. It
minimizes the hold step via a new circuit architecture. This design
takes advantage of the speed of open-loop sample-and-hold circuits
during the sample mode and cancellation of charge injection by
duplicating and feeding it through a second amplifier during the hold
mode. The unique feature of the design is an acquisition time of 150 ns
to 0.01% of a 10-V step including the time required for all internal
nodes to settle after the hold command is given. Aperture uncertainty is
less than 20 ps and linearity is 0.003%. The device has 10-pF on-chip
hold and dummy capacitors and the die size is 8.548 mm<sup>2</sup> on a
junction-field-effect-transistor (JFET) plus complementary bipolar
process
IEEE Trans on Nucl. Sc.
- G E Davies