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Power and Noise Reduction of High Frequency Variable Gain Amplifier
Abstract
This work illustrates the design of the cell-based variable-gain amplifier (VGA) with less power consumption and improved noise margin. The variable gain amplifier is incorporated into the current wireless front-end modules. The body-bias technique in the n channel MOSFET (n-MOS) devices greatly aided in the power reduction of the cells. The device characteristics were fine-tuned to get better gain and bandwidth and reduced the supply voltage. This technique ultimately reduced the number of cell stages required to meet the expectation. The reduction of the supply voltage and the technology upscaling helped to improve the noise margin. The presented unit cell achieved accurate dB-linear characteristics across a wide tuning range, based on a unique gain control method with a combination of sub-threshold n-MOS and saturation n-MOS transistors as active loads. A 7-cell reconfigurable VGA is simulated in 0.18-[Formula: see text]m Complementary MOSFET technology to verify the concept. The simulation results showed that the bandwidth of the VGA is greater than 2.5[Formula: see text]GHz, while less than 0.78[Formula: see text]mW is consumed from a 1.5-V supply. A noise figure of 23.7[Formula: see text]dB is measured. Also, the VGA achieves a gain control range of 19[Formula: see text]dB with a gain error less than [Formula: see text][Formula: see text]dB or 26.3%. These results make the designed amplifier adequate for high-frequency applications.
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This brief proposes a two-stage cascoded CMOS LNA with common drain envelope detection based power reduction method for the 5G applications of 28 GHz frequency. Dual inductive peaking and stagger tuning techniques are involved to get a 3 dB bandwidth of 2.25 GHz from 26.75 to 29 GHz. Besides, 22 dB of gain is provided by the proposed LNA. Inductive source degeneration helps to reduce the Noise Figure (NF) of the first cascoded stage, and a 2.3 dB of NF is observed in the LNA. The primarily amplified signals from the first cascoded stage are fed to the envelope detector and the second cascoded stage. When the RF signal is received, the envelope detector output will be high, and it turns on the second cascoded stage. In the existing method, the combination of a diode-connected transistor, low pass filter and buffer has been used for the envelope detection. A common drain transistor with an active resistor and capacitor is used in the envelope detection of the proposed method. Here, the power consumption of the LNA is reduced by 25.26% at the sleep mode. The proposed LNA consumes 9.5 mW and 7.1 mW of power from a 1.5 V supply at the active state and sleep state respectively. It requires 0.1235 mm2 of core area in 90 nm technology. Moreover, the behavior of the circuit under process corner variation and temperature variation is analyzed, and Monte–Carlo analysis is performed.
This paper deals with the design and optimization of two-stage CMOS Low Noise Amplifier (LNA) for WLAN applications. IEEE 802.11n WLAN standard provides up to 600 Mbps speed with 40 MHz channel bandwidth and high throughput. The receiver of these WLAN applications requires LNA with higher gain and minimum Noise Figure (NF). Elephant Herding Optimization (EHO) technique is involved for the first time to optimize the performance of the LNA. The post-layout simulation shows, a maximum gain of 26.7 dB at 2.4 GHz is achieved in the proposed design. Feedforward noise cancelation technique is involved to get a reduced noise figure of 1.12 dB. The first and second stages are tuned to cover the 3 dB maximum gain bandwidth of 3.2 GHz (from 1.7 GHz to 4.4 GHz). This LNA is designed at 90 nm technology with the supply voltage of 0.5 V and 1.2 V, and consumes 8.9 mW of power. Current reuse technology is used to reduce the power consumption. The input and output return losses have been found as -18 dB and -15 dB respectively at the targeted 2.4 GHz frequency. Third order input intercept point (IIP3) of the optimized LNA is -8.1 dBm.
A CMOS wideband cascaded variable gain amplifier (VGA) with a temperature-independent exponential gain control characteristic is presented in this paper. The exponential gain control function is realized using parasitic bipolar transistors and a control signal converter. The bandwidth is extended using an inductive peaking technique for high-frequency operations. The gain of the VGA varies from -38.8 to 55.3 dB in relation to the control voltage that varies from 0 to 1.8 V. The bandwidth of the proposed VGA is approximately 900 MHz with a gain control range of 94.1 dB. The proposed VGA includes a dc offset cancellation loop to avoid amplification of the dc offset. The VGA is powered by 1.8 V with 11.4 mA. The VGA chip including bondpads occupies an area of 850 mum times 490 mum.
This brief presents a new channel noise model using the channel length modulation (CLM) effect to calculate the channel noise of deep submicron MOSFETs. Based on the new channel noise model, the simulated noise spectral densities of the devices fabricated in a 0.18 μm CMOS process as a function of channel length and bias condition are compared to the channel noise directly extracted from RF noise measurements. In addition, the hot electron effect and the noise contributed from the velocity saturation region are discussed.
A variable gain distributed amplifier (VGDA) for the Rx path of ultrawideband phased-array system is implemented in 90-nm CMOS process and presented in this letter. In order to achieve high gain and wideband with relative low dc power dissipation (
$P_{\mathrm {dc}}$
), the combination of the conventional distributed amplifier (CDA) and the cascaded single-stage distributed amplifier (CSSDA) is utilized to the circuit. Moreover, the active variable termination resistor (AVTR) is adopted to adjust the flatness of gain. According to the experimental results, the proposed VGDA achieves a 21-dB peak gain with a 40-GHz 3-dB bandwidth (3.7–43.7 GHz), 18-dB gain control range (GCR), and 16° maximum phase variation.
A complementary metal‐oxide‐semiconductor (CMOS) dual‐band low‐noise amplifier (LNA) for 2G/3G/4G mobile communications is presented. It operates at 0.9 and 2.3 GHz of frequencies. The dual‐band operation is achieved by adding a modified notch‐filtering path in the wideband LNA. The modified notch‐filtering path does not require additional power to cancel the signals of the stop band frequency. The impact of the filtering path in the proposed LNA is analyzed. Improved results are observed in dual bands of frequency. Sustainability of the LNA under process corner variation and temperature variation are examined, and it is found to be suitable for the application. The proposed LNA is designed at 90‐nm technology in Cadence Virtuoso with 0.5 and 0.6‐V supply. The post‐layout simulation shows 22 dB of gain (S21), 2 dB of Noise Figure (NF), and −5.5 dBm of IIP3 at the high band. In the low band, 24 dB of S21, 2.7 dB of NF, and −6.65 dBm of IIP3 are reached. The circuit consumes 5.2 mW of power and 0.0918 mm2 of area. The efficiency of the LNA is estimated by the figure of merit, and comparable results are secured in the proposed work. A CMOS dual‐band low‐noise amplifier (LNA) for 2G/3G/4G mobile communications is presented. It operates at 0.9 and 2.3‐GHz of frequencies. The dual‐band operation is achieved by adding a modified notch‐filtering path in the wideband LNA. The modified notch‐filtering path does not require additional power to cancel the signals of the stop band frequency. The impact of the filtering path in the proposed LNA is analyzed. Improved results are observed in dual bands of frequency.
A 0.6-V low-power variable-gain low-noise amplifier by using 0.18-
${\mu }\text{m}$
CMOS process has been proposed. By using a tunable negative-feedback capacitor technology, variable gain can be achieved. Moreover, forward body biasing, input feedback capacitor, current-reuse and multiple-gate topologies are utilized for realizing low power consumption, small chip area, and high linearity. The measured results show the power gain and input third-order intercept point ranges from 4 dB to 10 dB and 0 dBm, respectively at 2.8 GHz. The power consumption is 0.6 mW.
This letter presents a simple approach for ultra-low-power and high-frequency variable gain amplifier (VGA) design, which requires no additional circuitry to generate the exponential-like function. Thus, the power consumption and chip area of the designed VGA can be drastically reduced without deterioration of other performance. The inverse exponential-like dB-linear characteristic is achieved by utilizing a pair of complementary transistors as the load. The p-MOS transistor is self-biased in the saturation region, while the n-MOS transistor is biased in the sub-threshold region. To prove the concept, a five-cell VGA is fabricated in a standard 0.18 CMOS technology. The measurements show that the power consumption of the VGA is less than 150 and achieves a total gain range of 71 dB, out of which 45 dB is dB-linear with less than 1 dB gain error, as well as bandwidth of more than 50 MHz. The output is better than 0 dBm and the minimum input-referred noise is 7.5 .
A simple and robust “cell-based” method is presented for the design of variable-gain amplifiers (VGAs). The proposed unit cell utilizes a unique gain compensation method and achieves accurate dB-linear characteristic across a wide tuning range with low power consumption and wide bandwidth. Several such highly dB-linear unit cells can be cascaded to provide the required gain range for a VGA. To prove the concept, single-cell, 5-cell, 10-cell and 15-cell reconfigurable VGAs were fabricated in a standard 0.18 μm CMOS technology. The measurement results show that the 10-cell VGA achieves a gain range of 38.6 dB with less than 0.19 dB gain error. The 15-cell VGA can either be used as reconfigurable VGA for analog control voltage or tunable PGA for digital control stream, with the flexibility of scaling gain range, gain error/step and power consumption. For the VGA at highest gain setting, it consumes 1.12 mW and achieves a gain range of 56 dB, gain error less than 0.3 dB.
This paper describes use of a novel exponential approximation for designing dB-linear variable gain amplifiers (VGAs). The exponential function is accurately generated using a simple error-compensation technique. The dB-linear gain is controlled linearly by the gate voltage, resulting in a simple and robust VGA. The proposed dB-linear VGA fabricated in a 65-nm CMOS process achieves a total variable gain range of 76 dB and dB-linear range greater than 50 dB with ±0.5-dB gain error. Under a 1.2-V supply voltage, the current consumption of the VGA is 1.8 mA and that of the output buffer is 1.4 mA. The input-referred in-band noise density is 3.5 nV/√{Hz} and the in-band OIP3 is 11.5 dBm. Due to the very simple circuit topology, the total active area of the VGA and the output buffer is extremely small, 0.01 mm2.
In this paper, a differential-ramp based variable gain amplifier (VGA) technique is introduced. Using the proposed technique, digitally programmable gain amplifiers (PGAs) can be converted to analog controlled, dB-linear VGAs with minimum impact on noise and linearity. This provides an efficient way of realizing an analog controlled VGA for OFDM based applications. The technique is illustrated by converting an opamp based high-linearity, low-noise PGA to a dB-linear VGA for CMOS mobile TV applications. The design including the cascade of a two-stage continuous 65-dB-linear VGA and a third-order Sallen-Key buffer stage is fabricated in a 65 nm CMOS process. The measured in-band OIP3 of the whole chain at maximum gain of 47 dB is 22 dBm, whereas the blockers in the adjacent channel result in 34 dBm OIP3 for the same gain setting. The design achieves 11 nV/¿(Hz) input referred noise density and occupies a die area of 0.17 mm<sup>2</sup>. The VGA circuit consumes 1.5 mA of current from a 1.2 V supply with an additional 200 ¿A switch control ramp current from a 2.5 V supply.
A fully integrated WirelessHD compatible 60-GHz transceiver module in 65-nm CMOS process is presented, covering the four standard channels. The silicon die is flip-chipped on top of a low-cost HTCC module which also includes an external 65-nm CMOS PA and large beamwidth antennas targeting industrial manufacturability. The module achieves a 16QAM OFDM mod- ulation wireless link with 3.8 Gbps over 1 m. The transceiver consumption is 454 mW in RX mode (including PLL) and 1090 mW in TX mode (including PLL and external PA). Index Terms—Analog baseband, CMOS, Gm-C contin- uous-time filter, high-temperature cofired ceramic (HTCC) module, low-noise amplifier (LNA), millimeter-wave (mmW) design, OFDM, power amplifier, 60 GHz, wireless HD.
Simple analytical expressions for MOSFETs noise parameters are developed and experimentally verified. The expressions are based on analytical modeling of MOSFETs channel noise, are explicit functions of MOSFETs geometry and biasing conditions, and hence are useful for circuit design purposes. Good agreement between calculated and measured data is demonstrated. Moreover, it is shown that including induced gate noise in the modeling of MOSFETs noise parameters causes ∼5% improvement in the accuracy of the simple expressions presented here, but at the expense of complicating the expressions.
The efficiency of body biasing for leakage reduction and performance improvement in a 90-nm CMOS low-power technology with triple-well option is evaluated. Static measurements of single devices and dynamic measurements of ring oscillators and 32-b parallel prefix adders are presented. Whereas forward biasing still provides a significant performance improvement of up to 37% for low-leakage devices with 2.2-nm gate oxide thickness, the application of reverse biasing to reduce subthreshold leakage currents is inefficient due to additional leakage currents such as gate leakage and gate-induced drain leakage. Experimental results confirm that, in 90-nm CMOS circuits, the efficiency of body biasing strongly depends on the device type and operating temperature. Moreover, the impact of the zero-temperature coefficient point on static device and dynamic circuit performance is investigated.
A limiting amplifier incorporates active feedback, inductive peaking, and negative Miller capacitance to achieve a voltage gain of 50 dB, a bandwidth of 9.4 GHz, and a sensitivity of 4.6 mV<sub>pp</sub> for a bit-error rate of 10<sup>-12</sup> while consuming 150 mW. A driver employs T-coil peaking and negative impedance conversion to achieve operation at 10 Gb/s while delivering a current of 100 mA to 25-Ω lasers or a voltage swing of 2 V<sub>pp</sub> to 50-Ω modulators with a power dissipation of 675 mW. Fabricated in 0.18-μm CMOS technology, both prototypes operate with a 1.8-V supply.
Precision dc-coupled amplifiers having risetimes of less than a nanosecond have recently been fabricated using the monolithic planar process. The design is based on a simple technique that has a broad range of applications and is characterized by a stage-gain- bandwidth product essentially equal to that of the transistors, and a very linear transfer characteristic, free from temperature dependence.
A CMOS variable-gain amplifier (VGA) using subthreshold
exponential region transistors with master-slave control technique is
proposed. The proposed technique is applied to an intermediate-frequency
VGA with a quadrature demodulator for wireless receivers. The test chip
is fabricated using a 0.25-μm CMOS technology. An 80-dB linearly
controlled gain range is achieved with exponential voltage-to-current
converters using MOS transistors biased in a subthreshold exponential
region, and the master-slave control circuits make the gain-control
characteristic insensitive to the temperature. The experimental results
indicate that the proposed technique is effective for a CMOS
variable-gain amplifier