A field programmable analog array for continuous, fuzzy, and multi-valued logic applications

Abstract

We propose a novel approach to the realization of continuous,
fuzzy, and multi-valued logic (mvl) circuits. We demonstrate how a
general-purpose field programmable analog array (FPAA), with cells
realizing simple arithmetic operations on signals, can be used for this
purpose. The FPAA, which is being implemented in a bipolar transistor
array technology, operates from ±3.3 V or ±5 V power
supplies and works in the range of frequencies up to several hundred MHz

Full text

A Field Programmable Analog Array for Continuous, Fuzzy,
and Multi-Valued Logic Applications1
Edmund Pierzchala, Student Member, IEEE
f.$
Marek A. Perkowski, Member, IEEE
f.$
Stanislaw Grygiel
$
TAnalogix Corporation, tel:
(503)
774-5918
$Department
of
Electrical Engineering, Portland State University
P.O.
Box
751, Portland, Oregon, 972074751
tel:
(503)
725-3806,
e-mail: edmundp@ee.pdx.edu
Abstract
In
this paper we propose
a
novel approach to the realization
of
continuous,
fiuzy,
and multi-valued logic (mvl) circuits.
We demonstrate how a general-purpose field program-
mable analog array (FPAA), with cells realizing simple
arithmetic operations
on
signals, can be used for this pur-
pose. The FPAA, which is being implemented
in
a bipolar
transistor array technology, operates from
f3.3V
or
fsV
power supplies and works in
the
range of frequencies up to
several hundred
MHz.
1.
Introduction
Digital programmable devices
for
classical, two-valued
logic have grown
in
importance over recent years.
Al-
though there are many published circuits for multiple-val-
ued logic (e.g.
[8,
18,
19]),
as
well
as
analog logic (includ-
ing continuous logics, fuzzy logic and Lukasiewicz logic
as
particular examples)
[9,
lo], to the best of the Authors’
knowledge there are no programmable devices for those
logics. In this paper
we
show how a general-purpose pro-
grammable analog array
(FPAA)
presented in [15], can
be
used for the implementation
of
a wide class
of
mvl, fuzzy
logic, and continuous logics circuits. Minor modifications
extending the
set
of
nonlinear operations realized
by
indi-
vidual cells
of
the
device are applied in order to reduce the
number
of
cells necessary
to
realize basic logic operations.
Both the structure
of
the device and the functionality
of
individual cells were chosen primarily for dynamic system
type
of
applications, but they prove to be well suited
for
the
realization
of
various mentioned logics. The presented ex-
amples are linked to the theory
of
realizing mvl functions
in
finite
fields, introduced
in
[12, 131, and generalized for
mvl
in
[14].
2.
The device
The
FPAA
is based on a regular, square array
of
current-
mode processing cells, interconnected on two levels: local,
1.
Patent
pending.
148
0195-623W94 $3.00
0
1994
IEEE
and global. Figures 1A and
B
show the local and the global
FIGURE 1A. Local signal interconnections
of
the FPAA.
FIGURE
1
B.
Global signal interconnections
of
the FPAA.

interconnection pattems, respectively. Each cell is con-
nected
to
its four nearest neighbors by
a
two-way current-
mode signal interconnection, and thus is able
to
receive
four different signals produced by those neighbors, wheth-
er
all
of them,
or
just selected ones. The cell’s own output
signal
is
progra”ab1y distributed
to
the same four neigh-
bors
(Figure
1A).
The global interconnection pattem is su-
perimposed on the local one, but it is shown separately to
avoid clutter (Figure
1B).
Each cell can broadcast its cur-
rent-mode output signal independently to any of the four
global lines
to
which the
cell
is
connected. Signals
sent
to
a global line from different cells are summed on this line.
If more
than
one cell receives the signal from a given global
line,
the
signal is divided evenly by the receiving cells.
Each cell can then send and receive signals to and from any
of its four nearest neighbors and any of the four global lines
to which it
is
connected. Each cell thus
has
eight inputs and
one output (in fact, eight outputs with copies of the same
output signal).
A
functional diagram of the cell is shown in Figure
2.
The cell processes current-mode, differential signals. Due
to the
lack
of
space only a general description of the cell’s
analog signal processing circuitry will
be
given. Detailed
design of the cell will
be
presented
in
[16].
Figure
3
shows the main building block
of
the cell
[2,4,
5.61.
In its simplest form the circuit contains only transis-
tors
Q,
-
Q4
and current source
f:.
Current sources
fA
rep-
resent the circuit’s input signals. The circuit is fully differ-
ential, i.e. both input and output signals are represented by
differences of currents
in
two wires.
The sum of currents
t
I
J
-
-
I
I
FIGURE
3.
Basic building block
of
the cell.
I:
which can be expressed as
[A(]
+
X)
is the positive
“half” of the input signal, and
I;,
which can be expressed
as
IA(1
-
X),
is its negative “half‘. The input signal is then
I,(]
+
X)
-
fA(l
-
X)
=
21,X;
X
is called
modulation
index.
Likewise, the output signal is the difference
Current gain is determined by the ratio IB/IAand
in
practice
can be
tuned
over several decades
from
a
fraction of
unity
to about
10.
The circuit has an excellent linearity
and
a
wide bandwidth, limited by the
fT
of the transistors
[2].
In
the bipolar process used for prototyping
fT
is of the order
of
8
GHz
and the simulated -3dB bandwidth of this circuit
fzu
-
f,,
expressed
as
+
Y)
-
IB(1
-
Y)
=
21~Y.
Programming signals
II
I
Co
nt ro
I
1
const
4L-J
FIGURE
2.
Functional diagram
of
the
programmable cell.
149

is over
3
GHz
for
fB
of several hundred FA.
Figure 4A
4
FIGURE
4.
Selected
DC
transfer characteristics
of
the cell.
shows the
DC
transfer characteristic of the circuit.
The
slope in
the
linear range can
be
changed by adjusting
the
gain.
The width and height of the linear range are deter-
mined by
the
currents
fA
and
fB,
respectively. By adding
(subtracting) currents on the input and on the output of
the
circuit (by additional programmed current sources) one can
change the location of the zero of the characteristic,
as
well
as
the two clipping (saturation) levels.
This
circuit
has
countless variations. By including tran-
sistors
Qs
and
Q6
one achieves the ability
to
invert the sig-
nal (negative weight).
If
another pair of inputs is connected
in place of the tail current sources
I,+
and
f;,
a cur-
rent-mode Gilbert multiplier
[3]
is realized. More transis-
tor pairs can
be
added (dashed line) to obtain more indepen-
dently tuned outputs.
Figure
5
shows the schematic of
a
multiplexer-summer
with independent tuning of input weights. Additional
summation (without independent tuning) can
be
realized
by connecting a number of signals to each input.
FIGURE
5.
Multiplexer-summer.
A demultiplexer can be realized in a similar fashion by
placing more inner (output) pairs
of
transistors. Circuits
from this family can
be
connected in cascades by adding
current sources (dashed line in Figure
5).
Then the differ-
ence between the (constant) current from such sources and
the output signal of one stage can be fed to the next stage.
This arrangement has better frequency response than a pnp
current mirror. By cascading several stages based on the
circuit of Figure
3
a wide-band current amplifier tunable in
the range of
0
-
80dB or more
[2,4]
can be obtained.
Two
(or more) nonlinear blocks shown in Figure
2
can
be real-
ized
as
single amplifier stages each. With two blocks one
can achieve
many
nonlinear characteristics, some of which
are shown in Figures 4A-H.
The integrator (Figure
6)
is
realized by connecting
an
operational transconductance amplifier
(OTA)
input stage
to
a current amplifier. The current amplifier has an addi-
tional voltage-mode output. Capacitors C are connected to
this output and to the input of the OTA, realizing a Miller
integrator. The current-mode output signal
of
the amplifier
is proportional
to
its voltage-mode output signal, which
represents the integral of the input current-mode signal. In
150

FIGURE
6.
Current-mode integrator and
sam-
pleand-hold circuit.
this
feedback arrangement the OTA works with a
very
small input voltage swing (provided that the gain in the
loop
is
high): also, due
to
the feedback opemtion the volt-
age on the capacitors is only slightly disturbed by the non-
linearities within the loop. Thus the linearity of the circuit
is primarily detennined by the linearity of the relationship
between the voltage-mode and the current-mode output
signals, which
is
fairly good if the output stage
is
designed
properly. The OTA input stage linearity is not critical. This
design inherits
all
good
features of the classical Miller inte-
grator employing a voltage-to-voltage amplifier (an op
amp), that is the ability
to
realize a low-frequency pole
(ideally,
an
integrator's pole should be at zero)
with
small
capacitors value, practically independent of the
hped-
ances of the source of the input signal and the load. This
is because the capacitors
see
an extremely high impedance
(typically
of
the order of tens
or
even hundreds of
Ghl).
In
the traditional design of
a
current-to-current integrator, the
Miller integrator (or even a capacitor)
is
followed by
an
OTA, converting the full range of voltages developing
across the capacitor into the output current. In such a de-
sign the linearity of the OTA limits the linearity of the inte-
grator, even though (in the Miller integrator) the voltage on
the capacitors
is
a
nearly perfectly linear integral of the in-
put signal. The circuit has additional advantages over the
classical design. The input signal can
be
fed directly into
the current amplifier, making the voltage on the capacitors
track the input signal. When desired, the input stage of the
current amplifier can be turned off, and the capacitors will
hold the last value of the signal. Finally, when no integra-
tion or sample-and-hold operation is necessary, the voltage
output
is
turned off and only the current amplifier is
used.
With
C
of 0.8pF the circuit demonstrates simulated
phase response of
-90M.5"
in the range of several
hundreds
Hz
to
over
300
MHz. The pole can be moved by
changing the operating conditions of the circuit. If a high
frequency pole
is
desired, the output signal can be
fed
back
to
an
additional input of the OTA to simulate resistors con-
nected to the output. The integrator contains the only
high
impedance points
in
the circuit.
Different functions of the cell are programmed by
changing the tail currents in the amplifier, multiplier, and
integrator circuits. For instance, if no multiplication is re-
quired, a constant (tunable) current is fed into one input of
the
multiplier. This represents selection symbolically
shown
as
const
in Figure
2.
In that case, the multiplexer-
summer disconnected from the multiplier can still be used
for the calculation
of
the signal connected to the control
block.
Power dissipated by the circuit depends on the number
of cells
used,
number of active inputs and outputs in each
cell,
tail
currents, and power supply voltages. For
f3.3V
supply voltages, four inputs active, and bias cwrents of
200pA,
power dissipated by a single cell is about 40mW.
The
control
block
stores programming information re-
ceived
f"
the outside of the cell, and sends control sig-
nals to analog processing blocks of the cell. Additionally,
it
performs comparison of the input signals against signals
produced by the analog processing blocks
or
a programmed
constant (Figure
7).
Each of the comparators produces
two
Y
I
It_
FIGURE
7.
Control block
of
the cell.
binary signals corresponding to the conditions
a
5
b
and
a
2
b.
Two signals of equal value on the output of any
comparator indicate equal input signals. This way the con-
trol block can produce control signals being a function of
certain conditions of instantaneous input signal values,
such
as
equality of two or more signals, equality
of
a
num-
ber of signals
to
zero or another constant, etc. This feature
is
also used
to
realize
minimum
and
maximum
follower
(min
and
man),
absolute value (abs),
and other operations.
To
realize
m'n
and
lltay
operations the control block simply de-
tects the smallest (largest) signal and selects this signal on
151

the input of the cell. This is accomplished by comparing
the output signal of the selected multiplexer-summer with
the input signals.
If
one (or more) of the input signals
are
smaller (larger) then the multiplexer-summer output, the
control circuit sends appropriate signals to the multiplexer-
summer
to
adjust its weights until
the
smallest (largest) sig-
nal is selected. When realizing the
ubs
function, the control
block
changes the sign
of
input weights
if
the weighted sum
is negative.
Some operations important for mvl, fuzzy and other log-
ic applications, performed by the cell,
are
summarized in
Table
1.
Xi
denote input signals,
Y
denotes the output sig-
nal.
No
distinction
is
made between local and global sig-
nals, since the cell processes
them
in the same manner.
Table
1.
W,
and
W2
are independent sets
of
input weights;
k
is
tuned in the
range
0
-
8OdB.
Complements
of
the signals (to the maximum pos-
sible signal value,
Max)
can
be
calculated.
3.
Y
=
kXjXj
4.
Y=kX?
5.
6.
7.
Y
1-6
is
any
of
the functions presented
in rows
1-6
above;
a
2
0.
8.
Y
=
U
Sign(Y,-6)
a=b,k=w.
y
=
k
mh@,,
...,
x,)
Y
=
k
max(X,
....,
X,)
y
=
k
y,
-6&
The control
block
"watches" input
signals and
selects
the smallest one.
Udenotes the step function.
a
=
0,
b
=
Ma,
k=
CO.
9.
y
=
b
u(yl-6)
As
seen from the table, the cell
performs
summing of in-
put signals selected by the control circuitry, multiplication
of two signals (squaring of one signal), or multiplication of
two independently derived weighted
sums
of input signals.
Further processing includes lossless or lossy integration,
and clipping.
The functions shown above
are
important for the imple-
mentation of continuous-time dynamic systems [7], and
multi-valued, fuzzy, and continuous (such
as
Lukasiewicz)
logic circuits.
The architecture of
the
device is motivated by the desire
to enable circuit realizations with minimal signal delays.
A number of examples, including
an
elliptic eighth-order
ladder filter [17], a
rank
filter cell [ll], circuits for tracking
the product of
two
matrices, a solution of a system of linear
equations
[7],
and a solution of a linear programming prob-
lem by the method of steepest descent [7], are shown in
1151.
The cell is being implemented in a bipolar transistor
array
process.
An
implementation in BiCMOS and analog
CMOS
(to
increase
density) is considered.
3.
MVL
applications
3.1.
Galois field
22
operations
Figures
8A
and
B
show the tables for addition and multi-
aObO
12 3
00000
10123
20231
30312
Ea
-2
-3
3
2
1
xmod3
FIGURE
8.
GF(22)
operations.
plication in Galois field of four elements. Each of these op-
erations can
be
realized by a single cell of
FPAA,
assuming
that only
two
of the cell's inputs are used
at
a time. Addi-
tion
can
be
realized
as
a=b
=f(a+b)
for
a#b
(Figures 8C
and
D),
and
a=b
=
0
otherwise. The condition
a=b
can be
detected by the control block. This requires programming
the weights of one of the input multiplexers-summers to
152

calculate the difference
a-b
of the input signals, selecting
constant
0
for comparison in the control block, and control-
ling the weights of the other input multiplexer to set them
to zero
if
a=6
was detected. Instead of functionf(x) (Figure
8D) a smooth functionfi(x) (Figure 8E) can
be
used. This
function
can
be
realized by adding two characteristics of
the saturation blocks shown in Figure 8F.
If
the function of
the form shown in Figure 8D is required, it can be realized
by providing more nonlinear blocks in the cell.
Multiplication aOb in the field (Figure 8B) can
be
real-
ized
as
a06
=
((a+6-2)
mod
3)
+
1
for
a#O
and
6#0,
and
aOb
=
0
otherwise. The two conditions for
a
and
b
can be
tested independently by the comparators
in
the control
block, and upon
at
least one of them being
true
the input
weights of the multiplexer-summer would
be
turned down
to
0.
Mod
3
operation can
be
realized
as
shown
in
Figures
8G and
H.
The control block performs
the
necessary logic
operations.
The realizations of GF(22) operations proposed above
are
similar to the ones presented in
[
191.
3.2.
Orthogonal expansion structures
Having defined the addition and multiplication
in
GF(22),
we
can
apply the combinational functions synthe-
sis method based on orthogonal functions presented in [141.
Figure
9A
shows a block diagram of a structure realizing
a function of input variables
XI,
X2,
...,
X,.
Each column
realizes one orthogonal function over GF(2*). Multiplied
by a constant from GF(22), this function is added
to
the oth-
er orthogonal functions. All operations are
in
GF(22). Fig-
ure 9B shows
an
example of realization of one of the func-
tions$. Since each cell can realize the identity operation
(see Table
l),
it is possible to omit certain input variables
X;,
X3
in this example. More
than
one column of cells can
be
used for the realization of eachj
if
necessary. Also, it
may
be
convenient to make certain input variables avail-
able on more than one horizontal line.
An
altemative ap-
proach, based on providing literals on horizontal lines, or
some
functions of single variables which
are
convenient for
the creation of literals, is also possible.
In
one such
ap-
proach the powers (i.e. multiple products in GF(22)) would
be
used to create polynomial expansions of mvl functions.
3.3.
Post logic
Same structures shown
in
Figure 9 can be used for the
implementation of Post logic. Each cell can realize
m'n
and
ntax
operations (Table l), and literals of
the
form shown in
Figure
4C.
Each functionf;: is realized
as
in Figure 9B, ex-
cept that the cells realize
min
or identity operation. Instead
of summing over GF(22),
ntax
operation is used.
FIGURE
9.
Orthogonal expansion structures.
3.4.
Other logics
The structure of Figure 9A can
be
used for realization of
combinational functions with other methods. Such realiza-
tions, unlike the ones based on the orthogonal expansions,
may not be unique in the presented structure, however due
to the availability
of
addition, multiplication (in the con-
ventional sense), and nonlinear operations on signals, some
combinational functions may have very efficient imple-
mentations.
Also, the topology of mvl circuits mapped into the
FPAA
does
not have to be constrained to the form shown
in Figure
9.
Global vertical and diagonal signal lines can be
used, if necessary, to achieve greater flexibility
of
the cir-
cuits' topologies. Figure 10 shows a structure for imple-
mentations based on generalized Shannon expansion of
mvl functions [14]. Some input variables need to be con-
nected to more
than
one diagonal line.
More
general forms
of the same kind are possible, based on other operators than
>
used for separation, for instance even vs. odd parity,
based on matrix orthogonality
[
141, which is a generaliza-
tion of the approach presented in [12, 131 for two-valued
functions.
Finally, the integrator block can be used
as
a memory
element, enabling realization of sequential circuits. Since
each cell can realize identity function, and global connec-
tions are available, larger irregular structures, composed of
combinational and sequential parts can be built in the pres-
ented structure.
4.
Analog
logics
Fuzzy logic and continuous logics (such
as
Lukasiewicz
logic) [9, 101 can
be
realized
as
well. As an example, let
us consider
an
implementation of a
fuzzy
logic controller
153

I
const
- -
-A-
i
FIGURE
10.
Generalized Shannon expansion
structure.
with correlation-product inference
[8].
A structure very
similar to that of Figure 9A, shown in Figure
11
A, is used
to implement a controller with
m
input variables and
n
fuzzy inference rules. Figure
11B
shows details of each
rule implementation. Fuzzy membership function
is
im-
plemented
as
a
trapezoidal transfer function of the kind
shown in Figm
4C.
Activation values
wj
are multiplied by
centroid values of
the
fuzzy rules consequents
Cj,
and their
areas
fj,
yielding
two
sums computed on
two
horizontal
global lines. The final expression for the defuzzified out-
put variable
Vk
is produced by a two-quadrant divider
[7]
shown in Figure
11C.
5.
Conclusions
In this paper, we have demonstrated how a general pur-
pose
field programmable analog array can
be
used for
the
implementation of various logic circuits. Although the
FPAA
was designed for dynamic systems and general elec-
tronics,
its
structure and functionality is generally well
suited to the presented applications. Only minor modifica-
tions of
the
FPAA
introduced
in
[
151,
namely the inclusion
of two or more nonlinear blocks,
are
necessary to enable
product
fuzzy
set
membership
0
min
FIGURE
11.
Fuzzy
controller.
convenient realization of the presented examples.
It is
demonstrated that
the
realizations based on orthogonal ex-
pansions
as
well as more general ones, based on sets of not
necessarily orthogonal functions, lead
to
regular circuit
structures which can
be
easily mapped to the FPAA.
The
FPAA
is an excellent tool for fast prototyping of cir-
cuits
in
various logics. It will provide the researchers
in
the
field with an opportunity to experiment with hardware real-
izations of various logic circuits without the necessity to
design and fabricate them. Presented examples demon-
strate simplicity
of
realization of a wide class
of
such cir-
cuits, which will
also
enable the implementation of design
automation pmedures.
The
FPAA
is under implementation in a bipolar transis-
tor array technology. For future applications, a program-
mable device dedicated to
mvl,
fuzzy and other logics can
be
implemented based on the presented material.
154

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