Dual source negative capacitance GaSb/InGaAsSb/InAs heterostructure based vertical TFET with steep subthreshold swing and high on-off current ratio

Abstract

Continuous downscaling of CMOS technology at the nanometer scale with conventional MOSFETs leads to short channel effects (SCE), increased subthreshold slope (SS), and leakage current, degrading the performance of ICs. We proposed a dual-source vertical tunnel field-effect transistor (TFET) with a steeper subthreshold swing (SS) and superior electrostatic control thanks to quantum mechanical band-to-band tunneling. We show that the use of GaSb/InGaAsSb/InAs heterostructure boosts the band-to-band tunneling rate in TFETs, resulting in higher on-state current. Incorporating the negative capacitance effect using ferroelectric materials further enhances the performance of the proposed device greatly. The lowest SS of 21.94 mV/dec and an on-off current ratio of 4.3267 × 10 11 were obtained for dual source GaSb/InGaAsSb/InAs heterostructure based vertical TFET. The lowest subthreshold swing was found as 17.37 mV/dec after integrating Hf 1-x Zr x O 2 ferroelectric material into the gate stack. The negative capacitance effect also increases the on-state current tenfold, resulting in an incredible I ON /I OFF ratio of 10 12. The suggested device focuses on low power consumption applications by assuring a very low leakage current and a reduced subthreshold swing.

Full text

Results in Physics 29 (2021) 104796
Available online 9 September 2021
2211-3797/Published by Elsevier B.V. This is an open access article under the CC BY license (http://creativecommons.org/licenses/by/4.0/).
Dual source negative capacitance GaSb/InGaAsSb/InAs heterostructure
based vertical TFET with steep subthreshold swing and high on-off
current ratio
Minhaz Uddin Sohag
a
, Md. Sherajul Islam
a
,
c
,
*
, Kamal Hosen
a
, Md. Al Imran Fahim
a
,
Md. Mosarof Hossain Sarkar
a
, Jeongwon Park
b
,
c
a
Department of Electrical and Electronic Engineering, Khulna University of Engineering & Technology, Khulna 9203, Bangladesh
b
School of Electrical Engineering and Computer Science, University of Ottawa, Ottawa, ON K1N 6N5, Canada
c
Department of Electrical and Biomedical Engineering, University of Nevada, Reno, NV 89557, USA
ARTICLE INFO
Keywords:
Vertical tunnel FET
Dual source
Ferroelectric material
Negative capacitance
Heterojunction
ABSTRACT
Continuous downscaling of CMOS technology at the nanometer scale with conventional MOSFETs leads to short
channel effects (SCE), increased subthreshold slope (SS), and leakage current, degrading the performance of ICs.
We proposed a dual-source vertical tunnel eld-effect transistor (TFET) with a steeper subthreshold swing (SS)
and superior electrostatic control thanks to quantum mechanical band-to-band tunneling. We show that the use
of GaSb/InGaAsSb/InAs heterostructure boosts the band-to-band tunneling rate in TFETs, resulting in higher on-
state current. Incorporating the negative capacitance effect using ferroelectric materials further enhances the
performance of the proposed device greatly. The lowest SS of 21.94 mV/dec and an on–off current ratio of
4.3267 ×10
11
were obtained for dual source GaSb/InGaAsSb/InAs heterostructure based vertical TFET. The
lowest subthreshold swing was found as 17.37 mV/dec after integrating Hf
1–x
Zr
x
O
2
ferroelectric material into the
gate stack. The negative capacitance effect also increases the on-state current tenfold, resulting in an incredible
I
ON
/I
OFF
ratio of 10
12
. The suggested device focuses on low power consumption applications by assuring a very
low leakage current and a reduced subthreshold swing.
Introduction
The progressive scaling down in channel length, oxide thickness, and
channel width of MOSFET results in high leakage current because of
short channel effects such as hot carriers effect (HCE), drain induced
barrier lowering (DIBL), mobility degradation, and so on [1–3].
Reducing power dissipation in nanoscale devices is also a great chal-
lenge since the subthreshold swing (SS) for MOSFETs employing the
carrier injection approach over an energy barrier cannot be made lower
than 60 mV/dec at 300 K, a phenomenon known as “Boltzman Tyranny”
[4]. As the size reduction of conventional MOSFET structures has
reached a limit, new structures to replace traditional MOSFET structures
must be proposed. The proposed topologies should have low power
consumption characteristics, optimal circuit size, and suitable process-
ing speed to function at higher frequencies [5].
To circumvent the so-called “Boltzman Tyranny,” steep switching
devices such as impact ionization MOSFETs (I-MOSFETs) [6], negative
capacitance (NC) MOSFETs [7,8], nanoelectromechanical eld-effect
transistors (NEMFETs) [9], and tunnel FETs (TFETs) [10] have been
extensively studied. Tunnel FETs offer a better subthreshold swing than
other proposed architectures due to the quantum–mechanical band-to-
band tunneling (BTBT) of carriers from source to channel rather than
a carrier injection mechanism over an energy barrier [11]. It provides
steeper switching than conventional MOSFETs as the devices are not
subjected to thermionic emission constraints [12,13]. As a result, Tunnel
FETs are a good substitute for MOSFETs because they can overcome the
limits of short channel effects and have a better subthreshold swing[14].
However, typical Si-based TFETs have a relatively low on-state current
because of their restricted BTBT rate, despite being an ultralow-power,
extremely reliable, and cost-effective technology [15]. The restricted
BTBT rate may occur due to the high effective mass of the carrier and the
larger value and indirect nature of the bandgap [16].
Several studies have been conducted in recent years to address these
issues, including heterojunctions with reduced bandgap materials such
* Corresponding author.
E-mail address: sheraj_kuet@eee.kuet.ac.bd (Md.S. Islam).
Contents lists available at ScienceDirect
Results in Physics
journal homepage: www.elsevier.com/locate/rinp
https://doi.org/10.1016/j.rinp.2021.104796
Received 7 July 2021; Received in revised form 18 August 2021; Accepted 5 September 2021

Results in Physics 29 (2021) 104796
2
as SiGe, InGaAs, Ge, InAs, SiGe, and high k-dielectric oxide material
[17–20]. In particular, GaSb and InAs are of special interest because of
their lower effective mass of carriers, direct nature of bandgap, and
tunability of the effective barrier height [21,22]. It is demonstrated that
GaSb, InAs and their mixture can signicantly enhance BTBT rate and
tunneling current densities [23–25]. In contrast, the vertical placement
of the source, channel, and drain would further improve the scalability
and performance of the device, which has already been widely examined
[26–30]. A vertical tunnel FET with triple metal-gate layers (TMG-TFET)
with an on–off current ratio of 10
8
and an average SS of 43.5 mV/dec
was reported by Ko et al. [27]. Vanlalawmpuia et al. [28] studied a Ge-
source vertical TFET and discovered an I
ON
/I
OFF
of 10
11
with an average
SS of 21.2 mV/dec. Jang et al. [29] developed a gate-metal-core
VNWTFET with an SS of 42.8 mV/dec and an on–off current ratio in
the order of 10
7
. Jung et al. [30] suggested a ferroelectric-gated vertical
TFET with an SS of 22 mV/decade and an I
ON
/I
OFF
ratio of 3.28×10
10
.
However, the on-state current of these devices is insufcient due to the
low tunneling rate. Although several of those structures provide better
SS, they could be made steeper. Despite their superior performance than
standard MOSFET structures, more investigations are thus highly
demanded to further improve the performances.
On the contrary, the integration of ferroelectric material (NC effect)
into the gate stack of tunnel FETs has already been proposed to bend the
energy band, resulting in a signicant increase in BTBT probability
[31,32]. The SS of the device structure is given by
∂
Vg
∂
log10(Id), which is
further resolved into
∂
Vg
∂ψ
s (body factor) and
∂ψ
s
∂
log10(Id)(transport factor)
[33,34]. The FE material in the gate stack acts as a negative capacitor,
reducing the body factor by amplifying
ψ
s via the NC effect, which aids
in lowering SS [8]. Ferroelectric NC can be easily integrated into existing
TFET structures and used with approaches that reduce transport factors
to obtain further SS reduction. As a result, the ferroelectric material’s
negative capacitance effect can improve the device performance,
ensuring a steeper off-to-on transition and an excellent I
ON
/I
OFF
current
ratio.
Here, we propose a dual-source negative capacitance GaSb/
InGaAsSb/InAs heterostructure-based vertical TFET structure to resolve
limitations in past studies. The proposed device structure enhances the
on-state current by reducing the electric eld at the channel drain
junction and doubling the effective tunneling area. We use Hf
1–x
Zr
x
O
2
(HZO) ferroelectric material to introduce a negative capacitance effect,
which further signicantly enhances the performance of the device. We
obtain the lowest subthreshold swing of 17.37 mV/dec and an incredible
on–off current ratio of 10
12
from the proposed device, which out-
performs all previous works.
Device structure
The equivalent capacitance model and a schematic depiction of the
proposed device structure are shown in Fig. 1. As illustrated in Fig. 1(b),
the ferroelectric capacitor is connected in series with the positive
capacitor, which is realized by a dielectric material. Here, the baseline
structure for the proposed device is the structure without the HZO layer.
The high-k gate oxide in the system is a 2 nm amorphous HfO
2
layer,
with a metal gate having a work function of 4.9 eV. The critical thickness
of ferroelectric oxide material for the proposed device structure is found
to be 8 nm. For the suggested structure, the gate and channel lengths are
10 nm and 50 nm, respectively. The gate length and channel length are
dened as the gate and channel contact lengths and the source and drain
contact lengths, respectively. The suggested device construction uses
GaSb, InGaAsSb, and InAs as the source, channel, and drain materials,
respectively. To reduce series resistance, the source and drain regions
are heavily p-doped (10
19
atoms/cm
3
) and strongly n-doped (10
19
atoms/cm
3
), respectively [35]. The channel area, on the other hand, is
lightly n-doped (10
15
atoms/cm
3
).
Methodology
The proposed dual-source negative capacitance GaSb/InGaAsSb/
InAs heterostructure-based vertical TFET is simulated using the ATLAS
Silvaco 2D simulator, a technology computer-aided design (TCAD) tool
that employs both non-local BTBT and the Landau-Khalatnikov (L-K)
equation. The one-dimensional L-K equations for the FE capacitor have
been self-consistently coupled with the non-local BTBT model. The
essential governing equations for the proposed structure are the
Schr¨
odinger and Poisson equations, which were solved in the TCAD
environment [36]:
−ℏ
2
1
dz2
1
m*(z)
ψ
(z)+V(z)
ψ
(z) = EiΨ(z)(1)
∇.D(z) = − [n(z)−
σ
(z)] (2)
These equations were solved at the nodal points of the mesh specied
for the device structure. In the suggested device construction, meshing
density is increased in the interface portion of two different materials,
while coarse meshing is used in other sections to improve output. To
simulate the tunneling process more accurately, the non-local BTBT
model is utilized to determine the tunneling current, dependent on the
spatial variation of the energy band. It also considers the fact that the
opposing carrier type’s generation/recombination is not spatially
contemporaneous. The net current per unit area for an electron with
transverse energy E
T
and longitudinal energy E in the non-local BTBT
model is given by [36],
J(E) = q
π
ℏ  T(E)[fl(E+ET)− fr(E+ET)]
ρ
(ET)dEdET(3)
where fl and fr are Fermi-Dirac functions using the quasi-Fermi-level on
the left-hand side of the junction and right-hand side of the junction,
respectively. The transverse electron effective mass(me)and the trans-
verse hole effective mass(mh)are combined in the 2D density of states as
[36],
Fig. 1. (a) Schematic diagram for the proposed dual source negative capaci-
tance GaSb/InGaAsSb/InAs heterostructure based vertical TFET and (b) the
capacitance model. Here C
MOS (total equivalent capacitance of the dual source
GaSb/InGaAsSb/InAs heterostructure based vertical TFET) and CFE (FE layer
capacitance) are in a series combination and V
G
is the effective gate voltage of
the proposed device including HZO. After the incorporation of HZO, the gate
voltage of the baseline structure becomes the surface potential
ψ
S.
M.U. Sohag et al.

Results in Physics 29 (2021) 104796
3
ρ
(ET) = 
memh
√
2
π
ℏ2(4)
And for an electron with longitudinal energy E, the tunneling prob-
ability can be expressed as[19],
T(E)
α
exp−4
2m*
√E3/2
g
3|e|ℏEg+Δφ
ε
s
ε
0x
t0xts
Δφ(5)
where m*,Eg,
ε
s,
ε
0x,t0x,ts,and Δφ are effective carrier mass, energy
bandgap, semiconductor material dielectric constant, oxide dielectric
constant, oxide thickness, semiconductor material thickness, and energy
range that provides tunneling, respectively. Eq. (5) claries that the
effective mass of electrons and the bandgap energy of semiconductor
materials utilized in the device structure are directly related to electron
tunneling. The bandgap narrowing model and Fermi-Dirac statistics are
used to account for the highly doped source/drain areas. As mobility
models, the concentration-dependent Conmob, parallel electric eld-
dependent Fldmob, and Lombardi models were employed. The
Shockley-Red-Hall and Auger recombination model was used to main-
tain constant minority carrier lifetimes and high current densities.
Transfer curve and output characteristics are found for baseline dual
source GaSb/InGaAsSb/InAs heterostructure based vertical TFET device
structure from simulation. These results are used to verify the negative
capacitance behavior of HZO. Ferroelectric materials are made up of
domains of electric dipoles. These domains of electric dipoles can vary
their polarization orientation based on an externally applied bias.
Although the free energy density U of ordinary dielectrics has a
quadratic relationship with the sheet charge density that appears across
their terminals, the free energy density U of a typical ferroelectric ma-
terial can be expressed as an even order polarization polynomial P as
follows[37]:
U=
α
P2+βP4+γP6−EP (6)
Here the terms
α
, β and γ are the anisotropy constants for the FE
material, and the electric eld E is denoted by [8],
E=VFE
tFE
(7)
where VFE indicates the voltage across the FE layer and tFE is the FE layer
thickness. The NC condition of ferroelectric materials is represented by
the inverted parabolic shape in the energy landscape around the origin
[38]. The L-K equation can be used to explain the behavior of ferro-
electric capacitors under a constantly uctuating electric eld E [39]:
ρ
dP
dt= − dU
dP(8)
Substituting U from Eq. (6), we have,
ρ
dP
dt= − 2
α
P−4βP3−6γP5+E(9)
Here
ρ
is the material’s damping coefcient, which explains a
ferroelectric material’s hysteresis behavior under dynamic conditions.
The equilibrium state for the FE can be found by setting P =Q and
exploring the minima of U [8].
dU
dQ=tFE2
α
Q+4βQ3+6γQ5−VFE =0(10)
This leads to the desired relationship between VFE and Q as follows,
VFE =tFE2
α
Q+4βQ3+6γQ5(11)
In this paper, Hf
1–x
Zr
x
O
2
is treated as a FE material with a concen-
tration of x =0.5, and the values of
α
, β and γ are taken from previous
studies [8,40]. The NC properties of the Hf
0.5
Zr
0.5
O
2
are examined using
the Landau model, with remnant polarization (P
r
) and coercive eld (E
c
)
set at 14.3 µC/cm
2
and 1.55 MV/cm, respectively [40]. The free energy
density vs. polarization and polarization vs. electric eld curves [see
Fig. 2] are constructed using the mentioned remnant polarization (P
r
)
and coercive eld (E
c
) values, which resembles the results of earlier
studies [41,42]. The inverted parabolic form derived from the energy
landscape in Fig. 2(a) conrms the presence of NC within HZO [37]. In
the steady-state (dP/dt=0), HZO exhibits ‘S’ shaped characteristic
around the origin with a negative slope (dP/dE<0), as seen in Fig. 2(b).
At E =0, the negative-slope region surrounding the origin becomes
unstable, causing the polarization to settle into one of two residual
states. These two stable polarization states at zero electric eld are
switchable only by introducing an electric eld larger than the coercive
eld E
c
[43,44]. The presence of NC state in HZO is indicated by the
negative slope of the P-E curve in Fig. 2(b). Under dynamic sweep, the
FE material exhibits an anti-clockwise hysteresis with a non-zero P at E
=0. The term
ρ
dP
dt in Eq. (9) slows the maximum rate of change in po-
larization P. It causes an anti-clockwise hysteresis by delaying the
change in polarization P in response to a change in electric eld E. The
hysteresis behavior of HZO with a non-zero polarization at the zero
electric eld is conrmed in Fig. 3(a). The FE material’s NC state is
extremely unstable. As a result, the primary problem is to keep it stable
when employing it in semiconductor devices. The gate oxide in the
proposed structure is HfO
2
. The ferroelectric-dielectric heterostructure
must fulll the following criteria to stabilize the FE in the NC state [45].
|CFE|>CMOS (12)
A hysteric jump of polarization occurs when CFE is less than CMOS ,
suppressing the NC feature of HZO. The following equation can be used
to calculate the FE capacitance (CFE )[33].
CFF =dQ
dVFE =2
α
+12βQ2+30γQ4×tFE −1(13)
The device structure must be constructed in such a way that the
mismatch between CFE and CMOS is as little as possible to leverage the NC
effect of HZO in the proposed semiconductor device.
The polarization vs. electric eld curve for Hf
0.5
Zr
0.5
O
2
is shown in
Fig. 3(a) under the dynamic sweep of the electric eld. Negative
permittivity is observed in case of FE materials. Permittivity for ferro-
electric materials can be expressed as follows [46].
ε
0
ε
f=
ε
0+dP
dE≈dP
dE(14)
Therefore, negative capacitance is found in FE when polarization
acts in the opposite direction of the applied electric eld. The inverse of
the permittivity can be derived by differentiating E with regard to P.

ε
0
ε
f−1=2
α
+12βP2(15)
The anisotropy constant
α
is inversely related to the permittivity,
which results in a negative slope in the “S”-shaped P vs. E curve [see
Fig. 2(b)] [46]. Therefore, HZO’s lower
α
value makes it an appealing
choice for advanced gate stack applications[38,41]. Fig. 3(b) depicts
permittivity vs. electric eld curve for Hf
0.5
Zr
0.5
O
2
thin lm for both
forward and reverse sweep.
Results and discussion
First, we simulated the baseline dual-source GaSb/InGaAsSb/InAs
heterostructure-based vertical TFET structure without negative capaci-
tance effect. The I
d
- V
g
characteristics for the baseline heterostructure in
logarithmic scale at various drain voltages are shown in Fig. 4. As
depicted in Fig. 4, increasing the drain voltage results in a higher I
ON
/
I
OFF
ratio and a reduced subthreshold swing. As previously stated,
traditional TFET structures have a low on-state current. In contrast, the
suggested baseline heterostructure has an on-state current of 1.3031
μ
A/
μ
m (at V
g
=0.9 V) and an off current of 3.0118 aA/
μ
m, resulting in a
high I
ON
/I
OFF
of 4.3267×10
11
. The average SS found for baseline
M.U. Sohag et al.

Results in Physics 29 (2021) 104796
4
heterostructure is 42.97 mV/dec, with the lowest SS being 21.94 mV/
dec. For the proposed baseline heterostructure, the charge inversion
event occurs at V
g
=0.65 V. All of the above-mentioned simulated re-
sults for the baseline heterostructure were obtained by maintaining the
drain voltage constant at 0.5 V. While the I
ON
/I
OFF
and SS obtained from
the suggested baseline heterostructure are excellent, the on-sate current
is insufcient, affecting the device’s overall performance. Therefore,
negative capacitance is added in the baseline heterostructure to improve
the overall performance of the device by acting as a performance
booster.
The SS is the change in gate voltage (V
g
) needed to change the drain
current (I
d
) by an order of magnitude[47]. Thus, the SS can be written as
follows [33]:
SS =
∂
Vg
∂
log10(Id)=
∂
Vg
∂ψ
s

m
∂ψ
s
∂
log10(Id)

n
(16)
Here
ψ
s stands for surface potential [Fig. 1(b)] and m is dened as
body factor which can also be expressed as follows[8]:
m=1+Cs
Cins(17)
Here Cs and Cins represent the capacitance of semiconductor and gate
insulator, respectively. The second term n in Eq. (16) is dened as a
transport factor determined by the transport mechanism. To break the
Boltzmann limit, the transport factor (n) is reduced by modifying the
transport mechanism in devices like tunnel FETs and impact ionization
FETs. The use of ferroelectric material in the gate stack reduces the body
factor (m) to less than one, lowering the SS in negative capacitance
TFETs even further. When gate voltage (Vg) is applied, it produces [8],
ψ
s=Vg1+Cs
Cins−1
(18)
Here
ψ
s
Vg>1 if Cins is replaced by CFE (capacitance of ferroelectric
material) as CFF <0 [40].
That is, ferroelectric material utilized as a gate insulator in the gate
stack helps in the amplication of surface potential(
ψ
s). Using the NC
effect of ferroelectric materials and modifying the transport mechanism
Fig. 2. (a) The energy landscape and (b) polarization vs. electric eld for HZO under steady state. Red marked region in both (a) and (b) indicates the NC state of
HZO analyzed using the Landau model of FE. (For interpretation of the references to colour in this gure legend, the reader is referred to the web version of
this article.)
Fig. 3. Characteristics for Hf
0.5
Zr
0.5
O
2
FE thin lm: (a) polarization vs. electric eld under the dynamic sweep of the electric eld and (b) permittivity vs. electric
eld curve.
M.U. Sohag et al.

Results in Physics 29 (2021) 104796
5
that limits the performance of traditional transistors, the so-called
“Boltzmann Tyranny” is broken. A lower SS value suggests steeper
switching of devices, resolving energy issues associated with very-large-
scale-integration technologies in ultralow-power nanoelectronics ap-
plications. To employ the ferroelectric material’s negative capacitance
effect, it must rst be stabilized in the NC state by connecting it in series
with the gate dielectric [48]. In the design of NC devices, capacitance
matching is critical. The thickness of ferroelectric material must be
chosen in such a way that it enables the best performance of the device
while also meeting the condition in Eq. (12). The device performance
suffers as a result of the capacitance mismatch. The solid black line in
Fig. 5. represents the capacitance characteristics for the baseline het-
erostructure without NC effect, and Fig. 5 also claries that the HZO
thickness below 8 nm doesn’t violate the condition mentioned in Eq.
(12). The dashed lines for HZO thickness greater than 8 nm create an
intersection between CFE and CMOS where |CFE|<CMOS . That indicates
that 8 nm HZO thickness is the critical thickness above which hysteresis
may take place.
To get the maximum performance out of the device, it should not be
operated in a hysteretic manner [45]. Hence, HZO thicknesses more
than 8 nm are unsuitable for optimum device performance because they
introduce hysteretic activity. According to Eq. (17), the optimal capac-
itance matching for 8 nm HZO thickness results in the lowest body
factor. As a consequence, the non-hysteretic behavior of the device
provides the lowest SS possible, making the body factor as small as
possible. Fig. 6 depicts the transfer characteristics of the proposed het-
erostructure TFET, which uses the HZO ferroelectric material as the
device gate stack. The transfer characteristics for the baseline hetero-
structure without NC effect are shown in Fig. 6 by the black dotted line.
The four solid lines demonstrate the non-hysteretic behavior of the de-
vice when the HZO thickness varies from 2 to 8 nm. The critical thick-
ness of HZO for the proposed device is 8 nm. The device will be
destabilized over this value, resulting in hysteretic functioning because
the condition in Eq. (12) is violated when the ferroelectric thickness
exceeds critical thickness. The hysteretic activity reduces its perfor-
mance of the device, which is not desirable at all [49]. Assume that the
ferroelectric material in the NC area is unstable. In that situation, the
device will exhibit hysteretic activity, and the ferroelectric material will
be unable to amplify the gate voltage efciently. The dashed lines in
Fig. 6 depict the hysteretic behavior when its thickness exceeds the
critical thickness, which might result in drain current deviation. Thus, it
can be stated that an HZO thickness of 8 nm, which is crucial for the
proposed device conguration, ensuring the optimal performance. The
8 nm HZO layer in the gate stack helps to achieve I
ON
/I
OFF
in the order of
10
12
, suppressing the I
ON
/I
OFF
observed in the baseline heterostructure.
The SS characteristics for nanoelectronics operation are presented in
Fig. 7. The SS characteristic for the baseline heterostructure is shown as
a solid black line, with the lowest SS of 21.94 mV/dec. Boltzmann sta-
tistics limit the transport factor (n) of typical MOSFETs to 60 mV/dec at
300 K. Using BTBT of carriers as the transport mechanism, the transport
factor is lowered in baseline heterostructure to yield SS less than 60 mV/
dec. When 8 nm HZO thickness is used as a gate insulator in the pro-
posed device, the lowest SS is 17.37 mV/dec for non-hysteretic opera-
tion. The device SS is further reduced by the NC effect of ferroelectric
Fig. 4. Simulation results for the baseline dual source GaSb/InGaAsSb/InAs
heterostructure based vertical TFET for three different drain voltages.
Fig. 5. Capacitance matching for the proposed device by comparing MOS
capacitance (C
MOS) and FE capacitance (CFE) in terms of charge density. The
intersect of black and red lines indicates the optimal HZO thickness, which is 8
nm. (For interpretation of the references to colour in this gure legend, the
reader is referred to the web version of this article.)
Fig. 6. log
10
(I
d
) vs. V
g
characteristics demonstrating hysteretic and non-
hysteretic operation of the proposed dual source negative capacitance GaSb/
InGaAsSb/InAs heterostructure based vertical TFET for various HZO
thicknesses.
M.U. Sohag et al.

Results in Physics 29 (2021) 104796
6
material, which reduces the body factor (m) to less than a unit. The
threshold voltage before and after applying the NC effect to the proposed
device is shown in Fig. 8. The threshold voltage for baseline structure is
0.65 V, which is reduced by 57.69 % when the HZO ferroelectric ma-
terial is used as the gate dielectric. The gure also demonstrates that
after applying the NC effect to the device, the on-state current observed
for baseline heterostructure is raised tenfold. The obtained results from
the proposed device are compared to those of previously reported homo-
and hetero-structure based classical TFETs in Table 1.. It can be
concluded from Fig. 8 and Table 1 that the NC effect of the ferroelectric
material contributes in boosting the overall performance of the proposed
device.
Conclusions
Dual source negative capacitance GaSb/InGaAsSb/InAs
heterostructure-based vertical TFET with a good on-state current and
great subthreshold swing is presented in the paper. In the proposed
vertical TFET, dual-source doubles the tunneling area. The use of low
bandgap materials in the heterostructure of vertical TFETs increases on-
state current. The baseline structure has the smallest subthreshold swing
of 21.94 mV/dec and an on–off current ratio of 4.3267 ×10
11
. For the
baseline structure, the threshold voltage was 0.65 V. The ferroelectric
material’s negative capacitance effect improves semiconductor device
performance. The on-state current is ten times higher after integrating
ferroelectric material HZO in the gate stack of the baseline construction,
and the threshold voltage is 0.275 V. Using the negative capacitance
effect of ferroelectric material HZO, a lowest subthreshold swing of
17.37 mV/dec and a good on–off current ratio in the order of 10
12
were
discovered. As a result of the ndings, the proposed device is a potential
device for future ultralow-power applications and technology.
CRediT authorship contribution statement
Minhaz Uddin Sohag: Conceptualization, Methodology, Software,
Data curation. Md. Sherajul Islam: Writing – original draft, Visualiza-
tion, Investigation, Supervision, Software, Validation. Kamal Hosen:
Writing - review & editing. Md. Al Imran Fahim: Writing - review &
editing. Md. Mosarof Hossain Sarkar: Writing - review & editing.
Jeongwon Park: Writing - review & editing.
Declaration of Competing Interest
The authors declare that they have no known competing nancial
interests or personal relationships that could have appeared to inuence
the work reported in this paper.
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