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BDD-based synthesis approach for in-memory logic realization utilizing Memristor Aided loGIC (MAGIC)
Abstract
In-Memory computation has received considerable attention in the light of recent advances made in the memristor-based design. Non-volatile memristor devices are compatible with both the crossbar structure, CMOS technology, and can perform logical operations when subjected to suitable voltages. In this work, a generalized synthesis technique is presented to implement the logic functions inside pure memristive-crossbar. To initiate the process, two novel memristive-designs are proposed for 2:1 multiplexer (MUX) that follow Memristor Aided loGIC (MAGIC) design style. Experimental results showed that each design is at least 68.05 %, 35.92 % more energy-efficient than their existing IMPLY, MAGIC-based designs, respectively. One of our proposed MUX designs is optimized in memristor-count, and the other is latency-optimized. The latency-optimized design offers 20 % improvement in performance compared to its existing IMPLY, MAGIC-based peers. Based on the simulation methodology presented in this work, the memristive-MUXes are simulated in Cadence Virtuoso. Subsequently, our proposed MUX designs are used for the technology mapping of the nodes of the Binary Decision Diagrams (optimized in terms of node, path counts) for the logic functions. Our proposed technique optimizes the implemented logic circuits in terms of memristor-count, step-count, and provides the details for – latency, required memristors, energy, area. Comparison of the synthesis results showed that the circuits generated using our proposed MAGIC-MUXes, are at least 82.21 %, 44 % more energy-efficient, and can offer 18.94 %, 18.92 % more performance-improvements than their peers, realized using the existing IMPLY, MAGIC-MUX designs, respectively. Also, our proposed-MUX based circuits need at least 56.73 % lesser crossbar-areas than their existing MAGIC-MUX based peers, which indicates the scope for large scale parallel processing inside a given memristive-memory.
Instead of the von Neumann architecture, logic-in-memory (LIM) provides a revolutionary approach to promoting computing efficiency. Based on the earlier work of complete LIM 16 Boolean logics, this article describes a memristor-based multiplexer (MUX) efficiently realized using a voltage/resistor-input-resistor-output (V/R-R) logic method, despite the fact that MUX is one of complicated logics in the design of VLSI circuits. Following that, a unique 2-1 MUX is further created by merging destructive resistor-input-resistor-output (R-R) logic with V/R-R logic, resulting in further device reduction. The 2-1 MUX only requires 3–4 memristors and four steps. Furthermore, the technique can be implemented for a 4-1 MUX using seven memristors and ten steps. Tests and simulations validated their feasibility and correctness. The effect of resistor due to the flip voltage variation on the computation accuracy is further analyzed, and the cascaded serial scheme of the MUX is finally presented.
In this manuscript, recent progress in the area of resistive random access memory (RRAM) technology which is considered one of the most standout emerging memory technologies owing to its high speed, low cost, enhanced storage density, potential applications in various fields, and excellent scalability is comprehensively reviewed. First, a brief overview of the field of emerging memory technologies is provided. The material properties, resistance switching mechanism, and electrical characteristics of RRAM are discussed. Also, various issues such as endurance, retention, uniformity, and the effect of operating temperature and random telegraph noise (RTN) are elaborated. A discussion on multilevel cell (MLC) storage capability of RRAM, which is attractive for achieving increased storage density and low cost is presented. Different operation schemes to achieve reliable MLC operation along with their physical mechanisms have been provided. In addition, an elaborate description of switching methodologies and current voltage relationships for various popular RRAM models is covered in this work. The prospective applications of RRAM to various fields such as security, neuromorphic computing, and non-volatile logic systems are addressed briefly. The present review article concludes with the discussion on the challenges and future prospects of the RRAM.
This paper presents a path balancing technology mapping algorithm, which is a new algorithm for generating a mapping solution for a given Boolean network such that the average logic level difference among fanin gates of each gate in the network is minimized. Path balancing technology mapping is required in dc-biased Single Flux Quantum (SFQ) circuits for guaranteeing the correct operation, and it is beneficial in CMOS circuits to reduce the hazard issues. We present a dynamic programming based algorithm for path balancing technology mapping which generates optimal solutions for dc-biased SFQ (e.g. Rapid SFQ or RSFQ) circuits with tree structure and acts as an effective heuristic for circuits with general Directed Acyclic Graph (DAG) structure. Experimental results show that our path balancing technology mapper reduces the balancing overhead by up to 2.7× and with an average of 21% compared to the state-of-the-art academic technology mappers.
A one-step sneak-path free read scheme for resistive crossbar memory is proposed in this article. During read operation, it configures the crossbar array into a four-terminal resistance network, which is composed of the selected cell and three other resistors corresponding to unselected cells that contribute to the sneak-path. Two sensing voltages with equal potential are applied to three terminals of the network. One is for sensing the resistance of the selected cell; the other is for creating zero-voltage drop across one of the three resistors, which connects the sneak-path to the selected cell. This effectively suppresses the current injected by the sneak-path to the selected cell-sensing loop. This work also proposes a cost-effective data-encoding circuit that guarantees that at least half of the memory cells are in a high-resistance state, which further minimizes sneak-path current. The impact of key design parameters, such as sensing voltage, switch on-resistance, and the ratio of memory cell resistances in different states, as well as nonideal effects are investigated. Equations for estimating the maximum array size to share a single read circuit are derived. The effectiveness of the proposed design has been validated via circuit simulations. Impacts of the word-/bit-line resistance are also analyzed.
As the CMOS technology is gradually scaling down to inherent physical device limits, significant challenges emerge related to scalability, leakage, reliability, etc. Alternative technologies are under research for next-generation VLSI circuits. Memristor is one of the promising candidates due to its scalability, practically zero leakage, non-volatility, etc. This paper proposes a novel design methodology for logic circuits targeting memristor crossbars. This methodology allows the optimization of the design of logic function, and their automatic mapping on the memristor crossbar. More important, this methodology supports the execution of Boolean logic functions within constant number of steps independent of its functionality. To illustrate the potential of the proposed methodology, multi-bit adders and multipliers are explored; their incurred delay, area and energy costs are analyzed. The comparison of our approach with state-of-the-art Boolean logic circuits for memristor crossbar architecture shows significant improvement in both delay (4 to 500×) and energy consumption (1.22 to 3.71×). The area overhead may decrease (down to 44%) or increase (up to 17%) depending on the circuit's functionality and logic optimization level.
Memristors are novel electrical devices used for a variety of applications, including memory, logic circuits, and neuromorphic systems. Memristive technologies are attractive due to their nonvolatility, scalability, and compatibility with CMOS. Numerous physical experiments have shown the existence of a threshold voltage in some physical memristors. Additionally, as shown in this brief, some applications require voltage-controlled memristors to operate properly. In this brief, a Voltage ThrEshold Adaptive Memristor (VTEAM) model is proposed to describe the behavior of voltage-controlled memristors. The VTEAM model extends the previously proposed ThrEshold Adaptive Memristor (TEAM) model, which describes current-controlled memristors. The VTEAM model has similar advantages as the TEAM model, i.e., it is simple, general, and flexible, and can characterize different voltage-controlled memristors. The VTEAM model is accurate (below 1.5% in terms of the relative root-mean-square error) and computationally efficient as compared with existing memristor models and experimental results describing different memristive technologies.
One of the most critical challenges for today’s and future data-intensive and big-data problems is data storage and analysis. This paper first highlights some challenges of the new born Big Data paradigm and shows that the increase of the data size has already surpassed the capabilities of today’s computation architectures suffering from the limited bandwidth, programmability overhead, energy inefficiency, and limited scalability. Thereafter, the paper introduces a new memristor-based architecture for data-intensive applications. The potential of such an architecture in solving data-intensive problems is illustrated by showing its capability to increase the computation efficiency, solving the communication bottleneck, reducing the leakage currents, etc. Finally, the paper discusses why memristor technology is very suitable for the realization of such an architecture; using memristors to implement dual functions (storage and logic) is illustrated.
Memristors are new passive circuit elements with interesting non-linear, analog, and memory properties that can be harnessed for various forms of computations. Compared to other circuit elements, including transistors, memristors have a smaller form factor, and thus have the potential for higher integration. While memristors so far have been used mainly for neuromorphic computation and for memories, we show in this paper that they can be integrated elegantly into existing design automation tools to perform digital computations by using K-maps to synthesize arbitrary Boolean functions. We demonstrate how the generated output is post processed and introduce memristor-specific area and delay constraints. We also evaluate the performance of our proposed approach with a set of benchmarks. Our results are relevant to the use of memristive devices to perform classical digital logic.
In light of the increased awareness of global energy consumption, questions are being asked about the energy contribution of computing equipment. Al-though studies have documented the share of energy consumption by this type of equipment over the years, research has rarely characterized the increas-ing share contributed by the rapidly growing segment of portable, pervasive computing devices. Portable computing is widely predicted to be a dominant mode of computing and communication in the future, and accounting for its energy consumption is necessary to develop efficient practices. This work takes a fresh and updated look at energy consumption as the result of com-puting devices with regard to global consumption, and pays special attention to the contribution of portable computing devices. We further quantify the impact of energy consumed by the computing sector on the environment, and the cost of electricity for an average residential consumer. Finally, based on the results of this study, we provide recommendations for the computer networking community for sustainable portable/mobile computing.
Memristors are novel devices, useful as memory at all hierarchies. These devices can also behave as logic circuits. In this paper, the IMPLY logic gate, a memristor-based logic circuit, is described. In this memristive logic family, each memristor is used as an input, output, computational logic element, and latch in different stages of the computing process. The logical state is determined by the resistance of the memristor. This logic family can be integrated within a memristor-based crossbar, commonly used for memory. In this paper, a methodology for designing this logic family is proposed. The design methodology is based on a general design flow, suitable for all deterministic memristive logic families, and includes some additional design constraints to support the IMPLY logic family. An IMPLY 8-bit full adder based on this design methodology is presented as a case study.
Memristive devices are novel structures, developed primarily as memory. Another interesting application for memristive devices is logic circuits. In this paper, MRL (Memristor Ratioed Logic) - a hybrid CMOS-memristive logic family - is described. In this logic family, OR and AND logic gates are based on memristive devices, and CMOS inverters are added to provide a complete logic structure and signal restoration. Unlike previously published memristive-based logic families, the MRL family is compatible with standard CMOS logic. A case study of an eight-bit full adder is presented and related design considerations are discussed.
Memristive devices are electrical resistance switches that can retain a state of internal resistance based on the history of applied voltage and current. These devices can store and process information, and offer several key performance characteristics that exceed conventional integrated circuit technology. An important class of memristive devices are two-terminal resistance switches based on ionic motion, which are built from a simple conductor/insulator/conductor thin-film stack. These devices were originally conceived in the late 1960s and recent progress has led to fast, low-energy, high-endurance devices that can be scaled down to less than 10 nm and stacked in three dimensions. However, the underlying device mechanisms remain unclear, which is a significant barrier to their widespread application. Here, we review recent progress in the development and understanding of memristive devices. We also examine the performance requirements for computing with memristive devices and detail how the outstanding challenges could be met.
The search for new nonvolatile universal memories is propelled by the need for pushing power-efficient nanocomputing to the next higher level. As a potential contender for the next-generation memory technology of choice, the recently found "the missing fourth circuit element", memristor, has drawn a great deal of research interests. In this paper, we characterize the fundamental electrical properties of memristor devices by encapsulating them into a set of compact closed-form expressions. Our derivations provide valuable design insights and allow a deeper understanding of key design implications of memristor-based memories. In particular, we investigate the design of read and write circuits and analyze data integrity and noise-tolerance issues.
A mathematical model of the prototype of memristor, manufactured in 2008 in Hewlett-Packard Labs, is described in the paper. It is shown that the hitherto published approaches to the modeling of boundary conditions need not conform with the requirements for the behavior of a practical circuit element. The described SPICE model of the memristor is thus constructed as an open model, enabling additional modifications of non-linear boundary conditions. Its functionality is illustrated on computer simulations.
We present a technique to derive fully testable circuits under the stuck-at fault model (SAFM) and the path-delay fault model (PDFM). Starting from a function description as a binary decision diagram, the netlist is generated by a linear time mapping algorithm. Only one additional input and one inverter are needed to achieve 100% testable circuits under SAFM and PDFM. Experiments are given to show the advantages of the technique.
Memristors have gained increasing interest recently as emerging memory technologies. Their unique ability to perform logic operations within the memory makes them even more attractive. MAGIC NOR is one such logic gate that can be integrated within memristive memory cells, thus opening possibilities for real in-memory computing. This paper explores the integration of MAGIC NOR gates within large-scale memory crossbar arrays. We evaluate both analytically and numerically different non-ideality parameters that influence the logic gate performance. First, we investigate the effect of parasitic resistance and capacitance within the memory array. Then, process and device variations are considered and modeled, as well as environmental conditions such as temperature and power supply variations. These non-idealities are formulated in the form of process corners that enable designers to estimate the effect of variations on their design in worst case scenarios, similar to the manner in which such effects are estimated in CMOS-based VLSI design.
‘Computations inside Memory’ has become a latest area of research as ‘memory with computing skills’ accelerates
the chances of developing ‘beyond-Von Neumann machines’, that is believed to be advantageous in terms of
performance and energy-efficiency. ‘Memristors’ are considered as potential devices for building such memories,
as they are highly dense, non-volatile scalable devices with faster switching times and lower energy dissipation
and are also compatible with the existing CMOS-technology. Additionally, memristors fit in crossbar structure and
can perform logic-computations, when different voltages are applied across them. Previously, various synthesis
works have been reported for logic realization using memristors. But logic blocks, implemented using synthesis
tools, are not always completely optimized. In this context, we present the alternative memristive-designs for the
two most commonly used digital units—Delay (D) and Toggle (T) flip-flops. The proposed designs are based on
Memristor Aided loGIC (MAGIC) design style and are specific to crossbar-based pure memristive-memories. A
relevant simulation methodology is presented for simulating the proposed MAGIC-designs of D and T flip-flops in
Cadence Virtuoso. Comparison with the existing designs of D, T flip-flops (using IMPLY) revealed that both the
proposed D, T flip-flops are more performance-efficient (by 28.571%, 20% respectively) and more energy-efficient
(by 83.873%, 82.905% respectively) than their corresponding IMPLY-peers. Also, the proposed D, T flip-flops are
found to use reduced crossbar areas (by 46.667%, 45% respectively) relative to their counterparts generated using
a recent synthesis technique, which makes the designs suitable for massive parallel executions inside memristive-memories
of any size.
We propose a technique for the analysis of manufacturing yield of nano-crossbar for the different values of defect percentage and crossbar-size. We provide an estimate of the minimum-size crossbar to be fabricated, wherein a defect-free crossbar of a given size can always be found with a guaranteed yield. Our technique is based on logical merging of two defective rows (or two columns) that emulate a defect-free row (or column). The proposed technique easily handles both the stuck-open and stuck-closed faults. Experimental results show that the proposed method provides higher defect-tolerance compared to that of previous techniques.
Memristors have drawn the attention of researchers due to their unique non-volatile and logic design capabilities.
Combining these two, a concept called in-memory computing has emerged, wherein the same memory unit is
used for both storage and computation, which helps in overcoming the CPU-memory bottleneck in conventional
processor architectures. In this paper, we propose a look-ahead strategy for Boolean functions using Memristor
Aided LoGIC (MAGIC) design style in the memristive crossbar, which supports in-memory computing. First, the
Boolean function is converted into a netlist of NOT and NOR gates using a logic synthesis tool. The proposed
crossbar mapping tool then maps the gate netlist to the crossbar, and also generates the micro-operations needed
to execute the gate operations. Experimental evaluation on ISCAS ′ 85 benchmarks reports average improvements
of 37.02%, 36.55%, 64.99% and 35.55% respectively in terms of memristor count, latency, crossbar size, and
energy over a recently published work. Results were also reported for IWLS-2005 benchmarks.
We introduce a new computer-aided design approach based on Free Binary Decision Diagrams (FBDDs) for implementing Boolean functions on crossbars using flow-based computing. Our crossbar synthesis procedure uses generalized FBDDs to design crossbars for a Boolean formula such that there is a flow of current from an input nanowire to an output nanowire through the sneak paths in the crossbar if and only if the Boolean formula evaluates to true. Generalized FBDDs are more succinct representations of Boolean formulae than traditional Reduced Ordered Binary Decision Diagrams (ROBDDs) because they do not require the same variable ordering along all paths of the decision diagram. Our experimental results with the middle bit of a multiplier show that our designs are 69.9% more succinct than flow-based crossbar computing approaches designed using ROBDDs.
Using memristive devices within a crossbar array could pave the way for memories with higher density and speed than state-of-the-art Flash memory, while maintaining relatively low energy. However, memristive crossbar arrays have great difficulty distinguishing logical states because of sneak path currents. The row grounding technique eliminates the sneak path effect, allowing reliable sampling of the memristor state. In this paper, we analyze the row grounding technique and propose several methods and constraints for the design of memristive crossbar arrays. When the row grounding technique is used for these arrays, our analysis shows that increasing the number of rows can help reduce read latency and energy, in contrast to the case of capacitive memory arrays. Simulation results confirm the theoretical analysis proposed in this paper. Copyright
Because of their resistive switching properties and ease of controlling the resistive states, memristors have been proposed in nonvolatile storage as well as logic design applications. Memristors can be fabricated in a crossbar and suitable voltages applied to the row and column nanowires to control their states. This makes it possible to move toward new non-von Neumann-type architectures, usually referred to as in-memory computing, where logic operations can be performed directly on the storage fabric. In this paper, a scalable design flow for in-memory computing has been proposed, where a given multioutput logic function is synthesized as a netlist of NOT/NOR gates and then mapped to the crossbar using the Memristor-Aided loGIC (MAGIC) design style. The memristors corresponding to the primary inputs are initialized a priori. Subsequently, the required gate operations are performed by applying suitable row and column voltages in sequence. Two alternate mapping schemes have been analyzed. The switching characteristics of MAGIC NOR gates have been evaluated using circuit simulation under the Cadence Virtuoso environment. Experimental evaluation on ISCAS'85 benchmarks reports the average improvements of 27.7%, 34.6%, and 26.2%, respectively over a recently published work with respect to the number of memristors, number of cycles, and total energy dissipation, respectively. It may be noted that the energy consumption of the gates used in the proposed approach (NOT) and (NOR) is significantly higher than that using CMOS technology.
Design of non-volatile in-memory computing devices has attracted high attention to Resistive Random Access Memories (RRAMs). We present a comprehensive approach for the synthesis of resistive in-memory computing circuits using Binary Decision Diagrams (BDDs), And-Inverter Graphs (AIGs), and the recently proposed Majority-Inverter Graphs (MIGs) for logic representation and manipulation. The proposed approach allows to perform parallel computing on a multi-row crossbar architecture for the logic representations of the given Boolean functions throughout a level-by-level implementation methodology. It also provides alternative implementations utilizing two different logic operations for each representation, and optimizes them with respect to the number of RRAM devices and operations, addressing area and delay, respectively. Experiments show that upper bounds of the aforementioned cost metrics for the implementations obtained by our synthesis approach are considerably improved in comparison with the corresponding existing methods in both area and especially latency.
Modern computers suffer from a growing disparity of speed between processor and memory which significantly limits their performance. Additionally, as the number of transistors per chip continues to increase, the operating frequency stabilizes due to the power considerations. One of the leading solutions to these issues is to reduce data transfer by adding processing capabilities into the memory itself. For data-intensive applications, this means a significant improvement in processing capabilities by saving a significant amount of time and energy. Although all the attempts to implement this solution so far were unsuccessful, emerging nonvolatile resistive memory technologies (namely, memristors) offer an opportunity for developing a Memory Processing Unit (MPU) based on a technique called ‘stateful logic’. The MPU allows adding processing capabilities to the memristive memory cells, thus enabling novel non-von Neumann architectures. The processing within the MPU relies on a sequence of logical operations. This paper presents the design of an MPU controller for executing in-memory computation. Different design techniques to execute processing and storing data within the MPU are described. The MPU controller has been designed and implemented in a VHDL environment and used to execute different operations within the MPU.
‘Memristor’ is a new emerging nanodevice that is gaining a lot of appreciation from the researchers these days. They possess dual properties of resistor, memory and find immense application in the fields of nanoelectronic circuit and memory designs. Material implication logic is applied in memristor-based circuit designs as it can be performed easily using two memristors and one resistor.
In this paper a memristor-based T (toggle) flip-flop is implemented using material implication logic. Thereby this T flip-flop is employed in designing an Up-Down counter, based on the implication operations using memristors. The designs thus presented for the T flip-flop and counter need 6, 16 memristors respectively. Memristor technology being highly dense, our counter design will occupy lesser area as compared to its conventional CMOS-based design. Also the proposed T flip flop takes 11 computation steps to generate its outputs and 52 steps are needed by the Up-Down counter to perform its operation. Moreover in our memristor-based counter circuit, counting can be started, stopped and resumed at any desired logic states by simply controlling the externally applied voltages.
Memristor is a new nanoelectronic device that has become very popular at recent times for its non-volatility, better alignment and excellent scalability properties. Various research works are going on designing of logic circuits, digital memory and neuromorphic systems using this nano device. Both pure and hybrid approaches are followed for the design purpose. Material implication logic brings in the motivation for exploring memristors in the area of logic design.
In this work material implication logic has been applied to design complex combinational circuits like demultiplexer, encoder, priority encoder, decoder and magnitude comparator using memristors. Both serial and parallel approaches have been used for the design purpose and the parallel implementations require lesser step counts than their serial counterparts. Also the designs presented occupy lesser area than their conventional CMOS-peers.
In a memristor crossbar array, functioning as a memory array, a memristor is positioned on each row–column intersection, and its resistance, low or high, represents two logical states. The state of every memristor can be sensed by the current flowing through the memristor. In this paper, we study the sneak path problem in crossbar arrays, in which current can sneak through other cells, resulting in reading a wrong state of the memristor. Our main contributions are modeling the error channel induced by sneak paths, a new characterization of arrays free of sneak paths, and efficient methods to read the array cells while avoiding sneak paths. To each read method, we match a constraint on the array content that guarantees sneak-path free readout, determine the resulting capacity, and provide an efficient encoder that achieves the capacity.
Realizing logic operations within passive crossbar memory arrays is a promising approach to enable novel computer architectures, different from conventional von Neumann architecture. Attractive candidates to enable such architectures are memristors, nonvolatile memory elements commonly used within a crossbar, that can also perform logic operations. In such novel architectures, data are stored and processed within the same entity, which we term as memristive memory processing unit (MPU). In this paper, Memristor-Aided loGIC (MAGIC) family is discussed with various design considerations and novel techniques to execute logic within an MPU. We present a novel resistive memory - the transpose memory, which adds additional functionality to the memristive memory, and compare it with a conventional memristive memory. A case study of an adder is presented to demonstrate the design issues discussed in this paper. We compare the proposed design techniques with the memristive IMPLY logic in terms of speed, area, and energy. Our evaluation shows that the proposed MAGIC design is 2.4 × faster and consumes 66.3% less energy as compared with the IMPLY-based computing for N-bit addition within memristive crossbar memory. Additionally, we compare the proposed design with IMPLY logic family on ISCAS-85 benchmarks, which shows significant improvements in speed (2×) and energy (10 ×), with similar area.
We present a Boolean logic optimization framework based on Majority-Inverter Graph (MIG). An MIG is a directed acyclic graph consisting of three-input majority nodes and regular/complemented edges. Current MIG optimization is supported by a consistent algebraic framework. However, when algebraic methods cannot improve a result quality, stronger Boolean methods are needed to attain further optimization. For this purpose, we propose MIG Boolean methods exploiting the error masking property of majority operators. Our MIG Boolean methods insert logic errors that strongly simplify an MIG while being successively masked by the voting nature of majority nodes. Thanks to the data-structure/methodology fitness, our MIG Boolean methods run in princIPle as fast as algebraic counterparts. Experiments show that our Boolean methodology combined with state-of-art MIG algebraic techniques enable superior optimization quality. For example, when targeting depth reduction, our MIG optimizer transforms a rIPple carry adder into a carry look-ahead one. Considering the set of IWLS'05 (arithmetic intensive) benchmarks, our MIG optimizer reduces by 17.98% (26.69%) the logic network depth while also enhancing size and power activity metrics, with respect to ABC academic optimizer. Without MIG Boolean methods, i.e., using MIG algebraic optimization alone, the previous gains are halved. Employed as front-end to a delay-critical 22-nm ASIC flow (logic synthesis + physical design) our MIG optimizer reduces the average delay/area/power by (15.07%, 4.93%, 1.93%), over 27 academic and industrial benchmarks, as compared to a leading commercial ASIC flow.
Very recently a new passive circuit element called memristor has been extensively investigated by researchers, which can be used for a variety of applications. This two-terminal device having few nanometer dimensions has been experimentally shown to possess both memory and resistor properties. This has also received great attention due to the fact that these devices can very easily be integrated on CMOS subsystems. Most of the logic design works in this context are based on material implication operation which can be very efficiently implemented using memristors. In this paper we propose an efficient realization of 2-to-1 multiplexer using memristors, and hence present a synthesis methodology that represents a given Boolean function as a Reduced Ordered Binary Decision Diagram (ROBDD) and then maps the same to memristor implementation.
Binary Decision Diagrams (BDDs) are widely used in electronic design automation and formal verification. BDDs are a canonical representation of Boolean functions with respect to a variable ordering. Finding a variable ordering resulting in a small number of nodes and paths is a primary goal in BDD optimization. There are several approaches minimizing the number of nodes or paths in BDDs, but yet no method has been proposed to minimize both objectives at the same time.
In this paper, BDD optimization is carried out as a bi-objective problem using two aforementioned criteria. For this purpose, we have exploited NSGA-II which has been proven to fit problems with a small number of objectives. Furthermore, the algorithm is facilitated with an objective priority scheme that allows to incorporate preference to one of the objectives.
Experimental results show that our multi-objective BDD optimization algorithm has achieved a good trade-off between the number of nodes and the number of paths. Comparison of the results obtained by applying priority to the number of nodes or paths with node and path minimization techniques demonstrates that the proposed algorithm can find the minimum of the preferred objective in most cases as well as lowering the other objective simultaneously.
Binary Decision Diagrams (BDDs) are widely used in electronic design automation and formal verification. BDDs are a canonical representation of Boolean functions with respect to a variable ordering. Finding a variable ordering resulting in a small number of nodes and paths is a primary goal in BDD optimization. There are several approaches minimizing the number of nodes or paths in BDDs, but yet no method has been proposed to minimize both objectives at the same time.
In this paper, BDD optimization is carried out as a bi-objective problem using two aforementioned criteria. For this purpose, we have exploited NSGA-II which has been proven to fit problems with a small number of objectives. Furthermore, the algorithm is facilitated with an objective priority scheme that allows to incorporate preference to one of the objectives.
Experimental results show that our multi-objective BDD optimization algorithm has achieved a good trade-off between the number of nodes and the number of paths. Comparison of the results obtained by applying priority to the number of nodes or paths with node and path minimization techniques demonstrates that the proposed algorithm can find the minimum of the preferred objective in most cases as well as lowering the other objective simultaneously.
Our challenge is clear: The drive for performance and the end of voltage scaling have made power, and not the number of transistors, the principal factor limiting further improvements in computing performance. Continuing to scale compute performance will require the creation and effective use of new specialized compute engines, and will require the participation of application experts to be successful. If we play our cards right, and develop the tools that allow our customers to become part of the design process, we will create a new wave of innovative and efficient computing devices.
This brief proposes a circuit structure that performs a stateful logic operation on memristor memory based on a nanocrossbar. Through analysis and comparison of multiple schemes, achievable circuit condition is demonstrated, and the feasibility of the duplication operation is proved. The proposed circuit structure provides the memory with the function of in situ logic operation and thus can potentially reduce the amount of memory accessing actions and provide a possible solution to the memory wall problem.
We propose a concept of magnetic logic circuits engineering, which takes an advantage of magnetization as a computational state variable and exploits spin waves for information transmission. The circuits consist of magneto-electric cells connected via spin wave buses. We present the result of numerical modeling showing the magneto-electric cell switching as a function of the amplitude as well as the phase of the spin wave. The phase-dependent switching makes it possible to engineer logic gates by exploiting spin wave buses as passive logic elements providing a certain phase-shift to the propagating spin waves. We present a library of logic gates consisting of magneto-electric cells and spin wave buses providing 0 or π phase shifts. The utilization of phases in addition to amplitudes is a powerful tool which let us construct logic circuits with a fewer number of elements than required for CMOS technology. As an example, we present the design of the magnonic Full Adder circuit comprising only 5 magneto-electric cells. The proposed concept may provide a route to more functional wave-based logic circuitry with capabilities far beyond the limits of the traditional transistor-based approach.
Progress of carbon nanotube (CNT) research and development in terms of published papers and patents is reported. Developments concerning CNT structures, synthesis, and major parameters, in terms of the published documents are surveyed. Publication growth of CNTs and related fields are analyzed for the period of 2000–2010. From the explored search term, “carbon nanotubes”, the total number of papers containing the CNT concept is 52,224, and for patents is 5,746, with a patent/paper ratio of 0.11. For CNT research in the given period, an annual increase of 8.09% for paper and 8.68% for patents are resulted. Published papers for CNT, CVD and CCVD synthesis parameters for the period of 2000–2010 are compared. In other research, publications for CNT laser synthesis, for the period of 2000–2010, are reviewed. Publications for major laser parameters in CNT synthesis for the period of 2000–2010 are described. The role of language of the published references for CNT research for the period of 2000–2010 is also investigated. Published papers/patents in English, Japanese, Chinese, Russian, German, French, Polish, and Spanish languages are compared. As expected, the number of paper/patent publications in English dominates other languages.
Memristor was realized as physical device recently by HP labs, this discovery spurred a great interest in memristors as a fundamental electronic element. Memristor-based technology provides much better scalability, higher utilization when used as memory, and overall lower energy consumptions compared to traditional CMOS technology. The contribution of this paper is a detailed study of the non-linear model of the Memristor. This modeling is used to recognize the time and the voltage characteristics of stable read and write operations, and the tradeoffs between the various design parameters such as voltage, frequency, noise margin, and area. Based on this modeling we propose a hybrid CMOS-Memristor memory cell and architecture that deliver the speed of an SRAM and the density of DRAM with no wasted leakage power in the storage.
Cross-point memory architecture offers high device density, yet it suffers from substantial sneak path leakages, which result in large power dissipation and a small sensing margin. The parasitic resistance associated with the interconnects further degrades the output signal and imposes an additional limitation on the maximum allowable array size. In this paper, we study the device requirements of a resistive cross-point memory array under the worst-case write and read operations. We focus on the data pattern dependence of the memory array and compare the effect of the memory cell resistance values and resistance ratio for determining the maximum array size. The number of cells in the array can reach 10<sup>6</sup> with a signal swing > 50% of the reading voltage when R<sub>on</sub> is beyond 3 M and R<sub>off</sub>/R<sub>on</sub> is greater than 2. A large memory cell resistance value can further reduce the power consumption, obviate the need for a large R<sub>off</sub>/R<sub>on</sub> ratio, and avoid the inclusion of cell selection devices. The effect of the nonlinearity of the I -V characteristics of the memory cells is also investigated. The nonlinearity calls for a substantial tradeoff between the memory cell resistance values and the resistance ratio, and must be taken into consideration for the device design.
Researchers have claimed that the memristor, the fourth fundamental circuit element, can be used for computing. In this work, we utilize memristors as weights in the realization of low-power Field Programmable Gate Arrays (FPGAs) using threshold logic which is necessary not only for low power embedded systems, but also realizing biological applications using threshold logic. Boolean functions, which are subsets of threshold functions, can be implemented using the proposed Memristive Threshold Logic (MTL) gate, whose functionality can be configured by changing the weights (memristance). A CAD framework is also developed to map the weights of a threshold gate to corresponding memristance values and synthesize logic circuits using MTL gates. Performance of the MTL gates at the circuit and logic levels is also evaluated using this CAD framework using ISCAS-85 combinational benchmarking circuits. This work also provides solutions based on device options and refreshing memristance, against drift in memristance, which can be a potential problem during operation. Comparisons with the existing CMOS look-up-table (LUT) and capacitor threshold logic (CTL) gates show that MTL gates exhibit less energy-delay product by at least 90 percent.
For complex system-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumption. Managing and optimizing this important component of SoC power requires a detailed understanding of the characteristics of its power consumption. Various power estimation and low-power design techniques have been proposed for the global interconnects that form part of SoC communication architectures (e.g., low-swing buses, bus encoding, etc). While effective, they only address a limited part of communication architecture power consumption. A state-of-the-art communication architecture, viewed in its entirety, is quite complex, comprising several components, such as bus interfaces, arbiters, bridges, decoders, and multiplexers, in addition to the global bus lines. Relatively little research has focused on analyzing and comparing the power consumed by different components of the communication architecture. In this work, we present a systematic evaluation and analysis of the power consumed by a state-of-the-art communication architecture (the AMBA on-chip bus), using a commercial design flow. We focus on developing a quantitative understanding of the relative contributions of different communication architecture components to its power consumption, and the factors on which they depend. We decompose the communication architecture power into power consumed by logic components (such as arbiters, decoders, bus bridges), global bus lines (that carry address, data, and control information), and bus interfaces. We also perform studies that analyze the impact of varying application traffic characteristics, and varying SoC complexity, on communication architecture power. Based on our analyses, we evaluate different techniques for reducing the power consumed by the on-chip communication architecture, and compare their effectiveness in achieving power savings at the system level. In addition to quantitatively reinforcing the view that on-chip communication is an important target for system-level power optimization, our work demonstrates (i) the importance of considering the communication architecture in its entirety, and (ii) the opportunities that exist for power reduction through careful comm- unication architecture design.
There is intense interest in graphene in fields such as physics, chemistry, and materials science, among others. Interest in graphene's exceptional physical properties, chemical tunability, and potential for applications has generated thousands of publications and an accelerating pace of research, making review of such research timely. Here is an overview of the synthesis, properties, and applications of graphene and related materials (primarily, graphite oxide and its colloidal suspensions and materials made from them), from a materials science perspective.
Memory processing unit for in-memory processing
- Hur
R.B. Hur, S. Kvatinsky, Memory processing unit for in-memory processing, in:
Proceedings of the IEEE International Symposium on Nanoscale Architectures, July
2016.