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Logic and in-memory computing achieved in a single ferroelectric semiconductor transistor
Abstract
Exploring materials with multiple properties who can endow a simple device with integrated functionalities has attracted enormous attention in the microelectronic field. One reason is the imperious demand for processors with continuously higher performance and totally new architecture. Combining ferroelectric with semiconducting properties is a promising solution. Here, we show that logic, in-memory computing, and optoelectrical logic and non-volatile computing functionalities can be integrated into a single transistor with ferroelectric semiconducting α-In2Se3 as the channel. Two-input AND, OR, and non-volatile NOR and NAND logic operations with current on/off ratios reaching up to five orders, good endurance (1000 operation cycles), and fast operating speed (10 μs) are realized. In addition, optoelectrical OR logic and non-volatile implication (IMP) operations, as well as ternary-input optoelectrical logic and in-memory computing functions are achieved by introducing light as an additional input signal. Our work highlights the potential of integrating complex logic functions and new-type computing into a simple device based on emerging ferroelectric semiconductors.
... These semiconductors offer an ideal platform for in-memory computing 11 . Logic, memory and neuromorphic computing functions are realized in junctions [12][13][14] or transistors 6,10,11,[15][16][17][18] using the layered ferroelectric semiconductor as the channel. The multiple conductance states in these devices provide the physical basis for the integration of logic and memory 19 , in which case the implementation of precise conductivity modulation becomes essential. ...
... This insight is widely applicable to currently reported FeCFETs, such as α-In 2 Se 3 , InSe, Bi 2 O 2 Se (refs. 6,10,11,15,16,21) and AgSiP 2 Se 6 transistors 6,10,11,15,16,21 . ...
... This insight is widely applicable to currently reported FeCFETs, such as α-In 2 Se 3 , InSe, Bi 2 O 2 Se (refs. 6,10,11,15,16,21) and AgSiP 2 Se 6 transistors 6,10,11,15,16,21 . ...
Precise control of the conductivity of layered ferroelectric semiconductors is required to make these materials suitable for advanced transistor, memory and logic circuits. Although proof-of-principle devices based on layered ferroelectrics have been demonstrated, it remains unclear how the polarization inversion induces conductivity changes. Therefore, function design and performance optimization remain cumbersome. Here we combine ab initio calculations with transport experiments to unveil the mechanism underlying the polarization-dependent conductivity in ferroelectric channel field-effect transistors. We find that the built-in electric field gives rise to an asymmetric conducting route formed by the hidden Stark effect and competes with the potential redistribution caused by the external field of the gate. Furthermore, leveraging our mechanistic findings, we control the conductivity threshold in α-In2Se3 ferroelectric channel field-effect transistors. We demonstrate logic-in-memory functionality through the implementation of electrically self-switchable primary (AND, OR) and composite (XOR, NOR, NAND) logic gates. Our work provides mechanistic insights into conductivity modulation in a broad class of layered ferroelectrics, providing foundations for their application in logic and memory electronics.
... For example, wang et al. demonstrated a multifunctional FeFET that can integrate logic, memory computing, photoelectric logic, and non-volatile computing into a single transistor. The gate of this transistor can also be used as a signal input, showing the powerful potential of FeFET in synaptic devices 14 . ...
After more than a hundred years of development, ferroelectric materials have demonstrated their strong potential to people, and more and more ferroelectric materials are being used in the research of ferroelectric transistors (FeFETs). As a new generation of neuromorphic devices, ferroelectric materials have attracted people's attention due to their powerful functions and many characteristics. This article summarizes the development of ferroelectric material systems in recent years and discusses the simulation of artificial synapses. The mainstream ferroelectric materials are divided into traditional perovskite structure, fluorite structure, organic polymer, and new 2D van der Waals ferroelectricity. The principles, research progress, and optimization for brain like computers of each material system are introduced, and the latest application progress is summarized. Finally, the scope of application of different material systems is discussed, with the aim of helping people screen out different material systems based on different needs.
... Through the synergistic modulation of mechanical and optical signals, our optoelectronic synaptic transistors can conveniently switch to distinct logic functions and improve information processing capabilities. High-performance logic computation can be achieved with either electrical or optical inputs without building complex complementary metal oxide semiconductor circuits, [61,62] but mechanical-optical synergy provides a new avenue for multifunctional applications of interactive neuromorphic devices. The α-In 2 Se 3 synaptic transistor also simulates the classical Pavlovian conditioning experiment related to the associative learning process in the brain. ...
Inspired by biological neural networks, the fabrication of artificial neuromorphic systems with multimodal perception capacity shows promises in overcoming the “von Neumann bottleneck” and takes advantage of the efficient perception and computation of diverse types of signals. Here, we combine a triboelectric nanogenerator with an α‐phase indium selenide (α‐In2Se3) optoelectronic synaptic transistor to construct a tribo‐ferro‐optoelectronic artificial neuromorphic device with multimodal plasticity. Based on the excellent ferroelectric and optoelectronic characteristics of the α‐In2Se3 channel, typical synaptic behaviors (e.g., pair‐pulse facilitation and short‐term/long‐term plasticity) are successfully simulated in response to the synergistic effect of mechanical and optical stimuli. The interaction of mechanical displacement and light illumination enables heterosynaptic plasticity and spatiotemporal dynamic logic. Furthermore, multiple Boolean logical functions and associative learning behaviors are successfully implemented using the paired stimuli of displacement pulses and light pulses. The proposed tribo‐ferro‐optoelectronic artificial neuromorphic devices have great potential for application in interactive neural networks and next‐generation artificial intelligence.
... So far, most FSTs have been proposed based on ferroelectric materials such as PbZr x Ti 1−x O 3 (PZT) [17,18], poly(vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)) [19][20][21][22], and novel two-dimensional materials [23][24][25]. Conductance dynamic range (G max /G min ) larger than 20 and more than 100 conductance states have been achieved in these FSTs, by means of channel scaling [26], electrode altering [27], and 2D ferroelectric semiconductors [28][29][30], but tens-ofvolt and microsecond pulses are usually required for the programming process. ...
Benefiting from the nonvolatile and fast programming operations of ferroelectric materials, ferroelectric synaptic transistors (FSTs) are promising in neuromorphic computing. However, it is challenging to realize conductance with a large dynamic range (Gmax/Gmin) and multilevel states simultaneously under low energy consumption. Here, solution-processed indium oxide (In2O3) synaptic transistors gated by ferroelectric Hf0.5Zr0.5O2 (HZO) are proposed for the first time to address the above problems. Excellent synaptic characteristics were realized through the delicately regulated ferroelectric phase and good inhibition of charge injection in ferroelectric bulk and ferroelectric/semiconductor interface. Long-term potentiation/depression (LTP/D) up to 101 effective conductance states and excellent endurance (>1000 cycles) with large Gmax/Gmin = 32.2 were successfully mimicked under a low energy consumption of 490 fJ per spike event. Besides, the simulation achieved 96.5% recognition accuracy of handwriting digit, which is the highest record for existing FSTs. This work provides a new pathway for developing low-cost, high-performance, and energy-efficient FSTs.
... Recently, ferroelectric field-effect transistors (Fe-FETs) with nondestructive operation, nonvolatility, and high dense integration have attracted extensively interest as a promising building block for high-performance analog computing. [23][24][25][26] In a Fe-FET, ferroelectric materials are utilized as the gate insulators where the conductance of semiconductor can be modulated by the polarization switching of a ferroelectric dielectric layer under an external electrical field. The short retention time originated from the gate leakage current and depolarization field-induced charge trap is the main obstacle for the commercialization of Fe-FET. ...
To meet the requirement of data-intensive computing in the data-explosive era, brain-inspired neuromorphic computing have been widely investigated for the last decade. However, incompatible preparation processes severely hinder the cointegration of synaptic and neuronal devices in a single chip, which limited the energy-efficiency and scalability. Therefore, developing a reconfigurable device including synaptic and neuronal functions in a single chip with same homotypic materials and structures is highly desired. Based on the room-temperature out-of-plane and in-plane intercorrelated polarization effect of 2D α-In 2 Se 3 , we designed a reconfigurable hardware platform, which can switch from continuously modulated conductance for emulating synapse to spiking behavior for mimicking neuron. More crucially, we demonstrate the application of such proof-of-concept reconfigurable 2D ferroelectric devices on a spiking neural network with an accuracy of 95.8% and self-adaptive grow-when required network with an accuracy of 85% by dynamically shrinking its nodes by 72%, which exhibits more powerful learning ability and efficiency than the static neural network.
... fabrication process, the Raman spectrum of the channel was tested. As shown in Fig. 1(b), peaks observed at 104, 181 and 193 cm -1 are corresponding to the , and modes of α-In 2 Se 3 respectively, which is consistent with previous results [45,46]. This demonstrates the high crystalline quality of the channel material after device fabrication. ...
Detection of solar-blind ultraviolet (SB-UV) light is important in applications like confidential communication, flame detection, and missile warning system. However, the existing SB-UV photodetectors still show low sensitivities. In this work, we demonstrate the extraordinary SB-UV detection performance of α-In2Se3 phototransistors. Benefiting from the coupled semiconductor and ferroelectricity property, the phototransistor has an ultraweak detectable power of 17.85 fW, an ultrahigh gain of 1.2 × 106, a responsivity of 2.6 × 105 A/W, a detectivity of 1.3 × 1016 Jones and an ultralow noise-equivalent-power of 4.2 × 10−20 W/Hz1/2 for 275 nm light. Its performance exceeds most other UV detectors, even including commercial photomultiplier tubes and avalanche photodiodes. It can be also implemented as an optoelectronic synapse for neuromorphic computing. A 784×300×10 artificial neural network (ANN) based on this optoelectronic synapse is constructed and demonstrated with a high recognition accuracy and good noise-tolerance for the Fashion-MNIST dataset. These extraordinary features endow this phototransistor with the potential for constructing advanced SB-UV detectors and intelligent hardware.
... Ferroelectric materials attract intensive attentions due to their uniquely reversible polarization switching property and high dielectric performance, thus having promising applications in the energy harvesters, 1 nonvolatile memory devices 2,3 and novel multi-fields coupling electronic devices. 4,5 For example, tin-hypothiodiphosphate (Sn 2 P 2 S 6 ) is a nonoxide ferroelectric semiconductor with monoclinic Pn structure at room temperature. ...
Driven by the minimization of total energy, the multi-domain morphology is preferred in as-grown ferroelectrics to reduce the depolarization and strain energy during the paraelectric to ferroelectric phase transition. However, the complicated multi-domain is not desirable for certain high-performance ferroelectric electro-optic devices. In this work, we achieve a reproducible and stable large-area monodomain in as-grown bulk ferroelectric single crystal Sn2P2S6. The monodomain dominates the entire single crystal, which is attributed to the internal charge carriers from the photoexcited disproportionation reaction of Sn ions. The charge carriers effectively screen the depolarization field and therefore decrease the depolarization energy and facilitate the formation of monodomain. This work offers a potential approach for engineering bulk ferroelectrics with a stable monodomain, which is desirable for the high-performance ferroelectric electro-optic devices.
... IMC can be realized using Static Random-Access Memory (SRAM) [39], Dynamic RAM (DRAM) [40] and Non-Volatile Memories (NVMs) including Resistive RAM (ReRAM) [41], Ferroelectric RAM (FeRAM) [42], STT-MRAM [22], Spin-Orbit Torque MRAM (SOT-MRAM) [32] and other emerging memory devices [21]. NVMs outperform SRAM and DRAM with near-zero leakage power and the non-volatile property of the stored data [43], while STT-MRAM and SOT-MRAM outperform other NVMs with ∼ 10 15 write endurance of single memory cell and much shorter access latency [44]. ...
Convolutional Neural Networks (CNNs) demonstrate great performance in various applications but have high computational complexity. Quantization is applied to reduce the latency and storage cost of CNNs. Among the quantization methods, Binary and Ternary Weight Networks (BWNs and TWNs) have a unique advantage over 8-bit and 4-bit quantization. They replace the multiplication operations in CNNs with additions, which are favoured on In-Memory-Computing (IMC) devices. IMC acceleration for BWNs has been widely studied. However, though TWNs have higher accuracy and better sparsity, IMC acceleration for TWNs has limited research. TWNs on existing IMC devices are inefficient because the sparsity is not well utilized, and the addition operation is not efficient. In this paper, we propose FAT as a novel IMC accelerator for TWNs. First, we propose a Sparse Addition Control Unit, which utilizes the sparsity of TWNs to skip the null operations on zero weights. Second, we propose a fast addition scheme based on the memory Sense Amplifier to avoid the time overhead of both carry propagation and writing back the carry to the memory cells. Third, we further propose a Combined-Stationary data mapping to reduce the data movement of both activations and weights and increase the parallelism of memory columns. Simulation results show that for addition operations at the Sense Amplifier level, FAT achieves 2.00X speedup, 1.22X power efficiency and 1.22X area efficiency compared with State-Of-The-Art IMC accelerator ParaPIM. FAT achieves 10.02X speedup and 12.19X energy efficiency compared with ParaPIM on networks with 80% sparsity
P‐type Two‐dimensional ferroelectric semiconductors (2D FeSs) play an increasingly essential role in the advanced nonvolatile and morphotropic beyond‐Moore electronic devices with high performance and low power consumption. But reliable p‐type 2D FeS with holes as majority carriers are still scarce. Here, we report the first experimental realization of room‐temperature ferroelectricity in van der Waals layered β‐In 1.75 Sb 0.25 Se 3 down to fewlayer. The origin of ferroelectricity in β‐In 1.75 Sb 0.25 Se 3 comes from aliovalent elemental substitution –antimony substituting to the indium sites (Sb In )– changing the local environment of the central‐layer Se atoms. Thanks to the intrinsic ferroelectric and semiconducting natures, ferroelectric semiconductor field‐effect transistor (FeSFET) devices based on β‐In 1.75 Sb 0.25 Se 3 exhibits reconfigurable, multilevel nonvolatile memory (NVM) states, which can be successively modulated by gate voltage stimuli. Furthermore, the inherent operation mechanism, owing to the switchable polarization, indicates that a neuromorphic memory is also possible with our 2D FeSFETs. These presented results facilitate the technological implementation of versatile 2D FeS devices for next‐generation logic‐in‐memory approach for Internet‐of‐Things (IoT) entities.
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Computing in-memory (CiM) is an alternative to von-Neumann architectures for energy efficient AI edge computing architectures with CMOS scaling. Approximate computing in-memory (ACiM) techniques have also been recently proposed to further increase the energy efficiency of such architectures. In the first part of the work, a Negative Capacitance FET (NCFET) based 6T-SRAM CiM accurate full adder has been proposed, designed and performance benchmarked with equivalent baseline 40nm CMOS design. Due to the steep slope characteristics of NCFET, at an increased ferroelectric layer thickness, Tfe of 3nm, the energy consumption of the proposed accurate NCFET based CiM design is ~82.48% lower in comparison to the conventional/Non CiM full adder design and ~ 85.27% lower energy consumption in comparison to the equivalent baseline CMOS CiM accurate full adder design at VDD = 0.5V. This work further proposes a reconfigurable computing in-memory NCFET 6T-SRAM full adder design (the design which can operate both in accurate and approximate modes of operation). NCFET 6T-SRAM reconfigurable full adder design in accurate mode has ~4.19x lower energy consumption and ~4.47x lower energy consumption in approximation mode when compared to the baseline 40nm CMOS design at VDD=0.5V, making NCFET based approximate CiM adder designs preferable for energy efficient AI edge CiM based computing architectures for DNN processing.
Two-dimensional (2D) ferroelectric and ferrovalley materials have recently received extensive attention due to their significant advantages for modern electronic devices, such as miniaturization, low-dissipation, non-volatility, and multi-functionality. More interestingly, the couplings between the ferroic orders in these materials have enriched the development of intelligent devices, especially in neuromorphic computing. In this paper, the research progress of 2D ferroelectric and ferrovalley materials is introduced and the coupling effects between them are also described. Then, we briefly introduce recent neuromorphic computing reports based on 2D ferroelectric materials and give perspectives on ferrovalley neuromorphic devices.
Two-dimensional (2D) ferroelectric materials are important materials for both fundamental properties and potential applications. Especially, group IV monochalcogenide possesses highest thermoelectric performance and intrinsic ferroelectric polarization properties and can sever as a model to explore ferroelectric polarization properties. However, due to the relatively large exfoliation energy, the creation of high-quality and large-size monolayer group IV monochalcogenide is not so easy, which seriously hinders the integration of these materials into the fast-developing field of 2D materials and their heterostructures. Herein, monolayer GeS is successfully fabricated on Cu(111) substrate by molecular beam epitaxy method, and the lattice structure and the electronic band structure of monolayer GeS are systematically characterized by high-resolution scanning tunneling microscopy, low-energy electron diffraction, in-situ X-ray photoelectron spectroscopy, Raman spectra, and angle-resolved photoelectron spectroscopy, and density functional theory calculations. All atomically resolved STM images reveal that the obtained monolayer GeS has an orthogonal lattice structure, which consists with theoretical prediction. Meanwhile, the distinct moiré pattern formed between monolayer GeS and Cu(111) substrate also confirms the orthogonal lattice structure. In order to examine the chemical composition and valence state of as-prepared monolayer GeS, in-situ XPS is utilized without being exposed to air. The measured spectra of XPS core levels suggest that the valence states of Ge and S elements are identified to be +2 and –2, respectively and the atomic ratio of Ge/S is 1∶1.5, which is extremely close to the stoichiometric ratio of 1∶1 for GeS. To further corroborate the quality and lattice structure of the monolayer GeS film, ex-situ Raman measurements are also performed for monolayer GeS on HOPG and multilayer graphene substrate. Three well-defined typical characteristic Raman peaks of GeS are observed. Finally, in-situ ARPES measurement are conducted to determine the electronic band structure of monolayer GeS on Cu(111). The results demonstrate that the monolayer GeS has a nearly flat band electronic band structure, consistent with our density functional theory calculation. The realization and investigation of the monolayer GeS extend the scope of 2D ferroelectric materials and make it possible to prepare high quality and large size monolayer group IV monochalcogenides, which is beneficial to the application of this main group material to the rapidly developing 2D ferroelectric materials and heterojunction research.
Spin orbit torque (SOT) devices with the advantages of high speed, low power consumption, and high stability have wide application prospects in the field of spintronics. The SOT‐based crossbar array device is an important extension of SOT devices, but it is not reported so far. Here, the all electrical magnetization switching of Hall crossings based on SOT crossbar array devices is realized. Through analyzing the current distribution and micromagnetic simulations, it is found that this field‐free SOT switching in the array devices comes from the asymmetric current density gradient distribution at the Hall‐crossings due to the shunt effect of grid circuits. All electrical tristate magnetization switching and the write protection of spin crossbar array devices are demonstrated. This work will further promote the application of the efficient memory or edge computing based on spin crossbar array devices.
Piezotronics is the coupling effect of the piezoelectric and semiconductor properties; however, the piezoelectric constant of the piezoelectric semiconductor is relatively small while the ferroelectric materials with large piezoelectric constant typically possess weak semiconductor properties, thus limiting the effective coupling coefficient of the piezotronic materials and devices. Here, a piezotronics and magnetic dual‐gated ferroelectric semiconductor transistor (PM‐FEST) is fabricated by Terfenol‐D, aluminum oxide (Al2O3), and ferroelectric semiconductor α‐In2Se3, which has a large piezoelectric coefficient, room‐temperature ferroelectricity, and dipole locking. The charge carrier transport and corresponding drain current of the PM‐FEST can be directly modulated by either the applied magnetic field or external strain. At a low magnetic field (<200 mT), the maximum current on/off ratio of α‐In2Se3 based PM‐FEST is as high as 1700%. Compared with traditional piezotronic devices, the PM‐FEST demonstrates a higher gauge factor (2.3 × 10⁴) than that of the piezoelectric semiconductors. This work provides a possibility of realizing magnetism‐modulated electronics in semiconductors by exploiting the coupling of piezotronics and magnetostriction.
Photoelectric synaptic devices with optical sensing capability are of great importance in simulating human vision systems. Especially realizing all‐in‐one vision neuristor on silicon based new materials and principles is being pursued. 2D van der Waals (vdW) materials have the unique advantage of arbitrary stacking on demand. Herein, a full‐vdW two‐terminal 2D ferroelectric α‐In2Se3/SnSe p–n heterojunction is proposed to construct an optoelectronic neuristor to simulate visual synaptic functions. Implementation of these simulations is attributed to the co‐modulation of the electrical polarization reconfigurable built‐in electric field caused by p–n junction and photo‐inducing ferroelectric polarization switching. These functions include ultra‐high paired‐pulse facilitation index (457%), short synaptic plasticity, long synaptic plasticity, and retina‐like optical adaptations. The high PPF is crucial for high‐precision decoding and processing of visual information. Meanwhile, the classical Pavlovian conditioned reflexes associated with associative learning are also emulated showing the ability of the device to handle complex electrical and optical inputs. This study demonstrates that two‐terminal ferroelectric p–n heterojunctions have great potential in high‐precision multifunctional optoelectronic visual synaptic devices.
With the continuous scaling down of the modern integrated circuits, conventional metal-oxide-semiconductor field effect transistors are becoming inefficient due to various nonideal effects such as enhanced short-channel effects. Recently, emerging two-dimensional (2D) ferroelectrics have demonstrated their ability to maintain ferroelectricity at the nanoscale and have shown superior properties compared to three-dimensional ferroelectrics. Here, we report a ferroelectric field effect transistor composed of all 2D van der Waals (vdWs) heterostructures and provide a comprehensive study of the modulation of ferroelectric polarization on the carrier transport properties. Remarkably, the ferroelectric polarization allowed for achieving an ultralow subthreshold swing of just 26 mV/dec and a high carrier mobility of up to 72.3 cm2/(V s) at a smaller drain voltage of 10 mV. These impressive characteristics offer new insights into evaluating the regulatory effect of ferroelectric polarization on the electrical properties of all 2D vdWs heterostructures.
In recent years, an increasing number of 2D van der Waals (vdW) materials are theory‐predicted or laboratory‐validated to possess in‐plane (IP) and/or out‐of‐plane (OOP) spontaneous ferroelectric polarization. Due to their dangling‐bond‐free surfaces, interlayer charge coupling, robust polarization, tunable energy band structures, and compatibility with silicon‐based technologies, vdW ferroelectric materials exhibit great promise in ferroelectric memories, neuromorphic computing, nanogenerators, photovoltaic devices, spintronic devices, and so on. Here, the very recent advances in the field of vdW ferroelectrics (FEs) are reviewed. First, theories of ferroelectricity are briefly discussed. Then, a comprehensive summary of the non‐stacking vdW ferroelectric materials is provided based on their crystal structures and the emerging sliding ferroelectrics. In addition, their potential applications in various branches/frontier fields are enumerated, with a focus on artificial intelligence. Finally, the challenges and development prospects of vdW ferroelectrics are discussed.
2D materials with atomic thickness display strong gate controllability and emerge as promising materials to build area‐efficient electronic circuits. However, achieving the effective and nondestructive modulation of carrier density/type in 2D materials is still challenging because the introduction of dopants will greatly degrade the carrier transport via Coulomb scattering. Here, a strategy to control the polarity of tungsten diselenide (WSe2) field‐effect transistors (FETs) via introducing hexagonal boron nitride (h‐BN) as the interfacial dielectric layer is devised. By modulating the h‐BN thickness, the carrier type of WSe2 FETs has been switched from hole to electron. The ultrathin body of WSe2, combined with the effective polarity control, together contribute to the versatile single‐transistor logic gates, including NOR, AND, and XNOR gates, and the operation of only two transistors as a half adder in logic circuits. Compared with the use of 12 transistors based on static Si CMOS technology, the transistor number of the half adder is reduced by 83.3%. The unique carrier modulation approach has general applicability toward 2D logic gates and circuits for the improvement of area efficiency in logic computation.
Logic-in-memory (LIM) has emerged as an energy-efficient computing technology, as it integrates logic and memory operations in a single device architecture. Herein, a concept of ternary LIM is established. First, a p-type 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene (C8-BTBT) transistor is combined with an n-type PhC2H4-benzo[de]isoquinolino[1,8-gh]quinolone diimide (PhC2-BQQDI) transistor to obtain a binary memory inverter, in which a zinc phthalocyanine-cored polystyrene (ZnPc-PS4) layer serves as a floating gate. The contrasting photoresponse of the transistors toward visible and ultraviolet light and the efficient hole-trapping ability of ZnPc-PS4 enable us to achieve an optically controllable memory operation with a high memory window of 18 V. Then, a ternary memory inverter is developed using an anti-ambipolar transistor to achieve a three-level data processing and storage system for more advanced LIM applications. Finally, low-voltage operation of the devices is achieved by employing a high-k dielectric layer, which highlights the potential of the developed LIM units for next-generation low-power electronics.
Bio‐inspired machine visions have caused wide attentions due to the higher time/power efficiencies over the conventional architectures. Although bio‐mimic photo‐sensors and neuromorphic computing have been individually demonstrated, a complete monolithic vision system has rarely been studied. Here, a neuromorphic machine vision system (NMVS) integrating front‐end retinomorphic sensors and a back‐end convolutional neural network (CNN) based on a single ferroelectric‐semiconductor‐transistor (FST) device structure is reported. As a photo‐sensor, the FST shows a broadband (275–808 nm) retina‐like light adaption function with a large dynamic range of 20.3 stops, and as a unit of the CNN, the FST's weight can be linearly programmed. In total, the NMVS has a high recognition accuracy of 93.0% on a broadband‐dim‐image classification task, which is 20% higher than that of an incomplete system without the retinomorphic sensors. Because of the monolithic unit, the NVMS shows high feasibility for integrated bio‐inspired machine vision systems.
The electric dipole locking effect observed in van der Waals (vdW) ferroelectric α-In2Se3 has resulted in a surge of applied research in electronics with nonvolatile functionality. However, ferroelectric tunnel junctions with advantages of lower power consumption and faster writing/reading operations have not been realized in α-In2Se3. Here, we demonstrate the tunneling electroresistance effect in a lateral β/α/β In2Se3 heterojunction built by local laser irradiation. Switchable in-plane polarizations of the vdW ferroelectric control the tunneling conductance of the heterojunction device by 4000% of magnitude. The electronic logic bit can be represented and stored with different orientations of electric dipoles. This prototype enables a new approach to rewritable nonvolatile memory with in-plane ferroelectricity in vdW 2D materials.
With the advent of the Internet of Things and big data, massive data must be rapidly processed and stored within a short timeframe. This imposes stringent requirements on the memory hardware implementation in terms of operation speed, energy consumption, and integration density. To fulfil these demands, two‐dimensional (2D) materials, which are excellent electronic building blocks, provide numerous possibilities for developing advanced memory device arrays with high performance, smart computing architectures, and desirable downscaling. Over the past few years, 2D material‐based memory device arrays with different working mechanisms including defects, filaments, charges, ferroelectricity, and spins, have been increasingly developed. These arrays can be used to implement brain‐inspired computing or sensing with extraordinary performance, architectures, and functionalities. In this review, we survey recent research into integrated, state‐of‐the‐art memory devices made from 2D materials, as well as their implications for brain‐inspired computing. We discuss the existing challenges at the array level, and present the scope for future research. This article is protected by copyright. All rights reserved
Imagers with pre-processing functions, such as image recognition and classification, contrast enhancement, and noise reduction, play a critical role in the neuromorphic visual system. Optoelectronic plasticity is a prerequisite to achieve these functions. In this study, we demonstrate a nonvolatile reconfigurable broadband photodetector based on a ferroelectric heterostructure composed of BP (black phosphorus)/α-In 2 Se 3 . The plasticity of the device comes from the ferroelectric polarization of α-In 2 Se 3 that can tune the built-in potential of the p–n junction. As a result, the rectification ratio and responsivity increase almost one order when changing the gate voltage pulse from +16 V to −16 V. Due to the introduction of BP, the device has a wide spectral response covering 473–1550 nm. In addition, our devices show excellent performance in terms of a high responsivity of up to 4.73 × 10 ⁴ A/W, a large specific detectivity of ∼2.09 × 10 ¹² Jones, a high external quantum efficiency of 9.21 × 10 ⁶ %, and a notable photo-on-off ratio of 4.82 × 10 ³ . Due to its high performance, reconfigurability, and broadband response, our device shows considerable potential in neuromorphic visual systems even in the infrared region.
With the advent of the big data era, applications are more data-centric and energy efficiency issues caused by frequent data interactions, due to the physical separation of memory and computing, will become increasingly severe. Emerging technologies have been proposed to perform analog computing with memory to address the dilemma. Ferroelectric memory has become a promising technology due to field-driven fast switching and non-destructive readout, but endurance and miniaturization are limited. Here, we demonstrate the α-In 2 Se 3 ferroelectric semiconductor channel device that integrates non-volatile memory and neural computation functions. Remarkable performance includes ultra-fast write speed of 40 ns, improved endurance through the internal electric field, flexible adjustment of neural plasticity, ultra-low energy consumption of 234/40 fJ per event for excitation/inhibition, and thermally modulated 94.74% high-precision iris recognition classification simulation. This prototypical demonstration lays the foundation for an integrated memory computing system with high density and energy efficiency.
Ferroelectric memristors represent a promising new generation of devices that have a wide range of applications in memory, digital information processing, and neuromorphic computing. Recently, van der Waals ferroelectric In2Se3 with unique interlinked out‐of‐plane and in‐plane polarizations has enabled multidirectional resistance switching, providing unprecedented flexibility in planar and vertical device integrations. However, the operating mechanisms of these devices have remained unclear. Here, through the demonstration of van der Waals In2Se3‐based planar ferroelectric memristors with the device resistance continuously tunable over three orders of magnitude, and by correlating device resistance states, ferroelectric domain configurations, and surface electric potential, the studies reveal that the resistive switching is controlled by the multidomain formations and the associated energy barriers between domains, as opposed to the commonly assumed Schottky barrier modulations at the metal‐ferroelectric interface. The findings reveal new device physics through elucidating the microscopic operating mechanisms of this new generation of devices, and provide a critical guide for future device development and integration efforts.
To meet the demands of future intelligent application scenarios, the time‐efficient information acquisition and energy‐efficient data processing capabilities of terminal electronic systems are indispensable. However, in current commercial visual systems, the visible information is collected by image sensors, converted into digital format data, and transferred to memory units and processors for subsequent processing tasks. As a result, most of the time and energy are wasted in the data conversion and movement, which leads to large time latency and low energy efficiency. Here, based on 2D semiconductor WSe2, a logic‐memory transistor that integrates visible information sensing‐memory‐processing capabilities is successfully demonstrated. Furthermore, based on 3 × 3 fabricated devices, an artificial visible information sensing‐memory‐processing system is proposed to perform image distinction tasks, in which the time latency and energy consumption caused by data conversion and movement can be avoided. On the other hand, the logic‐memory transistor can also execute digital logic processing (logic) and logic results storage (memory) at the same time, such as AND logic function. Such a logic‐memory transistor could provide a compact approach to develop next‐generation efficient visual systems. A logic‐memory transistor with the integration of visible information sensing‐memory‐processing is demonstrated. Meaningfully, the logic‐memory transistor can execute logic prosessing and logic results storage at the same time. The logic‐memory transistor also integrates visible information sensing‐memory‐processing capabilities. Furthermore, an artificical visual system is proposed to perform image distinction tasks, in which data conversion and movement can be avoided.
The growing importance of applications based on machine learning is driving the need to develop dedicated, energy-efficient electronic hardware. Compared with von Neumann architectures, which have separate processing and storage units, brain-inspired in-memory computing uses the same basic device structure for logic operations and data storage1–3, thus promising to reduce the energy cost of data-centred computing substantially⁴. Although there is ample research focused on exploring new device architectures, the engineering of material platforms suitable for such device designs remains a challenge. Two-dimensional materials5,6 such as semiconducting molybdenum disulphide, MoS2, could be promising candidates for such platforms thanks to their exceptional electrical and mechanical properties7–9. Here we report our exploration of large-area MoS2 as an active channel material for developing logic-in-memory devices and circuits based on floating-gate field-effect transistors (FGFETs). The conductance of our FGFETs can be precisely and continuously tuned, allowing us to use them as building blocks for reconfigurable logic circuits in which logic operations can be directly performed using the memory elements. After demonstrating a programmable NOR gate, we show that this design can be simply extended to implement more complex programmable logic and a functionally complete set of operations. Our findings highlight the potential of atomically thin semiconductors for the development of next-generation low-power electronics.
Due to the potential applications in optoelectronic memories, optical control of ferroelectric domain walls has emerged as an intriguing and important topic in modern solid‐state physics. However, its device implementation in a single ferroelectric, such as conventional BaTiO3 or PZT ceramics, still presents huge challenges in terms of the poor material conductivity and the energy mismatch between incident photons and ferroelectric switching. Here, using the generation of photocurrent in conductive α‐In2Se3 (a van der Waals ferroelectric) with a two‐terminal planar architecture, the first demonstration of optical‐engineered ferroelectric domain wall in a non‐volatile manner for optoelectronic memory application is reported. The α‐In2Se3 device exhibits a large optical‐writing and electrical‐erasing (on/off) ratio of >104, as well as multilevel current switching upon optical excitation. The narrow direct bandgap of the multilayer α‐In2Se3 ferroelectric endows the device with broadband optical‐writing wavelengths greater than 900 nm. In addition, photonic synapses with approximate linear weight updates for neuromorphic computing are also achieved in the ferroelectric devices. This work represents a breakthrough toward technological applications of ferroelectric nanodomain engineering by light. An optically engineered ferroelectric domain wall in a layered ferroelectric is demonstrated for optoelectronic memory applications. The device exhibits a large optical‐writing and electrical‐erasing ratio of >104, as well as multilevel current switching upon optical excitation. The optical‐writing wavelength can be greater than 900 nm. Photonic synapses with approximate linear weight updates for neuromorphic computing are also achieved in such devices.
Recently, 2D ferroelectrics have attracted extensive interest as a competitive
platform for implementing future generation functional electronics, including
digital memory and brain-inspired computing circuits. Fulfilling their potential
requires achieving the interplay between ferroelectricity and electronic
characteristics on the device operation level, which is currently lacking since
most studies are focused on the verification of ferroelectricity from different
2D materials. Here, by leveraging the ferroelectricity and semiconducting
properties of α-In2Se3, ferroelectric semiconductor field-effect transistors
(FeSFETs) are fabricated and their potential as artificial synapses
is demonstrated. Multiple conductance states can be induced in
α-In2Se3-based FeSFETs by controlling the out-of-plane polarization, which
enables the device to faithfully mimic biosynaptic behaviors. In comparison
with charge-trapping-based three-terminal synaptic devices, the electronic
synapses based on α-In2Se3 have the advantages of good controllability, fast
learning, and easy integration of gate dielectric, rendering them promising
for neuromorphic computing. In addition, an abnormal resistive switching
phenomenon in α-In2Se3 is reported when operated in the in-plane ferroelectric
switching mode. The findings pave the way forward for α-In2Se3-based FeSFETs
for developing neuromorphic devices in brain-inspired intelligent systems.
Reconfigurable logic and neuromorphic devices are crucial for the development of high-performance computing. However, creating reconfigurable devices based on conventional complementary metal–oxide–semiconductor technology is challenging due to the limited field-effect characteristics of the fundamental silicon devices. Here we show that a homojunction device made from two-dimensional tungsten diselenide can exhibit diverse field-effect characteristics controlled by polarity combinations of the gate and drain voltage inputs. These electrically tunable devices can achieve reconfigurable multifunctional logic and neuromorphic capabilities. With the same logic circuit, we demonstrate a 2:1 multiplexer, D-latch and 1-bit full adder and subtractor. These functions exhibit a full-swing output voltage and the same supply and signal voltage, which suggests that the devices could be cascaded to create complex circuits. We also show that synaptic circuits based on only three homojunction devices can achieve reconfigurable spiking-timing-dependent plasticity and pulse-tunable synaptic potentiation or depression characteristics; the same function using complementary metal–oxide–semiconductor devices would require more than ten transistors. A homojunction device made from two-dimensional tungsten diselenide can be used to create circuits that exhibit multifunctional logic and neuromorphic capabilities with simpler designs than conventional silicon-based systems.
Analogue in-memory computing using memristors could alleviate the performance constraints imposed by digital von Neumann systems in data-intensive tasks. Conventional linear memristors typically operate at high currents, potentially limiting power efficiency and scalability in practical applications. Here, we show that nonlinear ferroelectric tunnel junction memristors can perform linear computation at ultralow currents. Using logarithmic line drivers, we demonstrate that analogue-voltage-amplitude vector–matrix multiplication (VMM) can be performed in selectorless ferroelectric tunnel junction crossbars by exploiting a device nonlinearity factor that remains constant for multiple conductive states. We also show that our ferroelectric tunnel junction crossbars have the attributes required to scale analogue VMM-intensive applications, such as neural inference engines, towards energy efficiencies above 100 tera-operations per second per watt. Nonlinear ferroelectric tunnel junction memristors can be used to perform linear vector–matrix multiplication operations at ultralow currents.
Ultrathin ferroelectric materials could potentially enable low-power perovskite ferroelectric tetragonality logic and nonvolatile memories1,2. As ferroelectric materials are made thinner, however, the ferroelectricity is usually suppressed. Size effects in ferroelectrics have been thoroughly investigated in perovskite oxides—the archetypal ferroelectric system3. Perovskites, however, have so far proved unsuitable for thickness scaling and integration with modern semiconductor processes4. Here we report ferroelectricity in ultrathin doped hafnium oxide (HfO2), a fluorite-structure oxide grown by atomic layer deposition on silicon. We demonstrate the persistence of inversion symmetry breaking and spontaneous, switchable polarization down to a thickness of one nanometre. Our results indicate not only the absence of a ferroelectric critical thickness but also enhanced polar distortions as film thickness is reduced, unlike in perovskite ferroelectrics. This approach to enhancing ferroelectricity in ultrathin layers could provide a route towards polarization-driven memories and ferroelectric-based advanced transistors. This work shifts the search for the fundamental limits of ferroelectricity to simpler transition-metal oxide systems—that is, from perovskite-derived complex oxides to fluorite-structure binary oxides—in which ‘reverse’ size effects counterintuitively stabilize polar symmetry in the ultrathin regime. Enhanced switchable ferroelectric polarization is achieved in doped hafnium oxide films grown directly onto silicon using low-temperature atomic layer deposition, even at thicknesses of just one nanometre.
Ferroelectric field-effect transistors (FeFETs) are one of the most interesting ferroelectric devices; however, they, usually suffer from low interface quality. The recently discovered 2D layered ferroelectric materials, combining with the advantages of van der Waals heterostructures (vdWHs), may be promising to fabricate high-quality FeFETs with atomically thin thickness. Here, dual-gated 2D ferroelectric vdWHs are constructed using MoS2 , hexagonal boron nitride (h-BN), and CuInP2 S6 (CIPS), which act as a high-performance nonvolatile memory and programmable rectifier. It is first noted that the insertion of h-BN and dual-gated coupling device configuration can significantly stabilize and effectively polarize ferroelectric CIPS. Through this design, the device shows a record-high performance with a large memory window, large on/off ratio (107 ), ultralow programming state current (10-13 A), and long-time endurance (104 s) as nonvolatile memory. As for programmable rectifier, a wide range of gate-tunable rectification behavior is observed. Moreover, the device exhibits a large rectification ratio (3 × 105 ) with stable retention under the programming state. This demonstrates the promising potential of ferroelectric vdWHs for new multifunctional ferroelectric devices.
Ferroelectric field-effect transistors employ a ferroelectric material as a gate insulator, the polarization state of which can be detected using the channel conductance of the device. As a result, the devices are potentially of use in non-volatile memory technology, but they suffer from short retention times, which limits their wider application. Here, we report a ferroelectric semiconductor field-effect transistor in which a two-dimensional ferroelectric semiconductor, indium selenide (α-In2Se3), is used as the channel material in the device. α-In2Se3 was chosen due to its appropriate bandgap, room-temperature ferroelectricity, ability to maintain ferroelectricity down to a few atomic layers and its potential for large-area growth. A passivation method based on the atomic layer deposition of aluminium oxide (Al2O3) was developed to protect and enhance the performance of the transistors. With 15-nm-thick hafnium oxide (HfO2) as a scaled gate dielectric, the resulting devices offer high performance with a large memory window, a high on/off ratio of over 108, a maximum on current of 862 μA μm−1 and a low supply voltage. A ferroelectric semiconductor field-effect transistor, which uses the two-dimensional ferroelectric semiconductor α-In2Se3 as a channel material, could offer enhanced capabilities compared with conventional ferroelectric field-effect transistors in non-volatile memory applications.
Memristive devices have been extensively demonstrated for applications in nonvolatile memory, computer logic, and biological synapses. Precise control of the conducting paths associated with the resistance switching in memristive devices is critical for optimizing their performances including ON/OFF ratios. Here, gate tunability and multidirectional switching can be implemented in memristors for modulating the conducting paths using hexagonal α‐In2Se3, a semiconducting van der Waals ferroelectric material. The planar memristor based on in‐plane (IP) polarization of α‐In2Se3 exhibits a pronounced switchable photocurrent, as well as gate tunability of the channel conductance, ferroelectric polarization, and resistance‐switching ratio. The integration of vertical α‐In2Se3 memristors based on out‐of‐plane (OOP) polarization is demonstrated with a device density of 7.1 × 10⁹ in.⁻² and a resistance‐switching ratio of well over 10³. A multidirectionally operated α‐In2Se3 memristor is also proposed, enabling the control of the OOP (or IP) resistance state directly by an IP (or OOP) programming pulse, which has not been achieved in other reported memristors. The remarkable behavior and diverse functionalities of these ferroelectric α‐In2Se3 memristors suggest opportunities for future logic circuits and complex neuromorphic computing.
The need for continuous size downscaling of silicon transistors is driving the industrial development of strategies to enable further footprint reduction1,2. The atomic thickness of two-dimensional materials allows the potential realization of high-area-efficiency transistor architectures. However, until now, the design of devices composed of two-dimensional materials has mimicked the basic architecture of silicon circuits3–6. Here, we report a transistor based on a two-dimensional material that can realize photoswitching logic (OR, AND) computing in a single cell. Unlike the conventional transistor working mechanism, the two-dimensional material logic transistor has two surface channels. Furthermore, the material thickness can change the logic behaviour—the architecture can be flexibly expanded to achieve in situ memory such as logic computing and data storage convergence in the same device. These devices are potentially promising candidates for the construction of new chips that can perform computing and storage with high area-efficiency and unique functions.
High‐density memory is integral in solid‐state electronics. 2D ferroelectrics offer a new platform for developing ultrathin electronic devices with nonvolatile functionality. Recent experiments on layered α‐In2Se3 confirm its room‐temperature out‐of‐plane ferroelectricity under ambient conditions. Here, a nonvolatile memory effect in a hybrid 2D ferroelectric field‐effect transistor (FeFET) made of ultrathin α‐In2Se3 and graphene is demonstrated. The resistance of the graphene channel in the FeFET is effectively controllable and retentive due to the electrostatic doping, which stems from the electric polarization of the ferroelectric α‐In2Se3. The electronic logic bit can be represented and stored with different orientations of electric dipoles in the top‐gate ferroelectric. The 2D FeFET can be randomly rewritten over more than 10⁵ cycles without losing the nonvolatility. The approach demonstrates a prototype of rewritable nonvolatile memory with ferroelectricity in van der Waals 2D materials.
2D ferroelectric material has emerged as an attractive building block for high‐density data storage nanodevices. Although monolayer van der Waals ferroelectrics have been theoretically predicted, a key experimental breakthrough for such calculations is still not realized. Here, hexagonally stacking α‐In2Se3 nanoflake, a rarely studied van der Waals polymorph, is reported to exhibit out‐of‐plane (OOP) and in‐plane (IP) ferroelectricity at room temperature. Ferroelectric multidomain states in a hexagonal α‐In2Se3 nanoflake with uniform thickness can survive to 6 nm. Most strikingly, the electric‐field‐induced polarization switching and hysteresis loop are, respectively, observed down to the bilayer and monolayer (≈1.2 nm) thicknesses, which designates it as the thinnest layered ferroelectric and verifies the corresponding theoretical calculation. In addition, two types of ferroelectric nanodevices employing the OOP and IP polarizations in 2H α‐In2Se3 are developed, which are applicable for nonvolatile memories and heterostructure‐based nanoelectronics/optoelectronics. The thinnest layered ferroelectric is demonstrated for the first time at room temperature. The semiconducting hexagonal α‐In2Se3 nanoflakes exhibit out‐of‐plane and in‐plane ferroelectricity that are closely intercorrelated. The polarization switching and hysteresis loops can be realized in the thickness as thin as ≈2.3 nm (bilayer) and ≈1.2 nm (monolayer). Two types of ferroelectric switchable devices are proposed to show the potential application in nonvolatile memories.
Van der Waals (vdW) assembly of layered materials is a promising paradigm for creating electronic and opto-electronic devices with novel properties. Ferroelectricity in vdW layered materials could enable nonvolatile memory and low-power electronic and optoelectronic switches, but to date, few vdW ferroelectrics have been reported, and few in-plane vdW ferroelectrics are known. We report the discovery of in-plane ferroelectricity in a widely investigated vdW layered material, b′-In 2 Se 3. The in-plane ferroelectricity is strongly tied to the formation of one-dimensional superstructures aligning along one of the threefold rotational symmetric directions of the hexagonal lattice in the c plane. Surprisingly, the superstructures and ferroelectricity are stable to 200°C in both bulk and thin exfoliated layers of In 2 Se 3. Because of the in-plane nature of ferroelectricity, the domains exhibit a strong linear dichroism, enabling novel polarization-dependent optical properties.
Interest in two-dimensional (2D) van der Waals materials has grown rapidly across multiple scientific and engineering disciplines in recent years. However, ferroelectricity, the presence of a spontaneous electric polarization, which is important in many practical applications, has rarely been reported in such materials so far. Here we employ first-principles calculations to discover a branch of the 2D materials family, based on In2Se3 and other III2-VI3 van der Waals materials, that exhibits room-temperature ferroelectricity with reversible spontaneous electric polarization in both out-of-plane and in-plane orientations. The device potential of these 2D ferroelectric materials is further demonstrated using the examples of van der Waals heterostructures of In2Se3/graphene, exhibiting a tunable Schottky barrier, and In2Se3/WSe2, showing a significant band gap reduction in the combined system. These findings promise to substantially broaden the tunability of van der Waals heterostructures for a wide range of applications.
Mechanical exfoliation has been a key enabler of the exploration of the properties of two-dimensional materials, such as graphene, by providing routine access to high-quality material. The original exfoliation method, which remained largely unchanged during the past decade, provides relatively small flakes with moderate yield. Here, we report a modified approach for exfoliating thin monolayer and few-layer flakes from layered crystals. Our method introduces two process steps that enhance and homogenize the adhesion force between the outermost sheet in contact with a substrate: Prior to exfoliation, ambient adsorbates are effectively removed from the substrate by oxygen plasma cleaning; and an additional heat treatment maximizes the uniform contact area at the interface between the source crystal and the substrate. For graphene exfoliation, these simple process steps increased the yield and the area of the transferred flakes by more than 50 times compared to the established exfoliation methods. Raman and AFM characterization shows that the graphene flakes are of similar high quality as those obtained in previous reports. Graphene field-effect devices were fabricated and measured with back-gating and solution top-gating, yielding mobilities of ~4000 cm2/Vs and 12000 cm2/Vs, respectively and thus demonstrating excellent electrical properties. Experiments with other layered crystals, e.g., a bismuth strontium calcium copper oxide (BSCCO) superconductor, show enhancements in exfoliation yield and flake area similar to those for graphene, suggesting that our modified exfoliation method provides an effective way for producing large area, high-quality flakes of a wide range of 2D materials.
Recently, several emerging technologies have been reported as potential candidates for controllable ambipolar devices. Controllable ambipolarity is a desirable property that enables the on-line configurability of n-type and p-type device polarity. In this paper, we introduce a new design methodology for logic gates based on controllable ambipolar devices, with an emphasis on carbon nanotubes as the candidate technology. Our technique results in ambipolar gates with a higher expressive power than conventional complementary metal-oxidesemiconductor (CMOS) libraries. We propose a library of static ambipolar carbon nanotube field effect transistor (CNTFET) gates based on generalized NOR-NAND-AOI-OAI primitives, which efficiently implements XOR-based functions. Technology mapping of several multi-level logic benchmarks that extensively use the XOR function, including multipliers, adders, and linear circuits, with ambipolar CNTFET logic gates indicates that on average, it is possible to reduce the number of logic levels by 42%, the delay by 26%, and the power consumption by 32%, resulting in a energy-delay-product (EDP) reduction of 59 % over the same circuits mapped with unipolar CNTFET logic gates. Based on the projections in [1], where it is stated that defectfree CNTFETs will provide a 5x performance improvement over metal-oxide-semiconductor field effect transistors, the ambipolar library provides a performance improvement of 7x, a 57% reduction in power consumption, and a 20x improvement in EDP over the CMOS library.
Two-dimensional materials are attractive for use in next-generation nanoelectronic devices because, compared to one-dimensional materials, it is relatively easy to fabricate complex structures from them. The most widely studied two-dimensional material is graphene, both because of its rich physics and its high mobility. However, pristine graphene does not have a bandgap, a property that is essential for many applications, including transistors. Engineering a graphene bandgap increases fabrication complexity and either reduces mobilities to the level of strained silicon films or requires high voltages. Although single layers of MoS(2) have a large intrinsic bandgap of 1.8 eV (ref. 16), previously reported mobilities in the 0.5-3 cm(2) V(-1) s(-1) range are too low for practical devices. Here, we use a halfnium oxide gate dielectric to demonstrate a room-temperature single-layer MoS(2) mobility of at least 200 cm(2) V(-1) s(-1), similar to that of graphene nanoribbons, and demonstrate transistors with room-temperature current on/off ratios of 1 × 10(8) and ultralow standby power dissipation. Because monolayer MoS(2) has a direct bandgap, it can be used to construct interband tunnel FETs, which offer lower power consumption than classical transistors. Monolayer MoS(2) could also complement graphene in applications that require thin transparent semiconductors, such as optoelectronics and energy harvesting.
The discovery of ferroelectricity in oxides that are compatible with modern semiconductor manufacturing processes, such as hafnium oxide, has led to a re-emergence of the ferroelectric field-effect transistor in advanced microelectronics. A ferroelectric field-effect transistor combines a ferroelectric material with a semiconductor in a transistor structure. In doing so, it merges logic and memory functionalities at the single-device level, delivering some of the most pressing hardware-level demands for emerging computing paradigms. Here, we examine the potential of the ferroelectric field-effect transistor technologies in current embedded non-volatile memory applications and future in-memory, biomimetic and alternative computing models. We highlight the material- and device-level challenges involved in high-volume manufacturing in advanced technology nodes (≤10 nm), which are reminiscent of those encountered in the early days of high-K-metal-gate transistor development. We argue that the ferroelectric field-effect transistors can be a key hardware component in the future of computing, providing a new approach to electronics that we term ferroelectronics.
Overcoming the sub-5 nm gate length limit and decreasing the power dissipation are two main objects in the electronics research field. Besides advanced engineering techniques, considering new material systems may be helpful. Here, we demonstrate two-dimensional (2D) subthermionic field-effect transistors (FETs) with sub-5 nm gate lengths based on ferroelectric (FE) van der Waals heterostructures (vdWHs). The FE vdWHs are composed of graphene, MoS2, and CuInP2S6 acting as 2D contacts, channels, and ferroelectric dielectric layers, respectively. We first show that the as-fabricated long-channel device exhibits nearly hysteresis-free subthermionic switching over three orders of magnitude of drain current at room temperature. Further, we fabricate short-channel subthermionic FETs using metallic carbon nanotubes as effective gate terminals. A typical device shows subthermionic switching over five-to-six orders of magnitude of drain current with a minimum subthreshold swing of 6.1 mV/dec at room temperature. Our results indicate that 2D materials system is promising for advanced highly-integrated energy-efficient electronic devices.
Ionic floating-gate memories
Digital implementations of artificial neural networks perform many tasks, such as image recognition and language processing, but are too energy intensive for many applications. Analog circuits that use large crossbar arrays of synaptic memory elements represent a low-power alternative, but most devices cannot update the synaptic weights uniformly or scale to large array sizes. Fuller et al. developed an integrated device, ionic floating-gate memory, that has the gate terminal of a redox transistor electrically connected to a diffusive memristor. This low-power device enabled linear and symmetric weight updates in parallel over an entire crossbar array at megahertz rates over 10 ⁹ write-read cycles.
Science , this issue p. 570
Modern computers are based on the von Neumann architecture in which computation and storage are physically separated: data are fetched from the memory unit, shuttled to the processing unit (where computation takes place) and then shuttled back to the memory unit to be stored. The rate at which data can be transferred between the processing unit and the memory unit represents a fundamental limitation of modern computers, known as the memory wall. In-memory computing is an approach that attempts to address this issue by designing systems that compute within the memory, thus eliminating the energy-intensive and time-consuming data movement that plagues current designs. Here we review the development of in-memory computing using resistive switching devices, where the two-terminal structure of the devices, their resistive switching properties, and direct data processing in the memory can enable area- and energy-efficient computation. We examine the different digital, analogue, and stochastic computing schemes that have been proposed, and explore the microscopic physical mechanisms involved. Finally, we discuss the challenges in-memory computing faces, including the required scaling characteristics, in delivering next-generation computing. This Review Article examines the development of in-memory computing using resistive switching devices.
Out-of-plane ferroelectricity with a high transition temperature in ultrathin films is important for the exploration of new domain physics and scaling down of memory devices. However, depolarizing electrostatic fields and interfacial chemical bonds can destroy this long-range polar order at two-dimensional (2D) limit. Here we report the experimental discovery of the locking between out-of-plane dipoles and in-plane lattice asymmetry in atomically thin In2Se3 crystals, a new stabilization mechanism leading to our observation of intrinsic 2D out-of-plane ferroelectricity. Through second harmonic generation spectroscopy and piezoresponse force microscopy, we found switching of out-of-plane electric polarization requires a flip of nonlinear optical polarization that corresponds to the inversion of in-plane lattice orientation. The polar order shows a very high transition temperature (∼700 K) without the assistance of extrinsic screening. This finding of intrinsic 2D ferroelectricity resulting from dipole locking opens up possibilities to explore 2D multiferroic physics and develop ultrahigh density memory devices.
Spintronic and multiferroic systems are leading candidates for achieving attojoule-class logic gates for computing, thereby enabling the continuation of Moore's law for transistor scaling. However, shifting the materials focus of computing towards oxides and topological materials requires a holistic approach addressing energy, stochasticity and complexity.
Enriching the functionality of ferroelectric materials with visible-light sensitivity and multiaxial switching capability would open up new opportunities for their applications in advanced information storage with diverse signal manipulation functions. We report experimental observations of robust intra-layer ferroelectricity in two-dimensional (2D) van der Waals layered -In2Se3 ultrathin flakes at room temperature. Distinct from other 2D and conventional ferroelectrics, In2Se3 exhibits intrinsically intercorrelated out-of-plane and in-plane polarization, where the reversal of the out-of-plane polarization by a vertical electric field also induces the rotation of the in-plane polarization. Based on the in-plane switchable diode effect and the narrow bandgap (~1.3 eV) of ferroelectric In2Se3, a prototypical non-volatile memory device, which can be manipulated both by electric field and visible light illumination, is demonstrated for advancing data storage technologies.
A memristor is a resistive device with an inherent memory. The theoretical concept of a memristor was connected to physically measured devices in 2008 and since then there has been rapid progress in the development of such devices, leading to a series of recent demonstrations of memristor-based neuromorphic hardware systems. Here, we evaluate the state of the art in memristor-based electronics and explore where the future of the field lies. We highlight three areas of potential technological impact: on-chip memory and storage, biologically inspired computing and general-purpose in-memory computing. We analyse the challenges, and possible solutions, associated with scaling the systems up for practical applications, and consider the benefits of scaling the devices down in terms of geometry and also in terms of obtaining fundamental control of the atomic-level dynamics. Finally, we discuss the ways we believe biology will continue to provide guiding principles for device innovation and system optimization in the field.
The computing demands of future data-intensive applications will greatly exceed the capabilities of current electronics, and are unlikely to be met by isolated improvements in transistors, data storage technologies or integrated circuit architectures alone. Instead, transformative nanosystems, which use new nanotechnologies to simultaneously realize improved devices and new integrated circuit architectures, are required. Here we present a prototype of such a transformative nanosystem. It consists of more than one million resistive random-access memory cells and more than two million carbon-nanotube field-effect transistors—promising new nanotechnologies for use in energy-efficient digital logic circuits and for dense data storage—fabricated on vertically stacked layers in a single chip. Unlike conventional integrated circuit architectures, the layered fabrication realizes a three-dimensional integrated circuit architecture with fine-grained and dense vertical connectivity between layers of computing, data storage, and input and output (in this instance, sensing). As a result, our nanosystem can capture massive amounts of data every second, store it directly on-chip, perform in situ processing of the captured data, and produce ‘highly processed’ information. As a working prototype, our nanosystem senses and classifies ambient gases. Furthermore, because the layers are fabricated on top of silicon logic circuitry, our nanosystem is compatible with existing infrastructure for silicon-based technologies. Such complex nano-electronic systems will be essential for future high-performance and highly energy-efficient electronic systems.
Layered materials have been found to be the promising candidates for next-generation microelectronic and optoelectronic devices due to their unique electrical and optical properties. The p-n junction is an elementary building block for microelectronics and optoelectronics devices. Herein, using pulsed-laser deposition (PLD) method, we achieve the self-assembly of the lateral p-n heterojunction of In2Se3/CuInSe2 film. In comparison to the intrinsic In2Se3 one, the photodetectors based on the In2Se3/CuInSe2 heterojunction exhibit a tremendous promotion of photodetection performance and obvious rectifying behavior. The photoresponsivity and external quantum efficiency (EQE) of the fabricated heterojunction based device under 532 nm light irradiation are 20.1 A/W and 4698%, respectively. These values are about 7.5 times higher than those of pure In2Se3 devices. We attribute this promotion of photodetection to the suitable band structures of In2Se3 and CuInSe2, which greatly promote the separation of photoexcited electron-hole pairs. This work suggests an effective way to form lateral p-n junction, opening up a new scenario for designing and constructing high performance optoelectronic devices.
Our challenge is clear: The drive for performance and the end of voltage scaling have made power, and not the number of transistors, the principal factor limiting further improvements in computing performance. Continuing to scale compute performance will require the creation and effective use of new specialized compute engines, and will require the participation of application experts to be successful. If we play our cards right, and develop the tools that allow our customers to become part of the design process, we will create a new wave of innovative and efficient computing devices.
Hysteretic resistance effects based on a correlation between ferroelectric polarization and conductivity might become of particular interest for nonvolatile memory applications, because they are not subject to the scaling restrictions of charge based memories such as the ferroelectric random access memory. Two basic concepts, a metal-ferroelectric-metal structure and a metal-ferroelectric-semiconductor structure are discussed in the literature. This contribution discusses the principle of operation of those concepts in terms of the band model. A generalized model is proposed, which is based on a conductive metal-ferroelectric-semiconductor-metal structure. Here, the existence of a low and a high conductive state originates from a switch of the polarization in the ferroelectric layer and a resulting positive or negative polarization charge at the ferroelectric-semiconductor interface. Charge carriers in the film are attracted by or depleted at the interface giving rise to different local conductivities. By simulation, the effect of internal screening caused by mobile charge carriers on the hysteretic current-voltage behavior and the depolarizing field in the ferroelectric are estimated. The simulation discloses a switching ratio up to several orders of magnitude and a conductivity window, which scales with the donor concentration. It may also explain resistive switching in systems consisting only of one ferroelectric layer by assuming the presence of nonferroelectric interface layers.
Single-transistor ferroelectric field effect transistor offers attractive features for future memory applications, such as scalable cell structure, high speed, and low power consumption. However, its relatively short retention time has prevented its application as a non-volatile memory. In order to investigate its retention mechanism, we have developed an automatic retention measurement technique, which enables direct flatband voltage tracking shortly after programming. Two mechanisms, based on the effects of the depolarization field and the gate leakage followed by trapping, respectively, have been identified responsible for the memory window loss in different time regimes, according to the data obtained from this technique.
We developed a model with no adjustable parameter for retention loss at short and long time scales in ferroelectric thin-film capacitors. We found that the predictions of this model are in good agreement with the experimental observations in the literature. In particular, it explains why a power-law function shows better fitting than a linear-log relation on a short time scale ( 10<sup>-7</sup> s to 1 s) and why a stretched exponential relation gives more precise description than a linear-log plot on a long time scale (≫100 s ) , as reported by many researchers in the past. More severe retention losses at higher temperatures and in thinner films have also been correctly predicted by the present theory.
Over the past 30 years electronic applications have been dominated by complementary metal oxide semiconductor (CMOS) devices. These combine p- and n-type field effect transistors (FETs) to reduce static power consumption. However, CMOS transistors are limited to static electrical functions, i.e., electrical characteristics that cannot be changed. Here we present the concept and a demonstrator of a universal transistor that can be reversely configured as p-FET or n-FET simply by the application of an electric signal. This concept is enabled by employing an axial nanowire heterostructure (metal/intrinsic-silicon/metal) with independent gating of the Schottky junctions. In contrast to conventional FETs, charge carrier polarity and concentration are determined by selective and sensitive control of charge carrier injections at each Schottky junction, explicitly avoiding the use of dopants as shown by measurements and calculations. Besides the additional functionality, the fabricated nanoscale devices exhibit enhanced electrical characteristics, e.g., record on/off ratio of up to 1 × 10(9) for Schottky transistors. This novel nanotransistor technology makes way for a simple and compact hardware platform that can be flexibly reconfigured during operation to perform different logic computations yielding unprecedented circuit design flexibility.
The authors of the International Technology Roadmap for Semiconductors-the industry consensus set of goals established for advancing silicon integrated circuit technology-have challenged the computing research community to find new physical state variables (other than charge or voltage), new devices, and new architectures that offer memory and logic functions beyond those available with standard transistors. Recently, ultra-dense resistive memory arrays built from various two-terminal semiconductor or insulator thin film devices have been demonstrated. Among these, bipolar voltage-actuated switches have been identified as physical realizations of 'memristors' or memristive devices, combining the electrical properties of a memory element and a resistor. Such devices were first hypothesized by Chua in 1971 (ref. 15), and are characterized by one or more state variables that define the resistance of the switch depending upon its voltage history. Here we show that this family of nonlinear dynamical memory devices can also be used for logic operations: we demonstrate that they can execute material implication (IMP), which is a fundamental Boolean logic operation on two variables p and q such that pIMPq is equivalent to (NOTp)ORq. Incorporated within an appropriate circuit, memristive switches can thus perform 'stateful' logic operations for which the same devices serve simultaneously as gates (logic) and latches (memory) that use resistance instead of voltage or charge as the physical state variable.
A breakthrough in materials could refresh and sustain the information technology revolution.
A silicone-based one-transistor nonvolatile memory cell has been implemented by integration of a ferroelectric polymer gate on a standard n- type metal oxide semiconductor field effect transistor. The polarization reversal in the gate results in a stable and reproducible memory effect changing the source-drain current by a factor 102–103, with the retention exceeding 2–3 days. Analysis of the drain current relaxation and time- resolved study of the spontaneous polarization via piezoforce scanning probe microscopy indicates that the retention loss is controlled by the interface- adjacent charge injection rather than the polarization instability. A semiquantitative model describes the time-dependent retention loss characterized by an exponential decay of the open state current of the transistor. The unique combination of properties of the ferroelectric copolymer of vinylidene fluoride and trifluoroethylene, including an adequate spontaneous polarization and low dielectric constant as well as rather benign processing demands, makes this material a promising candidate for memories fully compatible with silicon technology.
A Schottky contact consisting of a semiconducting ferroelectric material and a high work function metal shows a bistable conduction characteristic. An on/off ratio of about 2 orders of magnitude was obtained in a structure consisting of a 0.2 μm ferroelectric PbTiO3 film, a Au Schottky contact, and a La0.5Sr0.5CoO3 Ohmic bottom electrode. The observations are explained by a model in which the depletion width of the ferroelectric Schottky diode is determined by the polarization dependence of the internal electric field at the metal-ferroelectric interface.
Long viewed as a topic in classical physics, ferroelectricity can be described by a quantum mechanical ab initio theory. Thin-film
nanoscale device structures integrated onto Si chips have made inroads into the semiconductor industry. Recent prototype applications
include ultrafast switching, cheap room-temperature magnetic-field detectors, piezoelectric nanotubes for microfluidic systems,
electrocaloric coolers for computers, phased-array radar, and three-dimensional trenched capacitors for dynamic random access
memories. Terabit-per-square-inch ferroelectric arrays of lead zirconate titanate have been reported on Pt nanowire interconnects
and nanorings with 5-nanometer diameters. Finally, electron emission from ferroelectrics yields cheap, high-power microwave
devices and miniature x-ray and neutron sources.
Integrated electronics has come a long way since the invention of the transistor in 1947 and the fabrication of the first integrated circuit in 1958. Given feature sizes as small as a few nanometres, what will the future hold for integrated electronics?
It is well-known that conventional field effect transistors (FETs) require a change in the channel potential of at least 60 mV at 300 K to effect a change in the current by a factor of 10, and this minimum subthreshold slope S puts a fundamental lower limit on the operating voltage and hence the power dissipation in standard FET-based switches. Here, we suggest that by replacing the standard insulator with a ferroelectric insulator of the right thickness it should be possible to implement a step-up voltage transformer that will amplify the gate voltage thus leading to values of S lower than 60 mV/decade and enabling low voltage/low power operation. The voltage transformer action can be understood intuitively as the result of an effective negative capacitance provided by the ferroelectric capacitor that arises from an internal positive feedback that in principle could be obtained from other microscopic mechanisms as well. Unlike other proposals to reduce S, this involves no change in the basic physics of the FET and thus does not affect its current drive or impose other restrictions.
In principle, a memory field-effect transistor (FET) based on the metal-ferroelectric-semiconductor gate stack could be the building block of an ideal memory technology that offers random access, high speed, low power, high density and nonvolatility. In practice, however, so far none of the reported ferroelectric memory transistors has achieved a memory retention time of more than a few days, a far cry from the ten-year retention requirement for a nonvolatile memory device. This work will examine two major causes of the short retention (assuming no significant mobile ionic charge motion in the ferroelectric film): 1) depolarization field and 2) finite gate leakage current. A possible solution to the memory retention problem will be suggested, which involves the growth of single-crystal, single domain ferroelectric on Si. The use of the ferroelectric memory transistor as a capacitor-less DRAM cell will also be proposed.
Ferroelectricity in hafnium oxide thin films
- Boescke
Programmable nanowire circuits for nanoprocessors
- Yan