No full-text available
To read the full-text of this research,
you can request a copy directly from the authors.
A CMOS field-programmable analog array
Abstract
The design details and test results of a field-programmable analog array (FPAA) prototype chip in 1.2-pm CMOS are presented. The analog array is based on subthreshold circuit techniques and consists of a collection of homogeneous configurable analog blocks (CAB’s) and an interconnection network. Interconnections between CAB’s and the analog functions to be implemented in each block are defined by a set of configuration bits loaded serially into an on-board shift register by the user. Macromodels are developed for the analog functions in order to simulate various neural network applications on the field-programmable analog array.
... However, the increasing availability of mainstream, low-cost microelectronics fabrication processes has enabled a new generation of integrated analog computing devices. These most often take the form of special-purpose analog processors aimed toward solving a particular class of problems [5], [6], [12], although more general-purpose architectures, like the field-programmable analog array, have also been explored [13]- [18]. ...
Analog computing is based upon using physical processes to solve formal mathematical problems. In the past, it was the predominant instrument of scientific calculations. Now, as the physical limits imposed on digital devices compel research into alternate computing paradigms, a reexamination of the potentialities of analog computing is warranted. This work studies the application of analog CMOS cells toward the simulation of dynamical systems, and, more generally, solving sets of coupled time-dependent ordinary differential equations. Following a brief review of the fundamentals of systems theory and analog computing, the main set of computing elements is introduced, each comprising analog cells designed in a 130 nm process. These are subsequently applied to the realization of practical, special-purpose analog computing modules. Illustrative systems from various fields are selected for simulation. Though by no means comprehensive, these case studies highlight the capabilities of contemporary analog computing, especially in solving nonlinear problems. Circuit simulations show good agreement with solutions obtained from high-order numerical methods, at least over a limited range of system parameters. The article concludes with a brief discussion of broader analog computing applications, offering future prospects toward further exploration of its potentialities and limitations in a wide range of domains.
... The analog counterpart of programmable logic is the field programmable analog array (FPAA) [5][6][7][8]. FPAAs are based on reconfigurable analog blocks (CAB), which are composed of operational amplifiers, filters, transistors, and/or various passive components [6,9]. These CABs can be connected using floating-gate transistors or similar signal routing switches to enable customized analog functionality by programming an interconnection network [6]. ...
A novel concept for programmable mixed-signal circuits is presented based on programmable transmission gates. For implementation, memristively switching devices are suggested as the most promising candidates for realization of fast and small-footprint signal routing switches with small resistance and capacity. As a proof-of-concept, LT Spice simulations of digital and analogue example circuits implemented by the new concept are demonstrated. It is discussed how important design parameters can be tuned in the circuity. Compared to competing technologies such as Field Programmable Analogue Arrays or Application-Specific Integrated Circuits, the presented concept allows for development of ultra-flexible, reconfigurable, and cheap embedded mixed-signal circuits for applications where only limited space is available or high bandwidth is required.
... FPAAs have analog components plus routing between analog and digital components, similar to FPGAs. Early programmable analog arrays [38][39][40] and early commercial devices (e.g., EPAC [41] or Anadigm [42]) were useful for glue logic and small occasional computations. Today's FPAAs show considerable capabilities in ultra-low power computation, signal processing, and embedded machine learning [4] from ICs fabricated in a 350 nm CMOS process. ...
The design of analog computing systems requires significant human resources and domain expertise due to the lack of automation tools to enable these highly energy-efficient, high-performance computing nodes. This work presents the first automated tool flow from a high-level representation to a reconfigurable physical device. This tool begins with a high-level algorithmic description, utilizing either our custom Python framework or the XCOS GUI, to compile and optimize computations for integration into an Integrated Circuit (IC) design or a Field Programmable Analog Array (FPAA). An energy-efficient embedded speech classifier benchmark illustrates the tool demonstration, automatically generating GDSII layout or FPAA switch list targeting.
... Two distinct approaches can be found in the history of the field. The first one relates to fault-tolerance and circuit creation or synthesis in the widest sense and is primarily pursued in the fields of Evolvable Hardware and Evolutionary Electronics based on reconfigurable analog arrays, predominantly on transistor level granularity [40][41][42][43][44][45][46][47][48], combined with algorithms of evolutionary optimization to configure and reconfigure the degrees of freedom of the given hardware for continued goal or specification fulfillment [19,20,[49][50][51][52][53][54][55][56][57][58][59][60][61][62][63][64]. These approaches allow both the compensation of static instance issues, e.g., defects and mismatch from manufacturing, as well as dynamic compensation of temporal phenomena such as drift, aging, or damage of defect suffered in electronics' service time. ...
The ongoing vivid advance in integration technologies is giving leverage both to computing systems as well as to sensors and sensor systems. Both conventional computing systems as well as innovative computing systems, e.g., following bio-inspiration from nervous systems or neural networks, require efficient interfacing to an increasing diversity of sensors under the constraints of metrology. The realization of sufficiently accurate, robust, and flexible analog front-ends (AFE) is decisive for the overall application system and quality and requires substantial design expertise both for cells in System-on-Chip (SoC) or chips in System-in-Package (SiP) realizations. Adding robustness and flexibility to sensory systems, e.g., for Industry 4.0., by self-X or self-* features, e.g., self-monitoring, -trimming, or -healing (AFEX) approaches the capabilities met in living beings and is pursued in our research. This paper summarizes on two chips, denoted as Universal-Sensor-Interface-with-self-X-properties (USIX) based on amplitude representation and reports on recently identified challenges and corresponding advanced solutions, e.g., on circuit assessment as well as observer robustness for classic amplitude-based AFE, and transition activities to spike domain representation spiking-analog-front-ends with self-X properties (SAFEX) based on adaptive spiking electronics as the next evolutionary step in AFE development. Key cells for AFEX and SAFEX have been designed in XFAB xh035 CMOS technology and have been subject to extrinsic optimization and/or adaptation. The submitted chip features 62,921 transistors, a total area of 10.89 mm2 (74% analog, 26% digital), and 66 bytes of the configuration memory. The prepared demonstrator will allow intrinsic optimization and/or adaptation for the developed technology agnostic concepts and chip instances. In future work, confirmed cells will be moved to complete versatile and robust AFEs, which can serve both for conventional as well as innovative computing systems, e.g., spiking neurocomputers, as well as to leading-edge technologies to serve in SOCs.
... Some designs were based on the current conveyor (CC) as the active block for the CAB [2][3][4][5], operational amplifiers (op-amps) [1,[6][7][8][9],current feedback operational amplifiers (CFOAs) [10]. and operational transconductance amplifiers (OTAs) [11][12][13][14][15][16]. Another difference in the FPAA architecture is the interconnection between CABs wherein most connections use switches, such as transmission gates [10],or basic metal-oxide semiconductor (MOS) switches for switched capacitance (SC) 2 | DIAB AnD MAHMOUD circuits [8,9]. ...
This study presents a new architecture for a field programmable analog array (FPAA) for use in low‐frequency applications, and a generalized circuit realization method for the implementation of nth‐order elliptic filters. The proposed designs of both the FPAA and elliptic filters are based on the operational transconductance amplifier (OTA) used in implementing OTA‐C filters for biopotential signal processing. The proposed FPAA architecture has a flexible, expandable structure with direct connections between configurable analog blocks (CABs) that eliminates the use of switches. The generalized elliptic filter circuit realization provides a simplified, direct synthetic method for an OTA‐C symmetric balanced structure for even/odd‐nth‐order low‐pass filters (LPFs) and notch filters with minimum number of components, using grounded capacitors. The filters are mapped on the FPAA, and both architectures are validated with simulations in LTspice using 90‐nm complementary metal‐oxide semiconductor (CMOS) technology. Both proposed FPAA and filters generalized synthetic method achieve simple, flexible, low‐power designs for implementation of biopotential signal processing systems.
... A field-programmable analog array (FPAA) is a reconfigurable integrated circuit (IC) that is the mixed-signal analogue to a field-programmable gate array (FPGA); while FPGAs allow for post-fabrication synthesis of digital circuits, FPAAs allow for the post-fabrication synthesis of analog circuits [27][28][29]. FPAAs can be used to synthesize common circuits such as amplifiers or filters, making them useful for sensor interfacing applications. The reconfigurable, analog architecture of an FPAA allows for both general-purpose analog signal processing and complex application-driven signal-processing tasks [30]. ...
The wireless sensor nodes used in a growing number of remote sensing applications are deployed in inaccessible locations or are subjected to severe energy constraints. Audio-based sensing offers flexibility in node placement and is popular in low-power schemes. Thus, in this paper, a node architecture with low power consumption and in-the-field reconfigurability is evaluated in the context of an acoustic vehicle detection and classification (hereafter “AVDC”) scenario. The proposed architecture utilizes an always-on field-programmable analog array (FPAA) as a low-power event detector to selectively wake a microcontroller unit (MCU) when a significant event is detected. When awoken, the MCU verifies the vehicle class asserted by the FPAA and transmits the relevant information. The AVDC system is trained by solving a classification problem using a lexicographic, nonlinear programming algorithm. On a testing dataset comprising of data from ten cars, ten trucks, and 40 s of wind noise, the AVDC system has a detection accuracy of 100%, a classification accuracy of 95%, and no false alarms. The mean power draw of the FPAA is 43 μ W and the mean power consumption of the MCU and radio during its validation and wireless transmission process is 40.9 mW. Overall, this paper demonstrates that the utilization of an FPAA-based signal preprocessor can greatly improve the flexibility and power consumption of wireless sensor nodes.
... Similar to a Field Programmable Gate Array (FPGA) an FPAA makes prototyping mixed-signal systems cost effective and shortening the test cycles [16][17]. FG-based FPAAs [18][19][20][21][22][23] offer the required reconfigurability and programmability when implementing large analog systems typically suffering from mismatch and process variations [24,25]. ...
This work presents a mixed-signal physical-computation-electronics for monitoring three vital signs; namely heart rate, blood pressure, and blood oxygen saturation; from electrocardiography, arterial blood pressure, and photoplethysmography signals in real-time. The computational circuits are implemented on a reconfigurable and programmable signal-processing platform, namely field-programmable analog array (FPAA). The design leverages the core enabling technology of FPAA, namely floating-gate CMOS devices, and an on-chip low-power microcontroller to achieve energy-efficiency while not compromising accuracy. The custom physical-computation-electronics operating in CMOS subthreshold region, performs low-level (i.e., physiologically-relevant feature extraction) and high-level (i.e., detecting arrhythmia) signal processing in an energy-efficient manner. The on-chip microcontroller is used (1) in the programming mode for controlling the charge storage at the analog-memory elements to introduce patient-dependency into the system and (2) in the run mode to quantify the vital signs. The system has been validated against digital computation results from MATLAB using datasets collected from three healthy subjects and datasets from the MIT/BIH open source database. Based on all recordings in the MIT/BIH database, ECG R-peak detection sensitivity is 94.2%. The processor detects arrhythmia in three MIT/BIH recordings with an average sensitivity of 96.2%. The cardiac processor achieves an average percentage mean error bounded by 3.75%, 6.27%, and 7.3% for R-R duration, systolic blood pressure, and oxygen saturation level calculations; respectively. The power consumption of the ECG, blood-pressure and photo-plethysmography processing circuitry are 126 nW, 251 nW and 1.44 μW respectively in a 350nm process. Overall, the cardiac processor consumes 1.82 μW.
... The desire to enable reconfigurability in analog electronics has led to the development of a relatively new class of devices called field-programmable analog arrays (FPAAs) [1,[14][15][16]. FPAAs are similar to digital field-programmable gate arrays (FPGAs) in that they allow for a system architect to program arbitrary connections of primitives to form larger systems. ...
Wearable medical devices, wireless sensor networks, and other energy-constrained sensing devices are often concerned with finding specific data within more-complex signals while maintaining low power consumption. Traditional analog-to-digital converters (ADCs) can capture the sensor information at a high resolution to enable a subsequent digital system to process for the desired data. However, traditional ADCs can be inefficient for applications that only require specific points of data. This work offers an alternative path to lower the energy expenditure in the quantization stage—asynchronous content-dependent sampling. This asynchronous sampling scheme is achieved by pairing a flexible analog front-end with an asynchronous successive-approximation ADC and a time-to-digital converter. The versatility and reprogrammability of this system allows a multitude of event-driven, asynchronous, or even purely data-driven quantization methods to be implemented for a variety of different applications. The system, fabricated in standard 0.5 μ m and 0.35 μ m processes, is demonstrated along with example applications with voice, EMG, and ECG signals.
... By contrast, Field-Programmable Analog Arrays (FPAAs) are switched-capacitor systems which architecturally resemble programmable logic devices (PLDs), but implement analog rather than digital circuitry, and enable the rapid physical deployment of near-arbitrary circuits based on only few commercially-available, general-purpose arrays. Representative devices include a multitude of arrays of interconnected and configurable analog blocks, each of which comprises 1) a set of operational amplifiers, 2) a set of capacitors having diverse values, 3) switch matrices allowing the realization of almost any combination of connections between the amplifiers and the capacitors, 4) one or more banks of static memory adapted to store a bit-string representing the current configuration and 5) means for externally uploading new configurations without disrupting operation [29]- [32]. Countless non-linear oscillators have been realized using this technology (see Ref. [33] for a review), and a recent study has introduced a circuit conjugating a rich dynamical repertoire with compactness [26]. ...
A novel hierarchical network based on coupled nonlinear oscillators is proposed for motor pattern generation in hexapod robots. Its architecture consists of a Central Pattern Generator (CPG), producing the global leg coordination pattern, coupled with six Local Pattern Generators (LPGs), each devoted to generating the trajectory of one leg. Every node comprises a simple non-linear oscillator and is well-suited for implementation in a standard Field-Programmable Analog Array (FPAA) device. The network enables versatile locomotion control based on five high-level parameters which determine the inter-oscillator coupling pattern via simple rules. The controller was realized on dedicated hardware, deployed to control an ant-like hexapod robot, and multi-sensory telemetry was performed. As a function of a single parameter, it was able to stably reproduce the canonical gaits observed in six-legged insects, namely the wave, tetrapod and tripod gaits. A second parameter enabled driving the robot in ant-like and cockroach-like postures. Three further parameters enabled inhibiting and resuming walking, steering, and producing uncoordinated movement. Emergent phenomena were observed in the form of a multitude of intermediate gaits, and of hysteresis and metastability close to a point of gait transition. The primary contributions of this work reside in the hierarchical controller architecture and associated approach for collapsing a large set of low-level parameters, stemming from the complex hexapod kinematics, into only five high-level parameters. Such parameters can be changed dynamically, an aspect of broad practical relevance opening new avenues for driving hexapod robots via afferent signals from other circuits representing higher brain areas, or by means of suitable braincomputer interfaces. An additional contribution is the detailed characterization via telemetry of the physical robot, involving the definition of parameters which may aid future comparison with other controllers. The present results renew interest into analog CPG architectures and reinforce the generality of the connectionist approach.
... Reconfigurable hardware platform is gaining increasing importance in all application areas of the semiconductor industry due to providing flexible customize application-specific integrated circuit (ASIC), and it is an attractive design for decreasing the monetary cost and circumventing the long development cycle [1]. Rapid-prototyping techniques for prototyping digital integrated circuits have become a widely endorsed approach in digital design for fast time-to-market products, such as the use of field programmable gate arrays (FPGAs) to cater particularly well reconfigurability. ...
In this paper, a NMOS-based wideband low power and linear tunable transconductance current differencing transconductance amplifier (CDTA) is presented. Based on the NMOS CDTA, a novel simple and easily reconfigurable configurable analogue block (CAB) is designed. Moreover, using the novel CAB, a simple and versatile butterfly-shaped FPAA structure is introduced. The FPAA consists of six identical CABs, and it could realize six order current-mode low pass filter, second order current-mode universal filter, current-mode quadrature oscillator, current-mode multi-phase oscillator and current-mode multiplier for analog signal processing. The Cadence IC Design Tools 5.1.41 post-layout simulation and measurement results are included to confirm the theory.
... To retain such rapid-prototyping capability and flexibility of FPGAs, previous commercial and academic efforts focused on an analog counterpart of the FPGA, namely field programmable analog arrays (FPAAs) [7]. Typical building blocks in an FPAA range from analog macros, such as switched capacitor circuits [8], [9], operational amplifiers and transconductance amplifiers [10], [11], to mega-modules like ADCs, DACs, track and hold circuits [2]. ...
Reconfigurable analog/mixed signal (AMS) platforms in scaled CMOS technology nodes are gaining importance due to the increased design cost, effort and shrinking time-to-market. Similar to field programmable gate arrays (FPGA) for digital designs, a Programmable ANalog Device Array (PANDA) provides a flexible and versatile solution with transistor-level granularity and reconfiguration capability for rapid prototyping and validation of analog circuits. This paper presents design and synthesis methodology of a PANDA design on 65 nm CMOS technology, consisting of a 24 × 25 cell array, reconfigurable interconnect, configuration memory and serial programming interface. To implement AMS circuits on the PANDA platform, this paper further proposes a CAD tool for technology mapping, placement, routing and configuration bit-stream generation. Several representative building blocks of AMS circuits, such as amplifiers, voltage and current references, filters, are successfully implemented on the PANDA platform. Dynamic reconfiguration capability of PANDA is demonstrated through input offset cancellation of an operational amplifier using an FPGA in a closed loop. Initial measurement results of PANDA implemented circuits demonstrate the potential of the methodology for rapid prototyping and hardware validation of analog circuits.
... Lee & Gulak, sub-thresh. FPAA[219], Xicor Digital Pot.[390], IMP Prog. Filter[135] Lee & Gulak, transcond. ...
... For example, when I 1p = 0.5 and HB = 0.1, its simulated THD is 16.08% and its ATHD is 16.33%. Table III shows the simulated absolute percentage error of ATHD compared with THD through (6). However, the ATHD index is estimated to evaluate the compensation performance instantaneously. ...
This paper proposes a FPAA-FPGA/DSP-based mixed signal controller that achieves superior performance when compared with conventional digital controllers in power quality compensation. This includes adaptive signal conditioning and programmability on-the-fly, higher flexibility, parallel computation capability, and easy implementation. In practical applications, the power quality compensator may suffer from poor compensation performance, particularly during light loading. The adaptive signal gain and programmable on-the-fly functions of the mixed signal controller are intended to improve the system compensation performance, which cannot be achieved by using conventional digital controllers alone. In this study, an approximate total harmonic distortion (ATHD) is proposed to determine the total harmonic distortion value more quickly, reducing the evaluation time of the power quality compensation system performance. With hysteresis pulse width modulations, when the hysteresis error margin is designed, the ATHD can be determined instantaneously. Finally, representative simulation and experimental results of a three-phase four-wire center-split hybrid active power filter are presented. These verify the validity and effectiveness of the proposed mixed signal controller in improving current quality compensation performance during light load conditions, compared with a conventional digital controller.
... Through the combination of primitive fixed and parametrically configurable elements, more complex building blocks can be formed (sometimes referred to as configurable analog blocks or ''CABs'' [98]), to include configurable oscillators, amplifiers, filters, and modulators. One of the most important building blocks is the programmable summing junction (Fig. 8), formed by combining a number of configurable resistances as shown in Fig. 8(a). ...
Reconfigurability can be thought of as software-defined functionality, where flexibility is controlled predominately through the specification of bit patterns. Reconfigurable systems can be as simple as a single switch, or as abstract and powerful as programmable matter. This paper considers the generalization of reconfigurable systems as an important evolving discipline, bolstered by real-world archetypes such as field programmable gate arrays and software-definable radio (platform and application, respectively). It considers what reconfigurable systems actually are, their motivation, their taxonomy, the fundamental mechanisms and architectural considerations underlying them, designing them and using them in applications. With well-known real-world instances, such as the field programmable gate array, the paper attempts to motivate an understanding of the many possible directions and implications of a new class of system which is fundamentally based on the ability to change.
... Of course, FPGAs as they are traditionally discussed are digital systems. Analog FPGAs have also been attempted [4,5,6]. In some devices, analog programmability is limited mostly to parametric adjustments of more elaborate versions of fixed building blocks [7]. ...
For adaptive space systems of the future, Air Force Research Laboratory's Space Electronics and Protection Branch (AFRL/VSSE) is pursuing the development of a microelectromechanical systems (MEMS)-based reconfigurable wiring manifold that can be programmed using techniques adapted from FPGA synthesis. The manifold is based on an interconnection network in a planar, multilayer printed wiring media into which are integrated a large number of micro-miniature latching relays. The relays, based on MEMS technology, can be integrated at densities above 100 / cm 2 . When integrated into a judiciously designed wiring media, these MEMS relays can be thought of as individual software-controlled wires, reducing pathway configurations on a large scale to a series of 0-1 programming decisions. Since the wires and relays of a complex configuration can be mapped into vertices and edges of a graph, solving for routing connections can be reduced to solutions of the associated graph Steiner forest. As such, many powerful FPGA routing techniques apply directly to this manifold. Other FPGA concepts applicable to the MEMS-wire manifold include configuration control (through the use of a JTAG interface) and extensibility of the wiring manifold through daisy-chaining the JTAG interfaces of a number of manifolds.
... The continuous-time approach offer a lower parameter range compared to the switched approach, but with particular design techniques, like the use of current conveyor for example, some very efficient analog blocks can be developed for the analog array. In the previous works [4][5] using the continuous-time approach for the design of fieldprogrammable analog array, the performance of the circuit were limited by the use of both Op-Amp based design and analog switches, preventing high-frequency operation of the circuits. ...
A design methodology for continuous time Field-Programmable Analog Array (FPAA) is presented. After introducing the key features of FPAA and dealing with design issues related to continuous-time applications, we present the elementary cell of the proposed FPAA. This cell is based on current conveyors and designed for high-frequency applications. Two examples are presented : a high-frequency amplifier and a high-frequency multiplier.
... Another trend in analog signal processing is to provide application flexibility and tunability through the incorporation of reconfigurable and programmable elements [4], [5], [14], [15]. Programmable and reconfigurable analog devices such as configurable analog blocks (CABs) are highly attractive for their fast and cost-efficient prototyping of analog circuits into field-programmable analog arrays (FPAAs) [16]. ...
A configurable analog block (CAB) architecture based upon the MOS translinear (MTL) principle is proposed. It is programmed to implement some current-mode nonlinear analog computational functions. The proposed CAB architecture consists of one cascoded MTL cell, a local switch network, and a pMOS array. The cascoded MTL cell implements one MTL loop that is reconfigurable and programmable using the switch network and the pMOS array. This CAB architecture is capable of implementing various frequently used nonlinear functions, such as squaring/inverse function, rectifying (absolute value), and square-rooting/geometric mean functions. The CAB has been fabricated in a 0.5- μm CMOS technology and verifies the concept. High capability and flexibility of the proposed CAB makes it suitable for current-mode analog computational and signal processing applications.
... Previous academic and industrial efforts focused on field programmable analog arrays (FPAA) with a wide range of configurable analog blocks (CAB) ranging from coarse grained macros such as operational amplifiers [1], operational transconductance amplifiers [2]- [4], switched capacitor circuits [5], ADCs and DACs [6] to medium grained primitives such as differential pairs and transconductors [7], [8]. FPAAs with transistor-level CABs known as field programmable transistors arrays (FPTAs) are explored in [9], [10] for evolvable hardware applications. ...
The design and development of analog/mixed-signal (AMS) integrated circuits (ICs) is becoming increasingly expensive, complex, and lengthy. Rapid prototyping and emulation of analog ICs will be significant in the design and testing of complex analog systems. A new approach, Programmable ANalog Device Array (PANDA) that maps any AMS design problem to a transistor-level programmable hardware, is proposed. This approach enables fast system level validation and a reduction in post-silicon bugs, minimizing design risk and cost. The unique features of the approach include: 1) transistor-level programmability that emulates each transistor behavior in an analog design, achieving very fine granularity of reconfiguration; 2) programmable switches that are treated as a design component during analog transistor emulating, and optimized with the reconfiguration matrix; and 3) compensation of ac performance degradation through boosting the bias current. Based on these principles, a digitally controlled PANDA platform is designed at 45 nm node that can map AMS modules across 22-90 nm technology nodes. A systematic emulation approach to map any analog transistor to 45 nm PANDA cell is proposed, which achieves transistor level matching accuracy of less than 5% for
I
<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub>
and less than 10% for
R
<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub>
and
G
<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub>
. Circuit level analog metrics of a voltage-controlled oscillator (VCO) emulated by PANDA, match to those of the original designs in 22 and 90 nm nodes with less than a 5% error. Several other 90 and 22 nm analog blocks are successfully emulated by the 45 nm PANDA platform, including a folded-cascode operational amplifier and a sample-and-hold module (S/H).
... Once the analog signal conditioning circuit to be designed is fixed, the design can be implemented by changing the capacitance values in the RAM array. Thus, taking the advantage of the switched capacitor technology [10], a wide variety of analog blocks like amplifiers with varying specifications can be realized by only changing the capacitance values. The FPAA configuration is performed by means of FPAA CAD tool, in which user can draw the desired analog circuit and send the related data block to FPAA device through RS232/USB communication [8]. ...
Leak Detector Remote Terminal Unit (LDRTU) is a single board, embedded
system that is used to acquire analog signals from leak detectors of secondary sodium loop
in Fast Breeder Reactor (FBR). This unit sends digitized data packets to the nearest Local
Control Centre (LCC) and generates control outputs in the form of potential free contacts
during all states of reactor operation. The design of analog circuitry in the above LDRTU
was realized with multiple numbers of discrete components like multiplexers, amplifier,
filter and analog to digital converter. This paper presents the design implementation of
Field Programmable Analog Array (FPAA) based LDRTU in which the complete analog
circuitry with discrete components are replaced by FPAA. The functionality of the above
circuitry is realized with this miniaturized FPAA chip. This design technique overcomes the
problems like obsolescence of components along with the added advantage of improved
reliability, reduced board space and power consumption. This paper also demonstrates the
performance of developed LDRTU with simulated sodium leak detector inputs.
... Once the analog signal conditioning circuit to be designed is fixed, the design can be implemented by changing the capacitance values in the RAM array. Thus, taking the advantage of the switched capacitor technology [10], a wide variety of analog blocks like amplifiers with varying specifications can be realized by only changing the capacitance values. The FPAA configuration is performed by means of FPAA CAD tool, in which user can draw the desired analog circuit and send the related data block to FPAA device through RS232/USB communication [8]. ...
Leak Detector Remote Terminal Unit (LDRTU) is a single board, embedded
system that is used to acquire analog signals from leak detectors of secondary sodium loop
in Fast Breeder Reactor (FBR). This unit sends digitized data packets to the nearest Local
Control Centre (LCC) and generates control outputs in the form of potential free contacts
during all states of reactor operation. The design of analog circuitry in the above LDRTU
was realized with multiple numbers of discrete components like multiplexers, amplifier,
filter and analog to digital converter. This paper presents the design implementation of
Field Programmable Analog Array (FPAA) based LDRTU in which the complete analog
circuitry with discrete components are replaced by FPAA. The functionality of the above
circuitry is realized with this miniaturized FPAA chip. This design technique overcomes the
problems like obsolescence of components along with the added advantage of improved
reliability, reduced board space and power consumption. This paper also demonstrates the
performance of developed LDRTU with simulated sodium leak detector inputs.
... The interconnection of elementary building blocks aiming at the configuration of more complex digital circuits has been a largely explored field, which has been originating even more complex field programmable gate arrays (FPGA). Efforts in developing integrated circuits that allows analog blocks (FPAA) to be programmatically interconnected in order to compose more complex systems are also reported in the literature [7]. Both approaches rely on wiring mechanisms able to establish a set of connections between these fundamental building blocks. ...
An internet-domain remotely controlled test board, on which real electronic circuits can be mounted and evalu-ated, is described in this paper. The physical arrangement of the server comprises a personal computer equipped with one GPIB controller, one bipolar power supply, two signal sources, a set of measurement instruments, one bi-dimensional relay-based interconnection matrix and a collection of uncommitted electronic building blocks. The whole operation of the system is based on a widely used graphical interface software. The usage cycle is initiated with the capture of the schematic diagram of the circuit to be tested, using the collection of components that are available at the server. Once the circuit is drawn and both the excitation signals and measurement points have been established by the user, a netlist is created obeying a cor-rect-by-construction mechanism and eventually uploaded to the server. On the server side, the content of the netlist is split into two parts: the arrangement of the circuit and the setup for all signal sources and measurement instru-ments. On-line results of the operating circuit can be cho-sen to be public or viewed only by the user. The herein described system is a valuable tool for circuit developers and a powerful teaching aid.
In spite of being the most popular reconfigurable platform for analog and mixed-mode design implementation, Field-Programmable Analog Array (FPAA) structures are limited to analog filters, amplifiers and communication circuits. Hexagonal FPAA is an established alternative to classical square-lattice FPAA but suitable architectures have not been cultivated much. In this paper, a hexagonal FPAA, implementing different nonlinear functions, eliminating global interconnections, and employing a graph-based mapping algorithm, has been proposed. For communication among the fundamental blocks and reconfiguration, it uses a local interconnection network consisting of central and corner switch blocks. The proposed mapping algorithm uses directed graph representations of fundamental blocks and desired circuits to map the nonlinear functions in the presented FPAA. Weights have been assigned to the graphs and manipulated for efficient placement and routing. All the theoretical predictions have been validated through SPICE simulation using 65 nm CMOS technology. The proposed architecture and mapping algorithm can be extended for large-scale FPAA enriched with automatic placement and routing tools.
This work focuses on reviewing the field programmable analog array (FPAA) architectures that eliminate the use of switches in signal path. The conventional FPAA architecture is composed of configurable analog blocks (CABs) connected together through switches in routing networks.The architectures covered in this survey have replaced the use of routing network by direct connection between CABs, and use of programmable analog building blocks. The first architecture covered is presented by Becker
et al.
with a hexagonal topology using operational transconductance amplifier (OTA) as a building block. The second architecture is presented by Mahmoud and Soliman, which uses the second generation current conveyor (CCII+) as a building block for their CABs arranged in a hexagonal architecture as well. Lastly, a more recent FPAA with a rectangular architecture proposed by Diab and Mahmoud is discussed, it uses the OTA as a building block for their rectangular architecture. The three FPAAs targeted continuous-time analog signal processing, having two architectures targeting high frequency applications, while the last targeting low frequency applications. The architectures, CAB structures, and the applications of each FPAA is covered separately in each section.
Large-scale field-programmable analog array (FPAA) devices could enable ubiquitous analog or mixed-signal low-power sensor to processing devices similar to the ubiquitous implementation of the existing field-programmable gate array (FPGA) devices. Design tools enable high-level synthesis to gate/transistor design targeting today's FPGA devices and the opportunity for analog or mixed-signal applications with FPAA devices. This discussion will illustrate the FPAA concepts and FPAA history. The development of FPAAs enables the development of multiple potential metrics, and these metrics illustrate future FPAA device directions. The system-on-chip (SoC) FPAA devices illustrate the IC capabilities, computation, tools, and resulting hardware infrastructure. SoC FPAA device generation has enabled analog computing with levels of abstraction for application design.
This work focuses on proposing FPAA architecture based on operational transconductance amplifier (OTA) as the basic block for low frequency continuous time signal processing. Two FPAA architectures are presented after a step by step development of the design structure. The architectures eliminate the use of switches for signal routing, instead they allow reconfigurability using a selecting network composed of OTAs. The proposed architectures demonstrate flexibility in architecture allowing the expansion of the basic structure. Both architectures allow the implementation of individual independent circuits with an option of cascading if required. Multiple filter circuits can be mapped on the FPAA with independent control and reconfigurability of gain, bandwidth, and notch frequency, thus allowing the use of the FPAA as a filter bank. As for the provided cascading feature, it allows the implementation of a system or a set of cascaded filters as desired by designer. Validation of proposed FPAA architecture and its characteristics is examined through simulation on LTspice using 90 nm CMOS technology with supply voltage of ± 0.6 V. A single 4th-order lowpass filter is implemented first and then a combination of amplifier, notch filter and lowpass filter is implemented. Simulation results of the filters on proposed FPAA is compared to results acquired from simulation of the circuits alone (off-FPAA) showing excellent agreement between both results, hence confirming the proposed FPAA architecture.
A fundamental capability of any system, whether conventional or neuromorphic, is the ability to have long-term memories whether for program control, parameter storage, or general configurability. This chapter provides an overview of a programmable analog technology based on floating-gate circuits for reconfigurable platforms that can be used to implement such systems. It covers basic concepts of floating-gate devices, capacitorbased circuits, and charge modification mechanisms that underlie this configurable analog technology. It also discusses the extension of these techniques to program large arrays of floating-gate devices. The analog programmability afforded by this technology opens up possibilities to a wide range of programmable signal processing approaches (e.g., image processing) enabled through configurable analog platforms, such as largescale field programmable analog arrays (FPAA).
This work presents a reconfigurable mixed-signal system-on-chip (SoC), which integrates switched-capacitor-based field programmable analog arrays (FPAA), analog-to-digital converter (ADC), digital-to-analog converter, digital down converter , digital up converter, 32-bit reduced instruction-set computer central processing unit (CPU) and other digital IPs on a single chip with 0.18 μm CMOS technology. The FPAA intellectual property could be reconfigured as different function circuits, such as gain amplifier, divider, sine generator, and so on. This single-chip integrated mixed-signal system is a complete modern signal processing system, occupying a die area of 7 × 8 mm ² and consuming 719 mW with a clock frequency of 150 MHz for CPU and 200 MHz for ADC/DAC. This SoC chip can help customers to shorten design cycles, save board area, reduce the system power consumption and depress the system integration risk, which would afford a big prospect of application for wireless communication.
Neuromorphic computing was originally referred to as the hardware that mimics neuro-biological architectures to implement models of neural systems. The concept was then extended to the computing systems that can run bio-inspired computing models, e.g., neural networks and deep learning networks. In recent years, the rapid growth of cognitive applications and the limited processing capability of conventional von Neumann architecture on these applications motivated worldwide research on neuromorphic computing systems. In this paper, we review the evolution of neuromorphic computing technique in both computing model and hardware implementation from a historical perspective. Various implementation methods and practices are also discussed. Finally, we present some emerging technologies that may potentially change the landscape of neuromorphic computing in the future, e.g., new devices and interdisciplinary computing architectures.
A current-mode field programmable analog array(FPAA) is presented in this paper. The proposed FPAA consists of 9 configurable analog blocks(CABs) which are based on current differencing transconductance amplifiers (CDTA) and trans-impedance amplifier (TIA). The proposed CABs interconnect through global lines. These global lines contain some bridge switches, which used to reduce the parasitic capacitance effectively. High-order current-mode low-pass and band-pass filter with transmission zeros based on the simulation of general passive RLC ladder prototypes is proposed and mapped into the FPAA structure in order to demonstrate the versatility of the FPAA. These filters exhibit good performance on bandwidth. Filter’s cutoff frequency can be tuned from 1.2MHz to 40MHz.The proposed FPAA is simulated in a standard Charted 0.18μm CMOS process with ±1.2V power supply to confirm the presented theory, and the results have good agreement with the theoretical analysis.
Approaches to constructing analog reconfigurable cells of integrated circuits with an array structure are discussed. A morphological method for synthesizing an analog reconfigurable cell and the criteria for estimating its efficiency are proposed. The design and electric circuit of the reconfigurable cell are developed and the results of circuit simulation are presented.
In this paper, the emergence of remote synchronization in a ring of 32 unidirectionally coupled non-linear oscillators is reported. Each oscillator consists of 3 negative voltage gain stages connected in a loop to which two integrators are superimposed and receives input from its preceding neighbour via a "mixing" stage whose gains form the main system control parameters. Collective behaviour of the network is investigated numerically and experimentally, based on a custom-designed circuit board featuring 32 field-programmable analog arrays. A diverse set of synchronization patterns is observed depending on the control parameters. While phase synchronization ensues globally, albeit imperfectly, for certain control parameter values, amplitudes delineate subsets of non-adjacent but preferentially synchronized nodes; this cannot be trivially explained by synchronization paths along sequences of structurally connected nodes and is therefore interpreted as representing a form of remote synchronization. Complex topology of functional synchronization thus emerges from underlying elementary structural connectivity. In addition to the Kuramoto order parameter and cross-correlation coefficient, other synchronization measures are considered, and preliminary findings suggest that generalized synchronization may identify functional relationships across nodes otherwise not visible. Further work elucidating the mechanism underlying this observation of remote synchronization is necessary, to support which experimental data and board design materials have been made freely downloadable.
We present a large-scale field programmable analog array that enables floating-gate (FG) adaptive circuits using FG-based switch technology. We present a novel architecture technology that enables switch routing with FG elements for signals resulting from high voltage adapting FG elements. We present careful analysis and characterization of the FG structure, including programming ranges, electron tunneling paths, to show the indirect programming structure involving an nFET device can handle the signals. We present the experimental data (350-nm commercial CMOS process) for a single-transistor adaptive structure, for a compiled autozeroing amplifier, and for multiple adaptive FG circuits.
This paper presents a novel field-programmable analog array (FPAA) architecture featuring a dual mode including discrete-time (DT) and continuous-time (CT) operation modes, along with a highly routable connection boxes (CBs) based interconnection lattice. The dual mode circuit for the FPAA is capable of achieving targeted optimal performance in different applications. The architecture utilizes routing switches in a CB not only for the signal interconnection purpose but also for control of the electrical charge transfer required in switched-capacitor circuits. This way, the performance of the circuit in either mode shall not be hampered with adding of programmability. The proposed FPAA is designed and implemented in a 0.18 μm standard CMOS process with a 3.3 V supply voltage. The result from post-layout simulation shows that a maximum bandwidth of 265 MHz through the interconnection network is achieved. The measured results from demonstrated examples show that the maximum signal bandwidth of up to 2 MHz in CT mode is obtained with the spurious free dynamic range of 54 dB, while the signal processing precision in DT mode reaches 96.4%.
This paper presents a core cell that can be reconfigured and combined with current mirrors to implement exponential, logarithmic, multiplier, divider and raise-to-power function circuits. The proposed circuit uses CMOS transistors operating in the strong inversion. The proposed circuits has been verified with the 0.8µm CMOS technology by HSPICE simulations. The simulations results confirm the functionality of the proposed circuits. The proposed circuits paves the way for designing analog signal processors.
The limited power budgets of sensor networks necessitate some level of in-network pre-processing to reduce communication overhead. The low power consumption of analog signal processing (ASP) is well-suited for this task. However, the quick adoption of this technology has been restrained by the fact that ASP implementation requires a priori knowledge of the application space. Our solution to this challenge is to enable run-time reconfiguration through the use of a field-programmable analog array (FPAA). In the same way that reconfigurable digital systems allow system designers to change the infrastructure of digital blocks, an FPAA allows an application developer to change the infrastructure of, and even tune, ASP blocks without circuit-level expertise. We will demonstrate that an FPAA can be used to (1) facilitate the use of ASP to reduce power consumption, and to (2) allow run-time reconfigurability to maximize ASP impact.
In this paper, the authors present work in the field of analog emulation of electric power system dynamics via field-programmable analog array (FPAA) technology. Specifically, they discuss development of a new emulation tool with increased modularity and operator density for analysis of larger power systems and smart grids. One innovative aspect of this work is the fact that it employs custom FPAA boards developed by researchers at The College of New Jersey and Drexel University. The work places emphasis on decreased prototype size, increased density of computational analog blocks (CABs), more effective FPAA interconnection scheme, and batch-mode FPAA configuration.
This paper presents a spike event coding scheme for the communication of analog signals in programmable analog arrays. In the scheme presented here no events are transmitted when the signals are constant leading to low power dissipation and traffic reduction in analog arrays. The design process and the implementation of the scheme in a programmable array context are explained. The validation of the presented scheme is performed using a speech signal. Finally, we demonstrate how the event coded scheme can perform summation of analog signals without additional hardware.
In this article, the design of configurable analogue blocks for field programmable analogue arrays is presented. The configurable blocks are capable of performing integration, differentiation, amplification, log, anti-log, add and negate functions. The realisation of these functions depends on differential continuous-time current-mode translinear loop techniques. To maintain high frequency operation, the programmability and configurability of the blocks are achieved by modifying the block's biasing conditions digitally. Simulation results for the presented circuits are included.
The "Reconfigurable Wires" project explores the reliability of gold-gold surfaces used in some microelectromechanical systems (MEMS) implementations of relays and postulates alternate formulations. The research has the exciting potential to: (1) immediate improvement in reliability of MEMS relays: (2) development of new devices that operate in non-traditional current/voltage regimes; (3) improvement in the current handling, constriction resistance, and reliability of macro-relays. The three primary products of this research to date are: (1) a journal paper on MEMS nanoscale contact surface morphology, (2) an invention disclosure on arc suppression schemes in micro-relays, and (3) an unpublished finding on the properties of 2-D randomized arrangements of "sticks" in 3-D.
The development of complex microelectronic systems confronts the design teams with a large variety of problems. Looking at the overall design time, validation requires in general significantly more than 50% of the resources. Furthermore, the composition of the design teams have noticeably changed: Although at the beginning of the 1990s, about one third of the design team was involved in validation issues, one decade later already over two thirds of the team was dealing with these issues. Two fundamental trends are observed in the VLSI community that contribute to the continuous increase of this effect in the future. On one hand, increasing system complexity because of tremendous advances in integration technology, and on the other hand, tighter time-to-market constraints.
A new configurable analogue block (CAB), the key element in the design of field programmable analogue arrays (FPAAs), is introduced in this paper. This CAB is based on wave equivalents of the passive elements and it is easily reconfigurable resulting in very simple and versatile FPAA structures. The proposed topology employs a minimum number of switches in the signal path due to the absence of the interconnection network required in other FPAA structures, and thus an improved performance is achieved in comparison with the already introduced corresponding programmable configurations. Copyright © 2008 John Wiley & Sons, Ltd.
Field Programmable Gate Arrays (FPGAs) and Field Programmable Analog Ar-rays (FPAAs) are devices used in applications where real time is considered the main feature. In this paper some important new trends in the field of analog de-vices are presented. Starting with a short presentation of the technology followed by a few examples of implemented applications, the paper ends up with two new ideas, mixed signal architecture and evolvable hardware. In summary, this new field of FPAA reprogrammable devices appears as a new challenge when dealing with real-time control.
Systems on chip, by definition, unite a number of functions and occasionally, sensors or actuators, into a unified, com-pact, lower-power solution to a signal processing problem. Recent efforts have seen the research, development, and commercialization of systems on chip that are sufficiently programmable and flexible to address a wider variety of applications and signal processing problems than their fixed configuration counterparts. In this paper, we present the application of a recently commercialized SoC effort to the problem of interrogating a low frequency radio fre-quency transponder, using an amplitude shift keyed encod-ing scheme. Within this representative application, the following reductions are realized compared to a discrete implementation: power 64%, cost 71%, component count 96%, and size 95%. In addition, the better matched compo-nents in the SoC provide a 25% improvement in read range over the discrete implementation of the radio frequency identification interrogator. INTRODUCTION Modular and user-defined design of electronic circuits is progressing rapidly in the integrated circuit industry. Reconfigurability and programmability of systems is most often associated with digital logic, such as in the popular Field Programmable Gate Array (FPGA). Modular, pro-grammable, and mixed signal Systems on Chip (SoC), however, are gaining popularity in addressing a wide vari-ety of user-defined applications, alongside their purely dig-ital counterparts. The ability to dynamically configure analog circuit blocks, digital circuit blocks, and the inter-connections between them on a single integrated die is key to facilitating rapid product development while maintain-ing the high level of precision and performance afforded by integrated circuits as compared to assemblies of discrete circuits. In addition to decreasing development time, pro-grammable mixed signal SoC offer the potential to signifi-cantly reduce power, component count, size, and cost of a wider variety of systems than purely digital SoC can address.
It is argued that the large interconnectivity and the precision required in neural network models present novel opportunities for analog computing. Analog circuits for a wide variety of problems such as pattern matching, optimization, and learning have been proposed and a few have been built. Most of the circuits built so far are relatively small, exploratory designs. Circuits implementing several different neural algorithms, namely, template matching, associative memory, learning, and two-dimensional resistor networks inspired by the architecture of the retina are discussed. The most mature circuits are those for template matching, and chips performing this function are now being applied to pattern-recognition problems. Examples of analog implementation are examined.< >
The interest in analog circuit techniques for implementing neural nets is undiminished, as is indicated by a large number of recent designs, coming from universities as well as from industry. One group of circuits are networks containing the "multiply-accumulate" neurons with a large interconnectivity. The main motivation for using analog circuit techniques is the fact that the multiply-accumulate operation can be implemented compactly, if only a moderate precision of the computation is required. Other types of networks are more algorithm-specific, hard-wired for one function, for example Kohonen networks, or neuromorphic designs implementing functions found in the visual or the auditory system. Most neural nets are built with standard CMOS technology, except for a few designs in CCD technology. A few analog neural net chips are now commercially available, and more and more reports of applications are appearing. This is a significant step in the development of analog neural nets, as now their usefulness is being put to the test in "real-world" applications.
Since its inception, VLSI theory has expanded in many fruitful and interesting directions. One major branch is layout theory which studies the efficiency with which graphs can be embedded in the plane according to VLSI design rules. In this survey paper, I review some of the major accomplishments of VLSI layout theory and discuss how layout theory engendered the notion of area and volume-universal networks, such as fat-trees. These scalable networks offer a flexible alternative to the more common hypercube-based networks for inter-connecting the processors of large parallel supercomputers. Keywords: Integrated circuits; Interconnection networks; Parallel computing; Super-computing; Universality; Thompson's model; Tree of meshes.
A class of interconnection networks based on some existing permutation networks is described with applications to processor to memory communication in multiprocessing systems. These networks, termed delta networks, allow a direct link between any processor to any memory module. The delta networks and full crossbars are analyzed with respect to their effective bandwidth and cost. The analysis shows that delta networks have a far better performance per cost than crossbars in large multiprocessing systems.
The author presents a new class of universal routing networks, called fat-trees, which might be used to interconnect the processors of a general-purpose parallel supercomputer. A fat-tree routing network is parameterized not only in the number of processors, but also in the amount of simultaneous communication it can support. Since communication can be scaled independently from the number of processors, substantial hardware can be saved for such applications as finite-element analysis without resorting to a special-purpose architecture. It is proved that a fat-tree of a given size is nearly the best routing network of that size. This universality theorem is established using a three-dimensional VLSI model that incorporates wiring as a direct cost. In this model, hardware size is measured as physical volume. It is proved that for any given amount of communications hardware, a fat-tree built from that amount of hardware can stimulate every other network built from the same amount of hardware, using only slightly more time (a polylogarithmic factor greater).
A circuit has been designed and fabricated which implements a
self-organizing algorithm proposed by T. Kohonen (1984). It uses a
competitive learning process which modifies weights such that similar
input feature vectors are clustered into distinct classes. This network
learns without supervision. Matching is accomplished by computing the
squared Euclidean distance at each node between the input and the
current weight vector. Connections to each node are implemented with
multiplying D/A converters. The weights are stored in dynamic RAM
registers at each connection. The design minimizes circuit area by using
unary encoding in the weight representation to permit the use of shift
operations in the adaption process and by sharing the circuits used in
weight adaptation and the activation computations
Analog VLSI implementations of adaptive systems, either of the traditional variety or the more complex types frequently found in neural network models of learning, require variable analog weights which are compact and have substantial resolution. The authors have designed a chip in ordinary 1.25- μm CMOS which stores analog weights as charge on MOS capacitors. The weights, of which there are 1104 per chip, can be updated in parallel along a vector in weight space, allowing for efficient implementations of gradient descent algorithms. The chips are organized as 46×24 matrix multipliers with voltage inputs and current outputs
The electronic implementation of neuromorphic systems requires
technologies well matched to the functions of storage and the
computation of sums of products. Additional requirements are low-power,
high fan-out capability and high-density interconnect. Massive
parallelism and redundancy mitigate the accuracy limitations of analog
circuits and force consideration of analog and analog-digital components
for network realization. Adaptive neuromorphic networks have the
potential for self-organization and learning in speech and image
understanding systems requiring minimal human intervention
Techniques from coding theory are applied to study rigorously the capacity of the Hopfield associative memory. Such a memory stores n -tuple of pm 1 's. The components change depending on a hard-limited version of linear functions of all other components. With symmetric connections between components, a stable state is ultimately reached. By building up the connection matrix as a sum-of-outer products of m fundamental memories, one hopes to be able to recover a certain one of the m memories by using an initial n -tuple probe vector less than a Hamming distance n/2 away from the fundamental memory. If m fundamental memories are chosen at random, the maximum asympotic value of m in order that most of the m original memories are exactly recoverable is n/(2 log n) . With the added restriction that every one of the m fundamental memories be recoverable exactly, m can be no more than n/(4 log n) asymptotically as n approaches infinity. Extensions are also considered, in particular to capacity under quantization of the outer-product connection matrix. This quantized memory capacity problem is closely related to the capacity of the quantized Gaussian channel.
This paper discusses the design of a primary memory system for an array processor which allows parallel, conflict-free access to various slices of data (e.g., rows, columns, diagonals, etc.), and subsequent alignment of these data for processing. Memory access requirements for an array processor are discussed in general terms and a set of common requirements are defined. The ability to meet these requirements is shown to depend on the number of independent memory units and on the mapping of the data in these memories. Next, the need to align these data for processing is demonstrated and various alignment requirements are defined. Hardware which can perform this alignment function is discussed, e.g., permutation, indexing, switching or sorting networks, and a network (the omega network) based on Stone's shuffle-exchange operation [1] is presented. Construction of this network is described and many of its useful properties are proven. Finally, as an example of these ideas, an array processor is shown which allows conflict-free access and alignment of rows, columns, diagonals, backward diagonals, and square blocks in row or column major order, as well as certain other special operations.
A generic chip is implemented in CMOS to facilitate studying
networks by building them in analog VLSI. By utilizing the well-known
properties of charge storage and charge injection in a novel way, the
authors have achieved a high enough level of complexity (>10<sup>3
</sup> weights and 10 bits of analog depth) to be interesting, in spite
of the limitation of a modest 6.00×3.5-mm<sup>2</sup> die size
required by a multiproject fabrication run. If the cell were optimized
to represent fixed-weight networks by eliminating weight decay and
bidirectional weight changes, the density could easily be increased by a
factor of 2 with no loss in resolution. Once a weight change vector has
been written to the RAM cells, charge transfers can be clocked at a rate
of 2 MHz, corresponding to peak learning rates of 2×10<sup>9</sup>
weight changes/second and exceeding the throughput of `neural network
accelerators' by two orders of magnitude
Banyan networks for partitioning [4]Analog electronic neural network circuits
- L R Coke
- G J Lipovski
- H P Graf
L. R. Coke and G. J. Lipovski, "Banyan networks for partitioning [4] H. P. Graf and L. D. Jackel, "Analog electronic neural network circuits,'' IEEE Circuits Devices Mag., vol. 5, no. 4, pp. 44-49, July 1989.
Field programmable analog arrays-A CMOS realization
- E K F Lee
E. K. F. Lee, "Field programmable analog arrays-A CMOS realization," M.A.Sc. thesis, Univ. Toronto, Toronto, Ont., Canada, 1991.
The capacity of the Hopfield associative memory IT-33Processor-memory interconnections for multiprocessorsElectronic implementation of neuromorphic systemsA programmable analog neural network chip
- R J Mceliece
- E C Posner
- E R Rodemich
- S S Venkatesh
- J H D B Patel
- R E Schwartz
- W E Howard
- Hubbard
R. J. McEliece, E. C. Posner, E. R. Rodemich, and S. S. Venkatesh, "The capacity of the Hopfield associative memory," IEEE Trans. Inform. Theory, vol. IT-33, no. 4, pp. 461-482, July 1987. [ 111 J. H. Patel, "Processor-memory interconnections for multiprocessors," in Proc. 6th Annual Symp. Computer Architecture, 1979, pp. 168-177. [ 121 J. I. Raffel, "Electronic implementation of neuromorphic systems," in Proc. IEEE I988 Crrstom Integrated Circuits Conf., 1988, pp. 1131 D. B. Schwartz, R. E. Howard, and W. E. Hubbard, "A programmable analog neural network chip," IEEE. J. Solid-state Circuits, vol. 24, no. 2, pp. 313-319, Apr. 1989.
83) received the Ph.D. degree in electrical engineering from the University of Manitoba From February he was a Research Associate in the Information Systems Presently he is an Assistant Professor in the
- Glenn Gulak
Glenn Gulak (S'82-M'83) received the Ph.D.
degree in electrical engineering from the University of Manitoba, Winnipeg, Man., Canada.
From February 1985 to January 1988 he was a
Research Associate in the Information Systems
Laboratory and the Computer Systems Laboratory at Stanford University, Stanford, CA.
Presently he is an Assistant Professor in the
Department of Electrical Engineering at the
University of Toronto, Toronto, Ont., Canada.
His research interests include VLSI circuits and
essing and digital communications.
Sc degree from the University of Toronto
- I Systems
- K F Edward
I
systems for signal proc
Edward K. F. Lee received the B.A.Sc degree
from the University of Windsor, Windsor, Ont.,
Canada, in 1988 and the M.A.Sc degree from
the University of Toronto, Toronto, Ont., in
1991. Currently, he is with the Department of
Electrical Engineering, University of Toronto,
where he is working towards the Ph.D. degree.
His research interests are in the areas of analog/digital cessing.
circuits, VLSI design, and signal