Stretchable transistors and functional circuits for human-integrated electronics

Abstract

Electronics with skin- or tissue-like mechanical properties, including low stiffness and high stretchability, can be used to create intelligent technologies for application in areas such as health monitoring and human–machine interactions. Stretchable transistors that provide signal-processing and computational functions will be central to the development of this technology. Here, we review the development of stretchable transistors and functional circuits, examining progress in terms of materials and device engineering. We consider the three established approaches for creating stretchable transistors: buckling engineering, stiffness engineering and intrinsic-stretchability engineering. We also explore the current capabilities of stretchable transistors and circuits in human-integrated electronics and consider the challenges involved in delivering advanced applications.

Full text

Review ARticle
https://doi.org/10.1038/s41928-020-00513-5
1Pritzker School of Molecular Engineering, The University of Chicago, Chicago, IL, USA. 2Nanotechnology and Science Division, Argonne National
Laboratory, Lemont, IL, USA. 3These authors contributed equally: Yahao Dai, Huawei Hu. ✉e-mail: sihongwang@uchicago.edu
Electronics is increasingly focused on connecting more and
more objects for efficient information collection and exchange,
ultimately creating an Internet of Everything. Collecting infor-
mation from human bodies is central to the development of such
ideas, and could lead to intelligent and ubiquitous healthcare1,
human/machine interfaces2 and even advanced human capabili-
ties3. However, this will require electronic devices that can be inter-
faced with various parts of the human body and that are capable of
collecting signals with sufficient quality, resolution and stabil-
ity. Such electronics need to have skin- or tissue-like mechani-
cal form factors4–6 and, in particular, should be capable of
deforming to strains of tens of per cent without degradation in
electronic performance.
Transistors will be central to the development of stretchable
electronics, serving as the building-block elements in circuits for
signal processing and computation. Imparting stretchability to
transistors and then functional circuits is thus a key goal in achiev-
ing fully functional stretchable electronics (Fig. 1). The primary
limitation is the lack of stretchable electronic materials4,7. To solve
this issue, three general approaches have been established for
imparting stretchability into transistors and circuits: buckling engi-
neering, stiffness engineering and intrinsic-stretchability engineer-
ing. These approaches address the problem across all levels, from
the entire electronic patch, to devices and down to the level of the
component materials. They each have their own characteristics
and advantages (Table 1), as well as distinct challenges for further
developments.
In this Review, we first consider the working mechanisms and
material components of transistors, then examine the three estab-
lished strategies for creating stretchable transistors. We also explore
the use of stretchable transistors and circuits in human-integrated
electronics and consider the challenges involved in creating
advanced capabilities towards next-generation electronics.
Basic knowledge and materials for field-effect transistors
There are two main types of field-effect transistor (FET): the
junction field-effect transistor (JFET)8 and the metal–oxide–
semiconductor field-effect transistor (MOSFET)9. MOSFETs are
more frequently used in integrated circuits (ICs) due to their large
input impedance and compatibility with both depletion and enhance-
ment modes. A typical MOSFET is a three-terminal device with three
electrodes (source, drain and gate), a semiconducting channel and
a dielectric layer. MOSFETs are further classified into two general
types according to the geometry of the semiconducting channel: the
conventional bulk type (Fig. 2a), fabricated on a single-crystal silicon
wafer that serves as both the substrate and the bulk semiconductor
layer10, and the thin-film transistor (Fig. 2b), with a semiconduc-
tor thin-film layer deposited on a separate inactive substrate, which
broadens the choice of semiconductor to emerging materials beyond
silicon11. As such, there is now a rich library of semiconducting mate-
rials being used for transistors. These include germanium, III–IV
compounds12 (such as GaN and GaAs), oxides13 (such as indium
gallium zinc oxide), carbon-based materials14,15 (such as graphene
and carbon nanotubes), transition-metal dichalcogenides16 and con-
jugated organic molecules and polymers17–19. However, none of the
high-performance semiconducting materials meet the requirements
for stretchable transistors and circuits because of their rigid and frag-
ile mechanical properties: that is, Young’s modulus typically above
1 GPa and fracture strain typically below 5%. To achieve stretchable
devices, innovations are thus required in materials and/or device
design to impart stretchability either on the entire electronic circuit/
system level or on the single-device level.
For the development of stretchable transistors (Fig. 2e), the over-
all goal is to combine skin-like stretchability (a strain level above
50%) with the high electrical performance of transistor devices, as
well as the integration capability for circuit development, which is
mainly subject to the device density, fabrication yield and perfor-
mance uniformity. The key figures of merit for the electrical per-
formance of transistors (Fig. 2c,d) are the threshold voltage (VT),
subthreshold swing (SS), on/off ratio (Ion/Ioff ), transconductance
(gm) and the cutoff frequency (fT)20. VT represents the gate-voltage
boundary that switches a transistor between open-circuit (off) and
short-circuit (on) states. SS quantifies how fast such switching takes
place in the subthreshold region. Lower VT and smaller SS are key to
achieving low power consumption. For digital applications mainly
based on transistors switching between on and off states, the ratio
Ion/Ioff needs to be sufficiently high, typically >104. For analogue
applications, gm is the key figure of merit, describing how effectively
Stretchable transistors and functional circuits for
human-integrated electronics
Yahao Dai1,3, Huawei Hu 1,3, Maritha Wang1, Jie Xu 2 and Sihong Wang 1 ✉
Electronics with skin- or tissue-like mechanical properties, including low stiffness and high stretchability, can be used to cre-
ate intelligent technologies for application in areas such as health monitoring and human–machine interactions. Stretchable
transistors that provide signal-processing and computational functions will be central to the development of this technology.
Here, we review the development of stretchable transistors and functional circuits, examining progress in terms of materials
and device engineering. We consider the three established approaches for creating stretchable transistors: buckling engineer-
ing, stiffness engineering and intrinsic-stretchability engineering. We also explore the current capabilities of stretchable tran-
sistors and circuits in human-integrated electronics and consider the challenges involved in delivering advanced applications.
NATURE ELECTRONICS | www.nature.com/natureelectronics

Review ARticle NaTurE ElEcTroNicS
the gate voltage (VG) modulates the drain current (ID), which is
defined as
gm
¼dI
D
dVG
¼
W
L
μC
i
V
D
when V
D<
V
G�
V
T
W
L
μC
i
V
G�
V
T
ðÞ
when V
D
>V
G�
V
T

where W and L are the channel width and length respectively, μ is
the charge-transport mobility, Ci is the gate dielectric capacitance
per unit area and VD is the drain voltage. Finally, the dynamic per-
formance of transistors for processing alternating current signals is
evaluated by the cutoff frequency fT for effective switching, which
is given by
fT¼gm
2πCG
ffi
μV
D
2πLLþ2Lov
ðÞ
when V
D<
V
G�
V
T
μVG�VT
ðÞ
2πLLþ2Lov
ðÞ
when VD>VG
�
VT
(
Here, CG is the total gate capacitance, which is given by
C
G
¼
Cch
þ
2Cov
ffi
CiWL
þ
2Lov
ðÞ
I
, where Cch is the channel
capacitance, Cov is the parasitic gate-overlap capacitance and Lov is
the gate-overlap length with drain/source electrodes.
The physical origins of these figures of merit suggest the follow-
ing electrical-performance-relevant requirements for the develop-
ment of stretchable transistors (Fig. 2e): semiconductors with high
μ; dielectrics with high dielectric constant κ; optimized semiconduc-
tor/dielectric interfaces; miniaturized device sizes from improved
fabrication processes and optimized electrode/semiconductor con-
tacts. For integration into functional circuits, stretchable transistors
are also subject to the requirements of sufficiently high device den-
sity, fabrication yield and performance uniformity (Fig. 2e).
When moving transistors to stretchable designs, the fundamen-
tals of device physics would need to incorporate the influences of
applied strains, so that the evolvement of the transistors’ perfor-
mance under stretching could be predicted. For the engineering
strategies (that is, stiffness engineering and buckling engineering)
that exert a minimal level of strain on the transistor devices, the
device performance is not affected by strain. However, when the
applied global strain goes beyond the threshold value set by the least
stretchable component in the overall designs, device failure usually
happens as a result of a broken component and/or a delaminated
interface. In contrast, for transistors that operate under strains
through intrinsic stretchability, an in-depth understanding of the
influence of strain on the device performance is highly needed,
which, for the above-described figures of merit, can be divided into
two aspects: the influences on the material parameters (including
μ of the semiconductor, Ci of the gate dielectric and conductivity
of the electrodes), which could come from the changes of a certain
material’s structural morphology and/or layer-to-layer interface
morphology; and the influences on the device geometric param-
eters (including W and L).
Buckling-engineering-enabled stretchable transistors and
circuits
Before research into stretchable electronics began, extensive efforts
had been made in the development of flexible electronics21 that can
undergo bending–unbending deformations. These developments
laid an important foundation for one of the strategies for realizing
stretchable electronics, which is to convert in-plane stretching to
out-of-plane unbending deformation through a buckled structure
(Fig. 3a). Beginning with this mechanical behaviour, the buckling
engineering method was devised as a generally applicable strategy
for making stretchable transistors from almost any material that can
be fabricated into flexible thin films.
In general, the formation of buckled structures can be realized by
several methods, including pre-stretch–release22,23, compression24,
moulding25,26, solvent swelling27, thermal expansion28 and 3D print-
ing29. Among these, the pre-stretch–release and moulding methods
have been adopted the most for building stretchable transistors. In
the pre-stretch–release method22,23, flexible thin films are first fabri-
cated on rigid substrates and then transferred onto a pre-stretched
2008 2011 2013 2015 2016 2017 2018
(i) Stretchable silicon
circuits with buckling
(iii) Stretchable silicon circuits
with stiffness engineering
(iv) Stretchable organic
transistors with buckling
(ii) Stretchable organic transistors
with stiffness engineering
(v) Stretchable organic transistors
with stiffness engineering
(vi) Intrinsically stretchable CNT
transistors
(vii) Intrinsically stretchable polymer
transistors
(viii) Intrinsically stretchable
polymer transistor arrays
and circuits
1 mm
Antenna
Wireless power coil RF coil RF diode ECG/EMG sensor
LED Strain gauge Temp. sensor 0.5 mm
200 µm
Elastomer matrix (SEBS)
Nanoconfinement
Stretchable
semiconductor
Aggregates
Stretchable
electrode
Stretchable
substrate
+
Organic transistor
SWNT paste and
elastic conductor
Source
Pentacene
Drain
Gate
SWNT
paste
Polyimide
Silicone rubber
SWNT paste and
elastic conductor
Silicone rubber
SWNT paste (interconnection)
Elastic conductor
(bit-line)
Elastic conductor (word-line)
Semiconducting CNTs
Unsorted CNTs
TPU dielectric
TPU substrate
Fig. 1 | Evolution of stretchable transistors and functional circuits. From left to right: (i) stretchable silicon circuits (2008); (ii) organic field-effect transistor
(OFET) active matrix (2008); (iii) stretchable epidermal electronics (2011); (iv) stretchable OFET (2013); (v) stretchable OFET active matrix (2015); (vi)
stretchable CNT-based transistor (2016); (vii) intrinsically stretchable OFET (2017); (viii) stretchable OFET active matrix (2018). TPU, thermoplastic
polyurethane. Scale bar in (v), 20 mm. Figure adapted with permission from: (i), ref. 22, AAAS; (ii), ref. 47, AAAS; (iii), ref. 86, AAAS; (iv), ref. 23, Springer
Nature Ltd; (vii), ref. 62, AAAS; (viii), ref. 74, Springer Nature Ltd. Figure reproduced with permission from: (v), ref. 45, Springer Nature Ltd; (vi), ref. 54, Wiley.
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elastomeric substrate. The release of the stretching causes the film to
buckle. In the moulding method24,25, the buckled structures are built
into a thin film by depositing it onto substrates with a wavy surface.
Buckling engineering on functional materials. Buckling engineer-
ing can be adopted to introduce stretchability into non-stretchable
functional layers, which can be further integrated into stretchable
devices. This has been demonstrated with single-crystal silicon. By
transferring microfabricated single-crystal silicon ribbons onto a
pre-stretched elastomeric substrate and then releasing the substrate,
the resulting wavy structures (Fig. 3b, top) can accommodate 10%
stretching on the elastomer substrate30. Using this method, stretch-
able transistors have been realized by incorporating other functional
layers (metals and dielectrics) before buckle formation. In addition
to conferring stretchability to rigid materials, the pre-stretch–release
process can also serve to increase the stretchability of moderately
stretchable layers. For example, the stretchability of semiconduct-
ing single-walled carbon nanotube (SWCNT) films can be effec-
tively increased by buckle formation during repeated stretching and
releasing steps31.
The moulding method — the other buckling appro ach that is easy
to implement — has also been applied to functional materials25,26.
One representative example was made using an Al2O3 thin film, one
of the most widely used high-κ dielectric materials, by depositing it
on rough copper foils (Fig. 3b, bottom). By incorporating the buck-
led Al2O3 with graphene as the semiconductor, the obtained transis-
tor achieved a stretchability of 20%25.
Buckling engineering on full devices. The buckling method can
also be applied directly to completed transistor devices fabricated
on flexible substrates22,23. This allows the transistor fabrication
process to be decoupled from the buckle formation processes, so
that any type of flexible transistor23 — even circuits22 — can oper-
ate with global strain applied to the elastomeric substrates. For
example, the pre-stretch–release method has been utilized to fab-
ricate buckled silicon complementary metal–oxide–semiconductor
(CMOS) circuits22. To reduce the maximum bending-induced strain
on non-stretchable layers, those layers were made to be thin and
were placed closer to the mechanical neutral plane. As a result, such
CMOS circuits can maintain unaltered performance with 5% global
strain (Fig. 3c, top) and are able to preserve their performance after
30 stretching cycles.
To further increase the stretchability of devices, a greater amount
of buckling needs to be introduced, but the bending-induced ten-
sile/compressive strains should not exceed the fracture onset strains
of any of the material components. Hence, the improvement in
stretchability can be achieved by using materials with larger frac-
ture strains. A state-of-the-art work implemented this strategy by
Table 1 | Comparison of stretchable transistors based on three general approaches and traditional silicon technology
Buckling engineering Stiness engineering Intrinsic-stretchability
engineering Silicon-based
integrated circuits
Material requirements Semiconductors Nearly all the
semiconductors Nearly all the
semiconductors Conjugated polymers;
semiconducting CNT
networks
Single-crystal silicon
Dielectrics Nearly all the
dielectrics, high-κ
dielectrics are mostly
used
Nearly all the
dielectrics, high-κ
dielectrics are mostly
used
Elastomers or elastomer
composites SiO2, Si3N4
Fabrication Key process Transfer printing;
buckles generation Transfer printing;
bonding between rigid
island and stretchable
substrate
Layer-on-layer deposition
and patterning Deposition, oxidation,
metallization,
lithography
Yield Medium Low High Ultrahigh
Electrical performance Mobility (cm2 V−1 s−1) 290 (n-type
silicon22); 140 (p-type
silicon22); 10 (CNT31);
40 (graphene25);
0.88 (organic
semiconductor23)
370 (n-type silicon35);
130 (p-type silicon35);
0.48–1.8 (organic
semiconductor45,47)
27 (CNT54);
0.1–2 (polymer
semiconductor55,62)
1,000 (n-type);
450 (p-type)
Operation voltage Low (1–10 V) Low (1–10 V) High (10–30 V) Very low (<1 V)
Integration capability Channel length 100–200 μm
(refs. 22,23,25)200–500 μm (refs. 35,45) 50–200 μm (refs. 60,62,74) 7 nm
Device density (cm−2) Up to 280 (ref. 22) Up to 400 (ref. 35) Up to 347 (ref. 74) Over 10 billion
Stretchability Highest stretchability ~5% for silicon22;
~20% for CNT31
and graphene25;
~100% for organic
semiconductors23
~100%35,45 Up to 600%62 Non-stretchable
Strain distribution In-plane strain
is converted to
out-of-plane local
bending
Not uniform, the strain
is mostly taken by the
interconnects
Uniform
Suitable applications Analogue signal
conditioning, digital
computations
Digital computations Sensing, multiplexing,
analogue signal
conditioning
Multiplexing, analogue
signal conditioning,
digital computations
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using organic semiconductors as the transistor channel layer and
sandwiching the functional devices between two ultrathin polymer
foils23, enabling a global stretchability of 233%. Moreover, the device
shows nearly unaltered performance under 100% strain for over
200 cycles and can be operated at high temperatures and in aqueous
environments (Fig. 3c, bottom).
Perspective. In general, the most prominent advantages of the
buckling engineering method are its simplicity in execution and
its broad applicability to large groups of materials and device
structures. Additionally, electrical performance is almost com-
pletely decoupled from the mechanical deformations because of
the low level of bending-induced strain. However, as the buckling
formations are stochastic processes in each of the releasing pro-
cesses, the bending-induced maximum strains at the microscopic
scale could have some variations among different releasing cycles32.
Multicycle stretching robustness thus needs to be studied further,
both experimentally and theoretically. Furthermore, buckling
VD
VG
Saturation
ID
dc
log ID
ID
1/2
VT
Ion/off
VG
a b
● Material deformability
● Stable layer-to-layer bonding
● Optimized strain distribution
e
–––––––––
Current
Gate DrainSource
n+n+
VG
VD
Dielectric
Bulk-type MOSFET Thin-film transistor
Charge carriers
Semiconductors
L
VG
VD
Dielectric
Gate
Source Drain
W
Linear
1
SS = Slope
● High-µ semiconductor
● High-κ and high-strength
dielectric
● Optimized semiconductor/
dielectric interface
● Efficient charge
injection
● High device density
● High yield
● Uniform device
performance
● Scalable
production
E
l
e
c
t
r
i
c
a
l
p
e
r
f
o
r
m
a
n
c
e
I
n
t
e
g
r
a
t
i
o
n
c
a
p
a
b
i
l
i
t
y
S
t
r
e
t
c
h
a
b
i
l
i
t
y
+++++++++++++
–––––––––––––
Stretchable
transistors
Fig. 2 | Schematic representations of transistor structures and the transfer and output characteristic curves. a, A conventional bulk-type MOSFET.
b, A thin-film transistor. c, A typical transfer curve of the transistor. Key figures of merit, including threshold voltage (VT), subthreshold swing (SS)
and on/off ratio (Ion/off), are shown. d, A typical output curve of the transistor. e, Performance metrics in the development of stretchable transistors.
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engineering often leads to roughened device surfaces and usually
needs relatively thick substrates, which can be a challenge for form-
ing intimate interfaces with biological tissues. Additionally, for
applications that require transparency in devices (for example, pho-
todetectors), the buckled configuration could interfere with light
penetration. More innovations in device design are desired to miti-
gate these side effects. Also, to enable scalable fabrication of transis-
tor arrays, innovations are required to achieve a uniform large-scale
buckling-formation process.
Stiffness-engineering-enabled stretchable transistors and
circuits
In general, circuit systems are spatially heterogeneous, with
three types of area: functional-device-occupied areas, conductive-
interconnect-occupied areas and empty spacing areas. To impart
global stretchability, there is plenty of mechanical-engineering
space that can be explored for varying the strain dissipation
pattern among these different types of area. As such, stretchability
can be imparted to functional devices through appropriate mechan-
ical designs that dissipate most of the applied strain into the empty
and interconnect areas, leaving the functional devices experiencing
minimal strain (Fig. 4a). In this way, stretchability is only a demand
for conductors that serve as interconnects.
From solid mechanics, when a strain is applied onto a continuum
object, the generated local strain is inversely proport ional to the local
stiffness33. Therefore, the strain applied to functional devices can be
effectively reduced by increasing the stiffness of the device regions.
This stiffness engineering has become another major approach that
can enable the use of non-stretchable devices to achieve stretchable
circuits. However, it should be noted that such non-uniform strain
distribution in a mechanically heterogeneous structure is typically
accompanied by the generation of large stresses at soft/stiff bound-
aries. As a result, the system-level stretching robustness largely
relies on strong adhesion at such boundaries.
Stretchable conductors as interconnects. As described above,
having stretchable conductors is crucial for realizing the stiffness
engineering approach. Conventionally, metals have been the only
class of materials serving as conductors in electronics. Certainly,
there are liquid-phase metals (for example, mercury, gallium-based
alloys) with intrinsic ductility (Fig. 4b(i)) that have been extensively
explored for their use in stretchable electronics34. However, due to
Buckled Al
2
O
3
Organic transistor
Functional materials
Semiconductors
Dielectrics
Buckled single-crystal silicon
Full devices
Silicon-based circuits
Organic thin-film transistors
CMOS circuit
Releasing
Stretching
a
cb
Fig. 3 | Buckling-engineering-enabled stretchable transistors and circuits. a, Schematics of the stretchability enabled by buckling engineering. b, Buckling
engineering on functional materials for stretchable transistors: buckled single-crystalline silicon prepared by the pre-stretch–release method (top); buckled
Al2O3 prepared by moulding on rough copper foils (bottom). c, Buckling engineering on full devices: buckled silicon CMOS circuits (top); buckled organic
thin-film transistor (bottom). Figure reproduced with permission from: b (top), ref. 30, AAAS; b (bottom), ref. 25, Springer Nature Ltd; c (top), ref. 22,
AAAS; c (bottom), ref. 23, Springer Nature Ltd.
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their structural instability compared with solid-state materials,
challenges arise when trying to use them to build devices with both
miniaturized size and long-term stability. As such, many engineer-
ing efforts and breakthroughs have been made to impart stretch-
ability to solid-state metals and other conductors7, mainly through
the design of strain-dissipative geometries, including buckling
structures and micro/nanostructure networks. For the buckling
geometry, not only the out-of-plane buckling reviewed above, but
also in-plane buckling designs (for example, serpentine designs)
have proven to be effective for generating stretchability up to
100%35 (Fig. 4b(ii)). In parallel, micro/nanostructure networks can
also deform to large strains without breaking the conducting
percolations (Fig. 4b(iii)), which is similar to the deformability
in kirigami structures36. Because the structural regularity in kiri-
gami patterns is not an essential requirement for deformability,
micro/nanostructure networks can be built by some simple
approaches, including the formation of microcracks during initial
stretching37 and the assembly of pre-synthesized conductive nano-
structures (for example, Ag nanowires38, Ag nanoparticles/flakes39
and CNTs40).
More recently, conductive polymers, such as poly(3,4-
ethylenedioxythiophene) polystyrene sulfonate (PEDOT:PSS) that
is inherently rigid and brittle due to its high crystallinity, have been
successfully engineered to be stretchable through blending with
plasticizers41 and/or surfactants42, as well as by the engineering of
processing conditions43. Representatively, the plasticizer-blending
method (Fig. 4b(iv)) has achieved the highest ever stretchability
up to 600% strain41. For more detailed discussions about stretch-
able conductors, there are several recently published review papers
particularly focused on this topic7,44.
Functional devices
Integrated circuits
Integrated
circuit
Transistors
Transistor
Releasing
Stretching
Functional device
Interconnect
Interconnects
Inorganic
conductors
Organic
conductors
Conductive polymers
(i)
(iii)
(iv)
Liquid metals
Buckling geometries
(ii)
Micro/nanostructure networks
Ag flakes
Fluorine rubber Ag nanoparticles
a
cb
Fibre
Metal
STEC Crystalline PEDOT
Fig. 4 | Stiffness-engineering-enabled stretchable transistors and circuits. a, Schematics of the stretchability enabled by stiffness engineering.
b, Stretchable interconnects that dissipate major strain under global stretching: (i) liquid metal with inherent stretchability; (ii) metals with buckling
geometry; (iii) micro/nanostructure network composed of Ag nanoparticles/nanosheets and elastomers; (iv) highly stretchable conductive polymer
prepared by blending PEDOT:PSS with plasticizers. STEC, stretchability and electrical conductivity (STEC) enhancers. c, Functional devices as ‘rigid
islands’: as-fabricated transistors (top; scale bar, 5 mm); chip-scale ICs (bottom). Figure reproduced with permission from: b(i), ref. 87, Wiley; b(ii), ref. 35,
copyright (2008) National Academy of Sciences, USA; b(iii), ref. 39, Springer Nature Ltd; b(iv), ref. 41, reprinted with permission of AAAS, © The Authors,
some rights reserved; exclusive licensee AAAS. Distributed under a Creative Commons Attribution NonCommercial Licence 4.0 (CC BY-NC); c (top),
ref. 45, Springer Nature Ltd; c (bottom), ref. 50, Springer Nature Ltd.
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Functional devices as rigid islands. With the stiffness engineer-
ing approach, almost any type of transistor can, in principle, be
used for stretchable electronics. To achieve this, transistors are
usually fabricated on patterned flexible supporting layers (for exam-
ple, polyimide) and then placed onto elastomeric substrates, as iso-
lated islands. The increase in local stiffness is provided by either
the flexible supporting layer35 or surrounding elastomeric sub-
strates with increased crosslinking density39,45. This design concept
has been successfully applied to thin-film transistors built with a
variety of semiconductors, including silicon35,46 and organic
small molecules (for example, pentacene47 and dinaphthothieno-
thiophene (DNTT)45) (Fig. 4c, top). These have demonstrated
mobility values in the range of 0.1–1 cm2 V−1 s−1. By applying
stiffness engineering designs to single-crystal silicon CMOS tran-
sistors35, mobilities up to 100–400 cm2 V−1 s−1 at 100% strain can
be provided. Meanwhile, such devices remain stable after being
stretched for over 1,000 cycles. The key fabrication innovations for
building such systems include the creation of single-crystal silicon
nanoribbon structures30 and the physical transfer of these silicon
nanoribbons onto a flexible substrate48. However, such multiple
physical transfer steps cause challenges for achieving high yield and
alignment resolution.
With its very loose requirements in terms of transistor
form factors for achieving global stretchability, the stiffness
engineering approach has also enabled the integration of com-
mercial IC chips into stretchable electronics (Fig. 4c, bottom).
However, the rigid and bulky nature of IC chips makes it chal-
lenging to achieve stable bonding between the hard chips and
the adhered stretchable substrate under large strains. This can be
resolved by adding support posts on elastomeric substrates for
chip bonding49 and/or by embedding chips in a soft medium50.
More recently, to further increase the device density for more
advanced functions, three-dimensional (3D) stacking of multiple
chip-bonded stretchable layers has been realized51. This approach
allows the possibility of using state-of-the-art electronic compo-
nents to realize fully functional and stand-alone stretchable elec-
tronic systems.
Perspective. Up to now, most advanced applications of stretch-
able electronics have been realized by stiffness engineering
approaches49,51. An important advantage of this, worth noting here,
is that the electrical functions are almost completely decoupled
from the stretching until mechanical failure (for example, delamina-
tion or fracture) is reached. For further enhancement of the stretch-
ability, investigations and optimizations are needed to achieve the
following: (1) more robust mechanical designs for stretchable sys-
tems to allow for tolerance-unpredicted strain distributions arising
from possible fabrication non-uniformities and (2) stronger adhe-
sion between soft and hard interfaces. More specifically, fabrication
using elemental transistors faces the challenges of improving the
fabrication yield and transistor density, whereas the use of IC chips
typically gives rise to bulkier devices, for which special designs are
needed to build intimate skin/tissue interfaces. Overall, because
certain human-integrated applications require not only global
stretchability but also other favourable mechanical properties (for
example, softness and local deformability), in-depth investigations
are needed to assess the suitability of stiffness-engineered systems
for such applications.
Intrinsically stretchable transistors and circuits
High performance and good integration capability are the two
main aspects of requirements for transistors. The two device-level
strategies for imparting stretchability discussed above can pre-
serve the inherent electrical performance of materials and devices,
but inevitably sacrifice integration capability, which is determined
by the fabrication yield, device density and uniformity. These
limitations can be bypassed by utilizing a fundamentally different
approach (Fig. 5a), that is, to impart stretchability as an intrinsic
property to electronic materials (semiconductors, conductors and
dielectrics), while maintaining their original functionalities.
Structurally, a material’s stretchability can only be obtained
from loosely packed structures. Such structures are commonly
found in polymers52, making them a promising material family for
providing inherent stretchability. Other than this, the percolated
networks of 1D nanostructures can also render thin films with
macroscopic continuity and stretchability53, as discussed in the
last section. Hence, for the development of intrinsically stretchable
semiconductors, conjugated polymers19 and 1D nanomaterials (for
example, CNTs54) with semiconducting properties emerge as the
two major avenues.
Intrinsically stretchable semiconductors. Extensive research
efforts in the past 40 years have led to the development of con-
jugated polymers with charge-carrier mobility in the range of
1–10 cm2 V−1 s−1, which rivals that of poly-silicon17. However, those
high-mobility polymers still have very limited stretchability due
to their typical planar backbone architectures and relatively high
crystallinity. Because large mechanical deformability can only be
afforded by disordered and loosely packed structures, the main
challenge for achieving intrinsically stretchable polymer semicon-
ductors is to moderately reduce the chain ordering and packing,
without affecting the charge-transport properties. Generally, this
challenge can be addressed by the following three engineering strat-
egies: backbone engineering, side-chain engineering and morpho-
logical engineering.
Towards achieving a more flexible polymer chain to obtain
high deformability, the demonstrated backbone engineer-
ing approaches (Fig. 5b(i), left) include building random copo-
lymers55, incorporating soft segments56,57 and introducing
backbone torsions58. Among these, incorporating soft segments
has been explored the most. One representative design incorpo-
rates alkyl segments, carried out through either block copolymer56
or conjugation spacer approaches57. More recently, the backbone
engineering strategy was further extended to the incorporation of
supramolecular interactions59 (that is, dynamic bonds) between
backbones (Fig. 5b(i), right) to dissipate strain energy. However,
these backbone modifications to some extent affect charge-carrier
delocalization along or across the polymer, thus sacrificing
charge-carrier mobility.
Compared with the modifications on backbones, engineer-
ing side chains with bulky and/or soft segments (Fig. 5b(ii),
left) could serve to increase the stretchability by weakening the
interactions between polymer chains while having less influ-
ence on the electrical performance. Synthetically, such side-chain
modification can be implemented during monomer synthesis60
or through post-polymerization attachment61. One representa-
tive example is an isoindigo-based conjugated polymer modified
with the bulky carbosilane side chain60 (Fig. 5b(ii), right), which
gained a stretchability of 100% strain while still providing mobility
above 1 cm2 V−1 s−1.
Despite the high structural tunability provided by the backbone
and side-chain engineering methods, these synthetic approaches
can be technically complicated. Opportunities also lie in the physical
engineering of polymer morphologies via the processing conditions
so as to enhance the chain dynamics62–65 (Fig. 5b(iii), left). Along this
line, we recently created a facile and versatile approach based on the
nanoconfinement effect62. By simply blending a conjugated polymer
with an elastomer (Fig. 5b(iii), right) to enable nanoscale phase sep-
aration, a percolated nanoconfined morphology could be achieved.
The afforded nanoconfinement effect enabled a stretchability
of over 100% strain without affecting the charge-carrier mobil-
ity. Moreover, this approach was shown not only to be broadly
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Review ARticle NaTurE ElEcTroNicS
applicable to a variety of conjugated polymer structures, but
also to demonstrate excellent shelf stability. More recently, this
nanoconfinement design has been combined with a solution-shearing
method to achieve multiscale ordering, which further enhances the
mobility66. Several other polymer-physics-originated concepts have
also been created for engineering stretchability63,64.
Intrinsically stretchable transistor array
(iii)(i)
Azide crosslinker
Elastomer
(ii)
Stretchable semiconductors
Carbon nanotubes
Polymer semiconductors
Side-chain engineering
(i)
Backbone engineering
=
(ii)
(iii)
Morphological engineering DPPT-TT + SEBS
DPPT-TT + SEBS
SEBS
a
c
b
Releasing
Stretching
C10H21
C10H21 C10H21
O
O
SS
S
S
O
NN
H
N
H
O
S
SSx
O
O
N
N
1–x
S
N
X
N
C10H21
C10H21
C10H21
C10H21
C10H21
X
R
N
N
R
Si
R=
S
Sn
O
O
N3
HN
HN
HN
NH
NH
NH
H
N
Stretchable
substrate
Fully patterned
intrinsically
stretchable
transistor
Fig. 5 | Intrinsically stretchable transistors and circuits. a, Schematics of intrinsically stretchable transistors. b, Schematics of typical stretchable
semiconductors and general strategies for designing stretchable polymer semiconductors: (i) backbone engineering (left) and a diketopyrrolopyrrole
(DPP)-based polymer semiconductor with PDCA modified backbone (right); (ii) side-chain engineering (left) and an isoindigo-based polymer
semiconductor modified with a bulky carbosilane side-chain structure (right); (iii) morphological engineering (left) and a stretchable polymer
semiconductor prepared by blending DPPT-TT with SEBS (right). c, Scalable fabrication of an intrinsically stretchable transistor array: (i) schematics of
the intrinsically stretchable transistor array and magnified image of one transistor in the array; (ii) a direct photo-patterning process for dielectrics; (iii) an
intrinsically stretchable transistor array on the fingertip, with device density of 347 cm−2. Figure reproduced with permission from: b(i) right image, ref. 59,
Springer Nature Ltd; b(ii) right image, ref. 60, American Chemical Society; c, ref. 74, Springer Nature Ltd. Figure adapted from: b(iii) right image, ref. 62, AAAS.
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Review ARticle
NaTurE ElEcTroNicS
Although polymer semiconductors are promising materials with
excellent inherent stretchability, it should be noted that the mor-
phologies of polymer films can evolve during repeated strain cycles,
which might present a challenge for achieving unaltered electrical
performance from such films during repeated stretching. For
example, a slight increase in the roughness of a polymer film has
been observed during multiple stretch–release cycles, contributing
to a gradual decrease in mobility62. On the other hand, because of
the typical high stretchability of the functional layers, intrinsically
stretchable transistors can better avoid a complete loss of function
as a result of repeated stretching.
Besides conjugated polymers, SWCNTs have also been explored
as a material system for the development of stretchable semicon-
ductors. In contrast to polymer semiconductors, SWCNTs form
percolated networks to transport charges, and their stretchability
comes from the reorientation and sliding of individual tubes53. CNT
networks, with macroscopic charge transport limited by conduc-
tion at tube-to-tube junctions, can provide mobilities as high as
80 cm2 V−1 s−1 (ref. 67), which is a major advantage over polymer
semiconductors. Benefiting from this, when SWCNTs are fabricated
into intrinsically stretchable transistors, the resulting transistors
display mobilities as high as 15 cm2 V−1 s−1, accompanied by stretch-
ability over 100%54. However, because the strain-induced morpho-
logical changes on SWCNT networks are usually irreversible, the
strain typically has a non-negligible influence on electrical perfor-
mance. In addition to such structural instability, semiconducting
SWCNTs usually have inferior ambient stability68 compared with
polymer semiconductors.
Intrinsically stretchable dielectrics. In contrast to the inherent
lack of stretchability of semiconductors, stretchable dielectrics have
been readily accessible since the first discovery of rubber. Several
existing elastomers, including polydimethylsiloxane (PDMS) and
polystyrene-block-poly(ethylene-ran-butylene)-block-polystyrene
(SEBS), have been utilized as gate dielectrics to achieve intrinsically
stretchable transistors with good operation stability59,62. However,
the main limitation of these non-polar elastomers is their relatively
low dielectric constants (in the range of 2–3), which lead to a high
operation voltage (>10 V) for the resulting stretchable transistors.
To overcome this limitation, research efforts have been devoted
to finding or creating elastomers with higher dielectric constants,
either by exploring more polar elastomers, such as poly(vinylidene
fluoride-co-hexafluoropropylene) (PVDF-HFP) and polyure-
thane (PU)69, or compositing with non-stretchable high-κ fillers70.
However, these high-κ elastomers tend to facilitate the delocaliza-
tion of ionic impurities, often leading to an electrical-double-layer
effect and thus a frequency-dependent performance71. On the other
hand, such an electrical-double-layer effect can be utilized to largely
decrease the operation voltage when the transistors are not used for
high-frequency applications. This is exemplified by the use of ionic
gels (made with intrinsic stretchability) as stretchable dielectrics72,73,
which give an operation voltage lower than 2 V and an operation
frequency up to 1 kHz.
Besides the intrinsic material property, the film quality of the
as-fabricated dielectric layers is the other equally important factor
for achieving higher capacitance and thus lower operation voltage.
Therefore, innovations in conformable film deposition methods for
such elastomeric films are also greatly needed.
Scalable fabrication of intrinsically stretchable transistors. With
the availability of intrinsically stretchable materials, the next main
challenge in the development of intrinsically stretchable electron-
ics is the scalable and reliable fabrication of integrated transistors
and circuits74,75. Because of the differences in many physicochemi-
cal properties of inorganic materials, most polymers are incom-
patible with lithography-based microfabrication processes.
This has been a long-standing challenge for polymer electronics
over the past 40 years, since its inception. Recently, our research
has successfully filled this gap through the development of a fab-
rication platform for intrinsically stretchable transistor arrays
(Fig. 5c(i))74. The key innovations in this fabrication plat-
form include a direct photo-patterning process for dielectrics
(Fig. 5c(ii)), an etching-based patterning process for polymer
semiconductors and effective harnessing of orthogonal poly-
mers as sacrificial layers. This platform has been shown to have
broad material applicability, without any sacrifice in performance.
Furthermore, the achieved transistor arrays have demonstrated
the expected advantages of intrinsically stretchable electronics:
scalable fabrication with a high yield of 94% and a high density of
347 cm−2 (Fig. 5c(iii)).
Perspective. In pursuit of stretchable ICs with complex functions
for practical applications, there are still several major aspects to
be improved: increasing the mobility, which needs innovations
in molecular design and processing methods for polymer semi-
conductors; reducing the operating voltage from the current level
of 30 V to below 5 V, which needs the development of stretchable
dielectrics with higher permittivity in conjunction with the inven-
tion of conformable film deposition methods; miniaturization
of devices and increasing the device density, which needs further
innovations in fabrication methods together with a significant
improvement in charge injection at the electrode contacts76,77 to
alleviate the short-channel effect; and developing n-type stretch-
able transistors. Other challenges faced by polymer semiconductors
also need to be taken into consideration during the developmental
efforts, including insufficient ambient stability, imperfect thin film
uniformity and batch-to-batch variations in polymer synthesis. The
first demands the identification and/or development of a stretch-
able encapsulation material with good air impermeability. The latter
two could be improved by the development of precision synthesis
methods and improvements in thin-film deposition processes for
polymer semiconductors.
Applications of stretchable transistors and circuits
In general, transistors in electronic systems are mainly used for
signal processing between input and output terminals, and can
be categorized into three general functions: multiplexing, ana-
logue signal conditioning and digital computation. Transistors
are also utilized as sensing elements for various types of signal.
Proof-of-concept demonstrations have shown that stretchable tran-
sistors can perform all four functions (Fig. 6a), suggesting future
work on developing fully functionalized stretchable systems.
Sensing. When serving as the transduction device for sensing,
transistors can typically offer higher sensitivity than other device
options, afforded by their built-in signal amplification function.
A large group of sensing mechanisms and material/device designs
have been developed by using transistors for sensing different types
of signal78,79. An early work demonstrated an intrinsically stretch-
able temperature sensor based on a transistor-like structure that
employs a temperature-sensitive and stretchable composite as
the channel material80. More recently, fully CNT-based stretch-
able transistors were developed for temperature sensing by tak-
ing advantage of the temperature-dependent behaviour of charge
transport in semiconducting SWCNT networks (Fig. 6b)81. The
most important advancement in this work is the use of a differen-
tial circuit design strategy to suppress the influence of strain on the
readout signal. Moving forward, there are many more innovations
to be explored towards realizing sensing functions for different
types of signal (pressure, vibration, moisture and various biomark-
ers) based on different material/device designs. Regardless of the
application, to achieve reliable sensing performance under
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Review ARticle NaTurE ElEcTroNicS
stretching, sensor designs need to decouple the influence of strain
from the sensing functions.
Multiplexing. For signal reading and writing from/to arrayed input/
output (I/O) devices such as sensors and light-emitting diodes, mul-
tiplexing operation is generally favoured to avoid crosstalk and to
reduce the number of wirings. Multiplexing has been realized by an
array of transistors, namely an ‘active matrix’, in which each transis-
tor or small group of transistors addresses one I/O device element.
So far, this has been realized in a number of stretchable electronic
systems. For example, using stiffness engineering designs, rigid
silicon82,83 and organic small-molecule transistors40 have been inte-
grated with their corresponding functional devices (for example,
light-emitting diodes) on rigid islands, which are supported by
an elastomer substrate to enable global stretchability (Fig. 6c).
Additionally, recent work has demonstrated the fabrication of an
intrinsically stretchable active matrix interfaced with a tactile sen-
sor array, with the advantages of high device density (25 pixels cm−2)
and outstanding skin conformability74. Overall, given that the aim
of arrayed integration is usually to achieve high density, the intrin-
sically stretchable approach could be more favourable for build-
ing an active matrix. To move forward in realizing higher working
frequencies and further reduced crosstalk, it is necessary to upgrade
the 1-transistor (1T) design that is currently prevalent in demon-
strated stretchable arrays to more complicated structures such as
2-transistor–1-capacitor (2T1C) designs84.
Analogue signal conditioning. Biological and physiological signals
are among the chief measurement targets for stretchable electron-
ics. However, they are typically weak in amplitude/intensity and are
therefore easily affected by interference from various types of back-
ground noise. Hence, robust amplification and filtering are needed
for the effective recording and processing of such signals. In early
research into buckling engineering of silicon transistors, differential
amplifiers with a stretchability of 5% strain were demonstrated22.
Intrinsically stretchable transistors, which exhibit superior con-
formability with the skin, could be a preferred choice for providing
on-site amplification by directly interfacing with skin and tissue.
Recently, a first generation of an intrinsically stretchable transis-
tor array was realized using self-biasing pseudo-CMOS designs,
achieving a gain of 4.7, a frequency bandwidth of ~50 Hz and a
stretchability of over 100% strain (Fig. 6d)74. In future work towards
achieving effective amplification of different types of bio-signal,
material and device innovations are needed to maximize the gain
and bandwidth. Also, based on the achieved amplifiers, stretchable
filters and analogue-to-digital converter (ADC) circuits are waiting
Multiplexing
a
Digital computation
Sensing
Analogue signal conditioning
cb
ed
Buckling engineering
Stretchable
transistors
and circuits
Stiffness engineering
Intrinsically stretchable
Sensing
Multiplexing
Analogue
Digital computation
42
39
36
33
30
27
24
21
Temperature (°C)
Output (V)
Bending
Hairdryer on
Time (s)
0 5 10 15 20 25 30 35 40 45 50 55 60
0.90
0.95
1.00
1.05
1.10
1.15
1.20
1.25
1.30
Data line
OLED
Trselector
Trdriver
Ground line
C
Bias-voltage line
Scanning line
Vdata Vbias
Vscan
Iselector
IOLED
Strain sensor
for pulse
GND Vsensor
Cin
VDD
Cu wires
Pulse sensor
100 mV
25 ms
Intrinsically stretchable
amplifier
Unconditioned pulse signal
Amplified pulse signal
Vout
VSS
GND
R0
R
0%
510–3
10–7
10–11
–6 –3 0 3 6
Vg (V)
∣Id∣ (A)
120
100
80
60
40
20
0
Gain
5
4
4
3
3
2
2
1
1
0
0
Vout (V)
Vin (V)
Fig. 6 | Applications for stretchable transistors and circuits. a, Summary of main application areas. b–e, Representative examples for the different
application areas: stretchable temperature sensor (b); stretchable active-matrix organic light-emitting diode (AMOLED) array (c); stretchable
sensor–amplifier system for pulse measurements (d); stretchable digital circuits (inverter) (e). Figure reproduced with permission from: b, ref. 81,
Springer Nature Ltd; c, ref. 40, Springer Nature Ltd; d, ref. 74 , Springer Nature Ltd; e, ref. 22, AAAS.
NATURE ELECTRONICS | www.nature.com/natureelectronics

Review ARticle
NaTurE ElEcTroNicS
to be realized, which can be designed with relaxed requirements for
skin conformability.
Digital computations. In most advanced electronic systems, the
‘brains’ are typically processors (central processor units and micro-
processors) that implement algorithms with different functions.
Such processors usually contain millions of transistors, with logic
gates as the building-block elements. So far, several types of logic
gate have been realized, including inverters (Fig. 6e)22, NAND and
NOR gates, and ring oscillators, with stretchability ranging from
5% to 100% strain74,75,85. The potential functions of logic gates in
stretchable systems generally include wireless communications,
d.c.-to-a.c. signal conversions and further integration into proces-
sors. Among these, the integration of stretchable logic gates into
processor development is the most challenging due to the need for
an exceptionally large number of devices. This poses very demand-
ing requirements in terms of device yield, performance uniformity
and device density. As the processor module is the central informa-
tion processing hub, it does not necessarily need to be placed at the
skin/tissue location for signal collection and/or delivery. It could
therefore be located in body areas where relatively lower strains
are created. As such, the stiffness engineering approach for the
incorporation of commercial silicon chips could be a highly via-
ble option for introducing digital computations into stretchable
electronic systems.
Outlook
Three technological pathways have been established for creating
stretchable transistors and circuits — buckling engineering, stiff-
ness engineering and intrinsic-stretchability engineering — and
proof-of-concept applications have been demonstrated. However,
challenges remain in terms of material innovation, device fabrica-
tion and circuit design architecture. In addition, to maximize the
utility of the technology, a broad understanding is required of the
pros and cons of these general approaches in terms of their different
functionalities and applications.
The design of stretchable transistors is still based on the
device physics of silicon transistors. However, the involvement of
substantial mechanical strain during device operation and the use
of unconventional device structures give rise to relatively unex-
plored device physics. A deeper understanding of the device
physics of stretchable transistors will provide important informa-
tion for the design and optimization of such transistors along all
three engineering pathways. Furthermore, improvements in both
electronic performance and mechanical robustness will largely come
from the continuous development of stretchable functional materials,
including conductors, semiconductors and insulators. For semi-
conductors and conductors, excellent charge-transport capa-
bilities — characterized by mobility and conductivity — are
needed. Additionally, precise control of electronic structure and
charge-carrier density are required to build high-performance
devices. Developments in stretchable insulators are also needed to
improve substrates, dielectrics and stable packaging layers with mini-
mal oxygen and water permeability.
At the device level, substantial enhancements in device densi-
ties are needed to build complex circuit structures within reason-
able device areas. Such improvements will come from the creation
of new fabrication methods and optimization of the fabrication
of multiscale mechanical structures. Furthermore, the strategy of
stacking 2D device layouts into multilayer 3D architectures could
deliver a substantial increase in device densities. Developments
in the large-area fabrication of stretchable transistors will also be
important, preferably using additive manufacturing processes,
which can better take advantage of solution-processable materials
with low-cost production. The larger device counts required for
more complex circuit designs will, however, create much higher
requirements in terms of device yield and uniformity, creating
another key challenge that will need to be resolved.
Finally, the application of complicated circuits also demands a
materials-to-device strategy for effective thermal control, because
the low thermal conductivities of elastomers necessitate the addi-
tion of heat-dissipation designs. Systematic progress in the creation
of circuits with higher complexities will require the development of
compact models for transistor structures operating under stretch-
ing, the realization of CMOS units and circuit design strategies for
mitigating strain effects.
Received: 25 May 2020; Accepted: 19 November 2020;
Published: xx xx xxxx
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Acknowledgements
This work is supported by the start-up fund from the University of Chicago. J.X.
acknowledges support from the Center for Nanoscale Materials, a US Department of
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Science, under contract no. DE-AC02-06CH11357.
Author contributions
Y.D., H.H. and S.W. researched the data and wrote the manuscript. M.W. and J.X.
reviewed and edited the manuscript. All authors discussed the contents and provided
important contributions to the manuscript.
Competing interests
The authors declare no competing interests.
Additional information
Correspondence should be addressed to S.W.
Peer review information Nature Electronics thanks Tsuyoshi Sekitani and the other,
anonymous, reviewer(s) for their contribution to the peer review of this work.
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