A Novel Pseudo NMOS Integrated CC -ISFET Device for Water Quality Monitoring

Abstract

The paper presents a performance analysis of Novel CMOS Integrated Pseudo NMOS CC –ISFET (PNCC-ISFET) having zero static power dissipation. The main focus is on simulation of power and performance analysis along with the comparison with existing devices, which are used for water quality monitoring. This approach can improve calibration of device to a fairly wide range without the use of a high speed digital processor. The conventional devices generally used, consume high power and are not stable for long term monitoring. The conventional devices have a drawback of low value of slew rate, high power consumption, and non linear characteristics. In the proposed design(PNCC-ISFET) due to zero static power, low value of load capacitance on input signals, faster switching, use of fewer transistors and higher circuit density the device exhibits a better slew rate, piece-wise linear characteristic, and is seen consuming low power of the order of 30mW. The functionality of the circuit is tested using Tanner simulator version 15 for a 70nm CMOS process model. The proposed circuit reduces total power consumption per cycle, increases speed of operation, is fairly linear and simple to implement. This device has a simple architecture, and hence is very suitable for water quality monitoring applications.

Full text

A Novel Pseudo NMOS Integrated CC -ISFET Device for
Water Quality Monitoring
I. INTRODUCTION
Water is vital for all known forms of life. With the
expansion of industrial production and increase in the
population every year, wastewater produced by industry
discharged into rivers and lakes due to which the qual-
ity of water is degraded. Hence, it is most urgent to
take effective measure to monitor and protect the water
resources. The supervision of water quality is generally
done by taking and analysing some sample liquid in the
laboratory. This method is very expensive, tedious and it
can take several weeks to get tests result. Many research
works have contributed to design quality measuring de-
vices [1-3]. But it’s always a challenge to select a more
precise and accurate device for monitoring the quality
of water. In Today’s scenario very complex functions
are realized. Also, there is a growing demand for high
density VLSI circuit’s which result in scaling of Vdd
and an exponential increase of leakage or static power
in deep sub-micron technology. Therefore reducing
static power consumption of portable devices for water
quality monitoring applications is highly desirable for a
long term monitoring. As the size of the transistor de-
creases (i.e Technology) the transistors density per unit
chip increases. Due to scaling of the device and large
integration of the transistors on the single chip leads to
increase in temperature and higher power consumption
[2]. This increase in temperature will increase the over-
all cooling cost and complicated packaging techniques.
The total power consumption in high perfor-
mance digital circuits is mainly due to leakage currents.
Leakage power makes up to 40% of the total power
consumption in today’s high performance monitoring
circuits. Hence, leakage power reduction is very neces-
sary for a low power design. The leakage power dis-
sipation is given by (1).
Pstatic = I leak * Vdd (1)
Where Ileak is the leakage current when the tran-
sistor OFF and Vdd is the supply voltage. The leakage
current consists of following components
(i) Gate leakage
(ii) Sub threshold leakage
(iii) Reverse biased junction leakage
(iv) Gate induced drain leakage.
ABSTRACT1
The paper presents a performance analysis of Novel CMOS Integrated Pseudo NMOS CC –ISFET
(PNCC-ISFET) having zero static power dissipation. The main focus is on simulation of power and per-
formance analysis along with the comparison with existing devices, which are used for water quality
monitoring. This approach can improve calibration of device to a fairly wide range without the use of a
high speed digital processor. The conventional devices generally used, consume high power and are not
stable for long term monitoring. The conventional devices have a drawback of low value of slew rate, high
power consumption, and non linear characteristics. In the proposed design(PNCC-ISFET) due to zero
static power, low value of load capacitance on input signals, faster switching, use of fewer transistors and
higher circuit density the device exhibits a better slew rate, piece-wise linear characteristic, and is seen
consuming low power of the order of 30mW. The functionality of the circuit is tested using Tanner simula-
tor version 15 for a 70nm CMOS process model. The proposed circuit reduces total power consumption
per cycle, increases speed of operation, is fairly linear and simple to implement. This device has a simple
architecture, and hence is very suitable for water quality monitoring applications.
Index Terms: Calibration; Simulation; Monitoring; Ion Sensitive Field Effect Transistor; Simulation;
Frequency compensation and Low power
Pawan Whig 1 and Syed Naseem Ahmad 2
1 Research Scholar, Department of Electronics and Communication Engineering, Jamia Millia Islamia, New Delhi-110025 India
2 Professor, Department of Electronics and Communication Engineering, Jamia Millia Islamia, New Delhi-110025 India
98 Journal of Integrated Circuits and Systems 2013; v.8 / n.2:98-103

A Novel Pseudo NMOS Integrated CC -ISFET Device for Water Quality Monitoring
Whig & Ahmad

99Journal of Integrated Circuits and Systems 2013; v.8 / n.2:98-103
The threshold voltage is only different in case of
MOSFET. In ISFET, defining the metal connection of
the reference electrode as a remote gate, the threshold
voltage is given by:
Where ERef is potential of reference electrode, ∆ф1j
is the potential drop between the reference electrode and
the solution, which typically has a value of 3mV [4].
Ψeol is the potential which is pH-independent; it can be
viewed as a common-mode input signal for an ISFET
interface circuit in any pH buffer solution and can be
nullified during system calibration and measurement
procedures with a typical value of 50 mV [5]. χsol is the
surface dipole potential of the solvent being independent
of pH., the terms in the parentheses are almost same
as that of MOSFET threshold voltage except the gate
metal function ф£. The other terms in above equation
are a group of chemical potential, among which the only
chemical input parameter shown has to be a function of
solution pH value. This chemical dependent character-
istic has already been explained by the Hal and Eijkel’s
theory which is elaborated using the generally accepted
site binding model and the Gouy-Chapman-Stern model.
Conventional water quality monitoring devices are made
up of voltage mode circuits (VMC) based on op-amps
and OTA’s(operational trans conductance amplifier).
These applications suffer from low band widths (BW’s)
arising due to stray and circuit capacitances. Also the need
for low voltage, low power circuits make these devices
not suitable for water quality monitoring. [6]. However,
with the advancement in VLSI devices new analog cur-
rent mode devices are developed which are very useful in
the water quality monitoring application These circuits
have a significant advantage of low power, low voltages
and can operate over wide dynamic range. These circuits
have large bandwidths, greater linearity and simple cir-
cuitry which consume low power. Current feedback op-
amps (CFOAs), operational floating conveyors (OFCs)
and current conveyors (CCs) etc. are popular CMC con-
figurations and the most widely used device among them
is second generation current conveyor CC-II. Hence,
Pseudo NMOS based CC-II is designed to perform as
the heart of water quality monitoring device.
III. CURRENT CONVEYOR
Current Conveyor (CC-II) has proved to be
a versatile analog building block that can be used to
implement numerous analog processing applications;
Out of these, sub-threshold leakage and gate-
leakage currents are dominant. The sub threshold leak-
age current of a MOS device is given by (2) and (3).
Isub=I0 exp [(Vgs-Vt) /(n VT)]
[1- exp (-Vds/VT)] (2)
I0=meff Cox (W/L) VT2 (3)
Where W and L are width and length of the
channel respectively, Vt is the threshold voltage, meff is
the electron/hole mobility, Cox is the gate oxide capaci-
tance per unit area, n is the sub-threshold swing coeffi-
cient, VT is the thermal voltage, Vgs is the transistor gate
to source voltage and Vds is the drain to source voltage.
II. ISFET
An ISFET is an ion sensitive field effect transistor
which has a property of measuring ion concentrations
in solutions. When the ion concentration (such as H+)
changes, the current through the transistor will change
accordingly. Here, the solution is used as the gate elec-
trode. A voltage between substrate and oxide surface
arises due to ion’s sheath. The ISFET has the similar
structure as that of the MOSFET except that the poly
gate of MOSFET is removed from the silicon surface
and is replaced with a reference electrode inserted inside
the solution, which is directly in contact with the hydro-
gen ion (H+) sensitive gate electrode [3] The Sub cir-
cuit block of ISFET macro model is shown in Figure 1.
Figure 1: Sub circuit block of ISFET macro model.
At the interface between gate insulator and the
solution, there is an electric potential difference that
depends on the concentration of H+ ion of the so-
lution, or otherwise pH value. The variation of this
potential caused by the pH variation will lead to mod-
ulation of the drain current. As a result, the Id - Vgs
transfer characteristic of the ISFET, working in triode
region is similar with that of MOSFET:
(4)
(5)

A Novel Pseudo NMOS Integrated CC -ISFET Device for Water Quality Monitoring
Whig & Ahmad
100 Journal of Integrated Circuits and Systems 2013; v.8 / n.2:98-103
it was introduced by Sedra and Smith [7]. The current
conveyor is a grounded three-port network represented
by the black box as shown in Figure 2. The general
Current Conveyor (CC) can be represented by the fol-
lowing input-output matrix relation:
=
When a = 1, the first generation current con-
veyor (commonly denoted CCI) is obtained. For a =
0, we obtain the second generation current conveyor
(commonly denoted CCII). For a = -1 we obtain the
third generation current conveyor (commonly denoted
CCIII). Usually, b = ±1. The sign of the parameter
b determines the conveyor current transfer polarity.
Positive b indicates that the CC has a positive cur-
rent transfer ratio and is denoted by CCI+, CCII+ or
CCIII+ while negative b means that it has a negative
current transfer ratio and is denoted by CCI-, CCII-or
CCIII-.
Figure 2: Block diagram of current conveyor
A well known basic building block is the second
generation current conveyor (CCII). Second genera-
tion current conveyors are widely used by analog de-
signers. An important attribute of current conveyor is
its ability to convey current between two terminals (X
and Z) at vastly different impedance levels.
IV. PSEUDO-NMOS LOGIC
Pseudo-NMOS logic is a ratioed logic which
uses a grounded PMOS load as a Pull up and an
NMOS driver circuit as pull-down network that realiz-
es the logic function. The main advantage of this logic
is that it uses only N+ 1 transistors as compared to
2N transistors for CMOS also, this logic have less load
capacitance on input signals, faster switching, higher
circuit density. In Pseudo NMOS logic the high output
voltage level for any gate is Vdd and the low output
voltage level is not 0 volt [8]. The only one main draw-
back of this logic is very high static power consumption
as there exists a direct path between Vdd and ground
through the PMOS transistor. In order to make low
output voltage as small as possible, the PMOS device
should be sized much smaller than the NMOS pull-
down devices. But to increase the speed particularly
when driving many other gates the PMOS transistor
size has to be made larger. Therefore there is always a
trade-off between the parameters such as noise margin,
static power dissipation and propagation delay.
Various methods used for decreasing static pow-
er in Pseudo NMOS logic are reverse body bias (RBB)
and transistor stacking.
A. Reverse body bias
This is an effective approach to reduce leakage
power. In this method, when the circuit enters the
standby mode, reverse body bias is applied to increase
the threshold voltage VT of the transistors and this de-
creases the sub-threshold leakage current. VT is related
to the reverse bias voltage between the source and body
Vsb by the following Eq. (6).
Where VTo is the zero bias VT for Vsb = 0 volt,
ff is a physical parameter and g is a fabrication pro-
cess parameter. Modification of VT can be achieved by
changing |Vsb|. This method can be either applied at
the full chip level or at a finer granularity. The advan-
tage of this method is that it can be implemented with-
out incurring any delay penalty. The key issue is that the
range of threshold adjustment is limited, which in turn
limits the amount of leakage reduction.
B. Transistor stacking method
Transistor stack is a leakage reduction technique
that works both in active and stand bye mode. It is
based on the observation that two OFF state transis-
tors connected in series cause significantly less leak-
age than a single device. This effect is known as the
“Stacking Effect”. When two or more transistors that
are switched OFF are stacked on top of each other, then
they dissipate less leakage power than a single transis-
tor that is turned OFF. This is because each transistor
in the stack induces a slight reverse bias between the
gate and source of the transistor right below it, and this
increases the threshold voltage of the bottom transistor
making it more resistant to leakage.
V. DEVICE DESCRIPTION AND ANALYSIS
For the integrated sensor, the measurement cir-
cuit tracks the threshold voltage (or the flat-band volt-
age) of the ISFET as the electrolyte pH is varied. A
practical solution to integrate the sensor with electron-
(6)

A Novel Pseudo NMOS Integrated CC -ISFET Device for Water Quality Monitoring
Whig & Ahmad
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101Journal of Integrated Circuits and Systems 2013; v.8 / n.2:98-103
ics is to view the ISFET sensor as a circuit component
in an integrated circuit rather than as an add on sensor
whose output signal is further processed. In this paper,
the ISFET is used as one of the input transistors in the
differential stage of the current conveyor as shown in
Figure 3. The circuit functions as follows: when the
ISFET-Current Conveyor is configured as a voltage
follower, the output voltage (Vo) is equal to the input
voltage (Vin); any difference in threshold voltages and
bias currents between the two input transistors at the
differential input stage will also appear at the output.
The distinct advantages of Pseudo NMOS is less load
capacitance on input signals, faster switching due to
fewer transistors, higher circuit density which motivate
us to implement this novel design. The only disadvan-
tage of Pseudo NMOS logic is that pull up is always
ON due to which there is significant static power dis-
sipation. There are several methods already discussed
above to reduce the static power dissipation but there is
no method which completely avoids this drawback. In
this novel design the circuit has zero static power dissi-
pation. The given circuit is designed in Pseudo NMOS
technology in which gate of PMOS is grounded. There
is one NMOS just above the grounded PMOS which
acts as a switch and ON only when input is applied,
otherwise OFF. Since the circuit is only ON when the
input signal is applied hence there is no direct path
from Vdd to ground which prevent the circuit from the
static power dissipation.
Figure 3: Circuit diagram of Pseudo NMOS CC-ISFET.
A. Transient analysis
Transient analysis of the PNCC-ISFET is ob-
served on Tanner tool Version 15 and it is found that
the output is fairly linear with respect to input with the
passage of time as shown in Figure 4 below.
Figure 4: Transient analysis of PNCC-ISFET.
B. Mathematical Regression Analysis
The Regression statistics including multiple R,
R square Adjusted R square and Standard error ob-
tained during experiment is shown in Table 1.
Table1. Regression Statistics
Regression Statistics
Multiple R 0.998428255
R Square 0.99685898
Adjusted R Square 0.996662667
Standard Error 0.08121496
Observations 18
On plotting a linear trend line between Vy and
Vz the coefficient of determination R2 is found to be
99.7% with standard error of 0.081 shown in Figure 5.
The coefficient of determination R 2 is useful because it
gives the proportion of the variance (fluctuation) of one
variable that is predictable from the other variable. It
is a measure that allows us to determine how certain
one can be in making predictions from a certain model.
The coefficient of determination is a measure of how
well the regression line represents the data. If the re-
gression line passes exactly through every point on the
scatter plot, it would be easy to explain all the variations.
Figure 5. Trend line between Vy and Vz obtained from SPICE model
readings with coeffi cient of determination R2

A Novel Pseudo NMOS Integrated CC -ISFET Device for Water Quality Monitoring
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102 Journal of Integrated Circuits and Systems 2013; v.8 / n.2:98-103
C. Residual plot
A residual plot between output and input shows
that for a regression model to be good fit when resi-
dues are random. There should be no recognizable
pattern. Good regression models give uncorrelated re-
siduals. The residual Plot for the device is plotted and
shown in given Figure 6.
Figure 6. Residual Plot of PNCC-ISFET
D. Normal Probability Plot
The normal probability plot is a special case of
the probability plot. The points on this plot form a
nearly linear pattern, which indicates that the normal
distribution is a good model for this data set. The nor-
mal Probability plot for the device is plotted and shown
in Figure 7.
Figure 7. Normal Probability Plot of PNCC-ISFET
VI. RESULT ANALYSIS
The various results obtained are summarized in
this section. Figure 8 and 9 shows component count
and the power consumption comparisons.
Figure 8. Component Comparison Chart
Figure 9. Power Comparison Chart
Table 2. Comparative analysis with existing devices
Parameters
Op- Amp –
ISFET [9]
CC-ISFET
[10] PPCC-ISFET
Technology CMOS CMOS Pseudo PMOS
Power supply 5V-0V 5V-0V 5V-0V
No. of Mosfets 27 16 9
Capacitor 2 2 1
Current Source 4 3 0
NMOS 17 10 8
PMOS 10 6 1
Resistor 5 5 0
Voltage Source 4 2 1
Max power (W) 3.63e-002 3.57e-002 3.00e-002
Min power (W) 2.13e-005 0.13e-005 0.00e+000
Stability analysis Closed loop
Stable
Closed loop
Stable
Closed loop
Stable
On comparing new design with the existing de-
signs as shown in Table 2 we arrive at the following results:
a) Number of MOSFET’s used are 27 in [9] and 16
in [10] for the conventional devices where as only
9 transistors are used in new proposed device. The
new proposed device deploys only 17% of compo-
nents as compared to 52% in [9] and 31% in [10].
b) The new proposed device consumes almost zero
static power.
c) No capacitor and resistor is used in the new tech-
nique.

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d) Number of current sources deployed is zero in the
new proposed device.
e) Number of n-MOS and p-MOS transistors required
for simulation of this device are 8 and 1 only.
f) Voltage sources required for proper operation of
the de-vices mentioned in table 3 are 4 in [9] and
2 in [10] for con-ventional devices and 1 in new
device.
As we know, volumetric efficiency measures
the performance of function per unit volume. In this
age of electronics, this is desirable since advanced de-
signs need to cram increasing functionality into smaller
packages. The concept of volumetric efficiency appears
in the design and application of capacitors, where the
“CV product” is a figure of merit calculated by mul-
tiplying the capacitance (C) by the maximum voltage
rating (V) divided by the volume. From this table, we
can figure out that there is significant saving in terms
of components. Hence, we come to a conclusion that
the circuit proposed here, meets all our requirements
in terms of component saving, miniaturization and
power efficiency.
VII. CONCLUSION
In this novel design, a new device employing
PNCC-ISFET is proposed. PNCC introduced a con-
venient building block that provides a simplified ap-
proach to the design of linear analog systems. It also
consumes considerably low power. There is significant
improvement in the slew rate. The output observed
is highly linear as it is evident from Figure 4. A sig-
nificant advantage of the proposed design is it’s simple
architecture, and low component count. Therefore it
is very suitable for water quality monitoring applica-
tions. This study may be extended for further improve-
ments in terms of power and size, besides the wiring
and layout characteristics level.
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