ArticlePDF Available

Dynamic Power Dissipation Analysis in CMOS VLSI Circuit Design with Scaling Down in Technology

Authors:
Manish Kumar
Manish Kumar
Manish Kumar
  • This person is not on ResearchGate, or hasn't claimed this research yet.
Download full-text PDF
Read full-text
Download citation

Abstract and Figures

In this paper, dynamic power dissipation in CMOS VLSI circuit is analyzed with scaling down in technology. Dynamic power dissipation of a CMOS full adder circuit is observed in different technologies (1.200µm, 0.800µm, 0.600µm, 0.250µm, and 0.120µm). This power dissipation reduces with the scaling down in technology and reduction in the supply voltage. Microwind ver. 3.1 EDA tool is used for the layout design and simulation of the CMOS full adder circuit.
Content may be subject to copyright.
Content uploaded by Manish Kumar
Author content
All content in this area was uploaded by Manish Kumar on Oct 19, 2020
Content may be subject to copyright.
55
J. of Active and Passive Electronic Devices, Vol. 12, pp. 55–61
Reprints available directly from the publisher
Photocopying permitted by license only
©2017 Old City Publishing, Inc.
Published by license under the OCP Science imprint,
a member of the Old City Publishing Group
Dynamic Power Dissipation Analysis in CMOS
VLSI Circuit Design with Scaling Down in
Technology
Manish KuMar
Department of Electronics & Communication Engineering, Madan Mohan Malaviya University of
Technology, Gorakhpur, Uttar Pradesh, India;
E-mail: er.manish.k@gmail.com
In this paper, dynamic power dissipation in CMOS VLSI circuit is ana-
lyzed with scaling down in technology. Dynamic power dissipation of a
CMOS full adder circuit is observed in different technologies (1.200µm,
0.800µm, 0.600µm, 0.250µm, and 0.120µm). This power dissipation
reduces with the scaling down in technology and reduction in the supply
voltage. Microwind ver. 3.1 EDA tool is used for the layout design and
simulation of the CMOS full adder circuit.
Keywords: Dynamic power dissipation, CMOS full adder, Scaling down,
technology.
1. INTRODUCTION
With the increase in demand of portable electronic systems that are driven by
portable batteries, reducing power dissipation has emerged as the major con-
cern among VLSI circuit designers and researchers [1-3]. Power and energy
efficient design has become a necessity in modern VLSI design. Nowadays
power dissipation has emerged as the most important issue in VLSI design
[4-6]. Earlier the main concern in VLSI circuit design was to deliver the max-
imum possible performance in terms of speed, while neglecting area and
power dissipation. However, in present scenario low power VLSI circuit
design has emerged due to the tremendous growth in demand of portable bat-
tery operated systems and technological limitations of high performance
56 Manish KuMar
devices. High speed and high density VLSI chips have experienced an alarm-
ing rise in chip temperature. VLSI chip temperature has reached to such a
high level that requires expensive packaging and cooling techniques for
reducing the chip temperature [7-9]. Serious reliability issues in VLSI chips
arise at such high temperatures.
Figure 1 shows the power density trend versus power design requirements
for modern VLSI chips [10]. Figure 2 shows an increase in power density of
Intel processors with the advancement in technology generation, year after year
[11]. Limited amounts of energy stored in battery of portable electronic sys-
FIGURE 1
Power density trend versus power design requirements for modern VLSI chips
FIGURE 2
Power density trends of Intel processors
DynaMic Power DissiPation analysis in cMos 57
tems require extensive power management techniques to increase the battery
life time. The energy density in emerging and new battery technologies is still
low. Therefore reducing the power dissipation by using low power VLSI circuit
design has emerged in present scenario [12-15]. Low power VLSI chips con-
sume less power from the battery and hence increases the lifetime of portable
batteries.
In this paper, layout of a CMOS full adder circuit is designed and simu-
lated in different technologies. Dynamic power dissipation of the adder cir-
cuit is observed by scaling down in technology.
2. DYNAMIC POWER DISSIPATION IN VLSI CIRCUITS
Dynamic power dissipation occurs in VLSI circuits during charging and dis-
charging of capacitances in the circuit [16]. Figure 3 shows the dynamic
power dissipation in a CMOS inverter circuit. The total capacitive load (Cload)
at the output of the inverter circuit consists of drain diffusion capacitance,
interconnect capacitance, and input gate oxide capacitance of the driven gates
that are connected to the output of the inverter circuit. During the switching
event, the output node voltage makes a full transition from 0V to VDD, and
one-half of the energy drawn from the power supply (VDD) is dissipated as
heat in the conducting pMOS transistor. Energy stored in the output node
capacitance during charging is dissipated as heat in the conducting nMOS
transistor, when the output voltage switches from VDD to 0V.
Dynamic power dissipation in VLSI circuits can be expressed as [16]
PaCV
DD f
dynamic Tload clk
=2 (1)
FIGURE 3
Dynamic power dissipation in a CMOS inverter circuit
58 Manish KuMar
Here aT is the switching activity factor, Cload represents the total load
capacitance,VDDis the supply voltage, and fclk represents the switching frequency.
Equation (1) indicates that the supply voltage is the dominant factor in
reducing the dynamic power dissipation.
3. SIMULATION RESULTS AND OBSERVATIONS
Layout of a CMOS full adder circuit is designed and simulated in different
technologies (1.200µm, 0.800µm, 0.600µm, 0.250µm, and 0.120µm).
Microwind ver. 3.1 EDA tool is used for the layout desigh and simulation of
the full adder circuit. Figure 4 shows the layout of a CMOS full adder circuit.
Figure 5 shows the three inputs A, B and C of the full adder circuit and Figure
6 shows the simulation results for sum and carry out. Table 1 and Figure 7
FIGURE 4
Layout of a CMOS full adder circuit
FIGURE 5
Inputs A, B and C of a CMOS Full adder circuit
DynaMic Power DissiPation analysis in cMos 59
FIGURE 7
Dynamic power dissipation of a CMOS full adder circuit with scaling down in technology
FIGURE 6
Sum and Carry out of a CMOS Full adder circuit
TABLE 1
Dynamic power dissipation of a CMOS full adder circuit with scaling down in technology
Sl.No. Technologies
Supply
voltage (VDD)
No. of pMOS
transistors
No. on nMOS
transistors
Dynamic
power
dissipation
1 1.200 µm 5.00 V 12 12 2.075 mW
2 0.800 µm 5.00 V 12 12 1.694 mW
3 0.600 µm 5.00 V 12 12 1.281 mW
4 0.250 µm 2.50 V 12 12 0.136 mW
5 0.120 µm 1.20 V 12 12 0.008 mW
60 Manish KuMar
show the dynamic power dissipation of the CMOS full adder circuit in differ-
ent technologies.
It is observed from Table 1 and Figure 7 that the dynamic power dissipa-
tion of the full adder circuit reduces with the scaling down in technology. It is
also observed that the dynamic power dissipation reduces with the decrease
in the supply voltage (VDD) also.
4. CONCLUSION
Dynamic power dissipation trends of a CMOS full adder circuit is analyzed
by scaling down in technology. Dynamic power dissipation reduces with the
scaling down in technology and reduction in the supply voltage. Supply volt-
age scaling is also considered as the effective method in reducing dynamic
power dissipation in VLSI circuits.
REFERENCES:
[1] Chandrakasan, A., Sheng, S., and Brodersen, R., “Low-Power CMOS Digital Design,”
IEEE Journal of Solid-State Circuits, vol. 27, pp. 473-484, 1992.
[2] Kumar, M., Hussain, M. A., and Singh, L. L. K., “Power Dissipation and Switching Speed
Analysis of a CMOS Full adder in Deep Submicron and Nanoscale Technologies”, Jour-
nal on Electronics Engineering, vol.1, no.1, pp.21-25, 2010.
[3] Bursky, D., “Power reduction schemes promise cool digital ICs” Electronic Design, vol.
43, pp. 51-65, 1995.
[4] Bellaouar, A., and Elmasry, M. I., “Low-power digital VLSI design circuits and systems”,
Kluwer Academics Publishers, Norwell, 1995.
[5] Kumar, M., Hussain, M. A., and Paul, S. K., “Performance of a Two Input NAND Gate
Using Subthreshold Leakage Control Techniques”, Journal of Electron Devices,vol.14,
pp. 1161-1169, 2012.
[6] Kumar, M., Hussain, M. A., and Paul, S. K., “New Improved Hybrid Digital Circuit
Design Techniques for Reducing Subthreshold Leakage Power in Standby Mode”, Cir-
cuits and Systems, vol.4, No. 1, pp. 75-82, 2013.
[7] Chandrakasan, A., and Brodersen, R., “Minimizing Power Consumption in Digital CMOS
Circuits,” Proceedings of IEEE, vol. 83, no. 4, pp. 498-523, 1995.
[8] Liu, D., and Svensson, C., “Trading Speed for Low Power by Choice of Supply and
Threshold Voltages,” IEEE Journal of Solid-State Circuits, vol. 28, no. 1, pp.10-17, 1993.
[9] Kumar, M., Hussain, M. A., and Singh, L. L. K., “Design of a Low Power High Speed
ALU in 45nm Technology Using GDI technique and its Performance Comparison”, Com-
munications in Computer and Information Science, vol.142, pp. 458-463, 2011.
[10] Sarkar, A., “An RTL to GDSII approach for low power design: A design for power meth-
odology,” EE Times, 2011.
[11] Borkar, S., “Design challenges of technology scaling”, IEEE Micro, vol. 19, pp. 23-29,
2002.
[12] Charles, H. S., “Shrinking devices put the squeeze on system packaging”, EDN, vol. 39,
pp. 41-46, 1994.
[13] Kumar, M., “Realization of a Low Power High Performance IC Design Technique for
Wireless Portable Communication Devices used in Underground Mines”, IP Multimedia
DynaMic Power DissiPation analysis in cMos 61
Communications in special issue of International Journal of Computer Applications, pp.
52-54, 2011.
[14] Kunie, S., Hiraga, T., Tokue, T., Torii, S., and Ohsawa, T., “Low power architecture and
design techniques for mobile handset LSI Medity™ M2”, IEEE Asia and South Pacific
Design Automation Conference, Seoul, 748-753, 2008.
[15] Sharma, P. K., and Kumar, M., “Implementation of BDDs by various techniques in Low
power VLSI design”, International Journal on Recent Trends in Engineering & Technol-
ogy, vol.10, No.2, pp. 221-228, 2014.
[16] Kang, S. M., and Leblebici, Y., “CMOS Digital Integrated Circuits-Analysis and Design”,
Tata McGraw Hill, New Delhi, 2003.
... The switching power consumption occurs as a result of the charging and discharging of the load capacitance, which is connected to the circuit. It is mathematically expressed as [63][64][65][66][67]: ...
Processor Power and Energy Consumption Estimation Techniques in IoT Applications: A Review
Article
  • Dec 2022
The energy efficiency of IoT nodes remains the dominant factor for effective IoT solutions that will meet the challenges of the 21st century, especially in the drive towards a carbon-neutral world through net-zero targets. Microprocessors/microcontrollers are devices that perform entire operations of IoT devices. Therefore, the power and energy consumption of these processors directly reflects the power consumed by the IoT devices they drive. An accurate estimation of the power and energy consumption of the processors is vital for the development of energy-efficient IoT solutions because IoT devices are designed to operate in remote locations for long periods without human intervention. It is against this backdrop that this paper which is expected to serve as a guide for researches and IoT node/application developers in selecting the best technique for an IoT use-case, presents a review of processor power and energy consumption estimation techniques starting from the lowest level of abstraction to the highest level of abstraction. The review involves a detailed discussion of estimation technique methodologies for an abstraction level, and where applicable, generalized methodologies which cover the most approach used for an abstraction level are covered. The existence of overlaps and the impact of processor duty cycles on the techniques were discussed. A comparison of the strengths and weaknesses of each technique was made, from where register-transfer level and instruction level techniques are shown to be resilient against errors that occur from poor input signal conditioning. Future directions for the development of estimation techniques are also presented as recommendation.
View
View
Read Improved and Low Leakage Power CNTFET Based Hybrid 10t SRAM Cell for Low Power Applications
Article
Full-text available
  • Oct 2023
  • CIRC SYST SIGNAL PR
Static random access memory (SRAM) cell design has undergone extensive development to achieve good performance and low power consumption. This paper introduces an SRAM cell with ten carbon nanotube field effect transistors (CNTFETs) named 10 T CNTFET SRAM cell to help with that and to address the drawback of most SRAM cells caused by their poor stability during read operation. The Schmitt-trigger (ST)-based inverter and PPN-inverter are coupled back to back to create the novel SRAM cell structure. Additionally, single-ended writing, feed-back cutting, and single-ended reading are used in this novel SRAM cell. The single-ended writing technique and feed-back cutting method are used to their full potential to increase the write static noise margin (WSNM) of this 10 T CNTFET SRAM cell. The single-ended read mode of this 10 T CNTFET SRAM cell increases the read static noise margin (RSNM) as the storage nodes are not disturbed. The hold power, read power, WSNM, hold static noise margin (HSNM), RSNM, read delay, leakage power, and VDDmin of this 10 T CNTFET SRAM cell are 0.5527 nW, 1.8087 nW, 432.4 mV, 360 mV, 360 mV, 5.0651 pS, 0.276 nW, and 32.1 mV, respectively. To understand the performance of this introduced SRAM cell and several existing SRAM cells are simulated and the parameters are compared. A comparative study shows that the introduced cell is more stable than the other cells while consuming less power during reading and holding. Furthermore, the new cell reads much faster and has less VDDmin than the other bit cells. This research also documents how SRAM cell performance changes when the CNTFET parameters change. Using the 32 nm CNTFET model from Stanford University using the Hewlett simulation program with integrated circuit emphasis (HSPICE) simulation tool, the simulation is carried out.
View
Embedded microfluidic cooling with compact double H type manifold microchannels for large-area high-power chips
Article
  • Nov 2022
  • INT J HEAT MASS TRAN
Driven by the demands of the intelligent industry, integrated circuit chip has witnessed development in the direction of use of increased number of transistors and larger area. Consequently, power dissipation is increasingly limiting chip performance. In this study, an embedded microfluidic cooling solution for a 20 mm×20 mm high-power chip was realized. The microchannels and the double H type manifold channels were etched on two silicon wafers, and thereafter assembled employing the silicon-silicon direct bonding process. The depth of all the channels was 250 μm, and the width of the microchannels and manifold channels were approximately 210 μm and 2 mm after careful numerical optimization, respectively. In addition, a compact channel layout was used to enable cooling of the entire area. Platinum serpentine resistors were prepared for heating and temperature sensing, respectively. The global temperature was measured under a heat dissipation power of 417 W, the average temperature rise was 22.2 K, and the coefficient of performance was 3200 when using deionized water as the working fluid at the volume flow rate and pump pressure of 612 ml/min and 35.0 kPa, respectively. The average temperature rise agreed with the simulation results within 1.6 K. Moreover, this study proposed a simplified thermal resistance network model to examine the fin effects of the silicon substrate in the microchannels. The relationships between the Nusselt number and the Reynolds number were calculated for further optimization of channels. The proposed compact double H type manifold microchannels was concluded to be a promising embedded microfluidic cooling approach for large area high power chips.
View
View
Design of a Low Power High Speed ALU in 45nm Using GDI Technique and Its Performance Comparison
Article
Full-text available
  • Jan 2011
The paper presents a low power high speed Arithmetic Logic Unit (ALU) in 45 nm technology using Gate Diffusion Input (GDI) technique and its performance comparison with CMOS and nMOS Pass Transistor Logic (PTL) techniques. The simulated results revealed better performance characteristics of various logic and arithematic functions of a 1-bit ALU using GDI technique as compared to conventional CMOS and nMOS PTL techniques. GDI technique allows reducing power dissipation and delay while maintaining low complexity of logic design. MICROWIND and DSCH 3.1 EDA tools were used for the schematic layout and simulation of ALU using BSIM4 model.
View
PERFORMANCE OF A TWO INPUT NAND GATE USING SUBTHRESHOLD LEAKAGE CONTROL TECHNIQUES
Article
Full-text available
  • Oct 2020
This paper presents performance comparison analysis of a two input NAND gate using conventional CMOS, stack, sleep and sleepy keeper techniques. Performance characteristics of a two input NAND gate were analysed in 45 nm technology using BSIM4 model. Sleepy Keeper technique dissipated lesser static power and lesser static power delay product (PDP static) in comparison with the other techniques. An improvement of 1.4 X and 1.3X were observed in static power dissipation and static power delay product respectively by using the Sleepy keeper technique in comparison with the conventional CMOS technique. Sleepy keeper technique lowers the subthreshold leakage power dissipation while maintaining the logic state of the digital circuit.
View
Implementation of BDDs by Various Techniques in Low Power VLSI Design
Article
Full-text available
  • Oct 2020
Power has become an important design parameter in today's ultra low sub-micron digital designs as found. The impact of the increase in power is multi-discipline to researchers ranging from power supply design, power converters, voltage regulators design, system, board and package temperature analysis and signal integrity analysis to minimizing power itself. This survey basically focuses on steps taken till date in solving the challenges arising due to increase in power in CMOS digital circuit design using a very efficient pre-computation technique with the use of BDDs (Binary Decision Diagrams).
View
View
Realization of a Low Power High Performance IC Design Technique for Wireless Portable Communication Devices used in Underground Mines
Article
Full-text available
The demand for increasing speed and low power dissipation triggers numerous research efforts with the increasing demand of wireless portable communication systems in underground mines driven by batteries. Presence of highly flammable gases in underground mines prohibits the use of higher power dissipating electronic systems. Low power wireless portable communication devices can safeguard the life of miners in case of disaster. The demand for increased battery life of portable devices has forced researchers to seek out new integrated circuit techniques to reduce the power dissipation without comprise in performance of the portable electronic system. Power consumption by the electronic system determines the battery life of the device. As a result, tremendous effort has been devoted to achieve lower power dissipation without affecting performance of portable communication devices. Therefore, reduction of power dissipation without sacrifice in performance is vital for wireless portable communication devices for improving the safety standards and productivity in underground mines. Multi threshold circuit technique can be used to design a low power high performance integrated circuit for wireless portable communication devices used in underground mines.
View
View
Power-reduction schemes promise 'cool' digital ICs
Article
  • Jan 1995
A lower power-supply level provides the first and simplest option that system designers employ towards reducing chip power consumption. Many of today's VLSI chips were designed with 3.3-V operation in mind, and due to reductions in feature sizes, cannot withstand 5-V supplies. However, just microprocessors and memory chips operating at 3.3 V are not all that a present system needs. Over the next two years, however, components such as displays to the disk drives will fall into the 3.3-V category, paving the way for completely low-power systems. With such systems becoming manufacturable, system designers must face the resultant challenges such as reducing portable system weight and extending operating time. Advances in power management and supply-voltage scaling that promise cooler and faster CPUs and logic are described.
View
View
View
Low power architecture and design techniques for mobile handset LSI Medity
Conference Paper
  • Apr 2008
This paper presents the low power architecture and design techniques for the mobile handset LSI Medity™ M2. M2 is a second-generation mobile handset LSI which integrates a Digital baseband and Application processor on a chip. M2 is capable of supporting 3.2 Mbps HSDPA, WCDMA communications, and rich, high-resolution multimedia applications, while power consumption is kept almost the same as in its predecessor chip M1. To reduce power consumption, M2 adopts hardware management clock control schemes, Multiple Vt transistors, an On-chip Power Switch, and Back-bias control. Preliminary measurement results show the design to work very well.
View