Fabrication and reliability demonstration of 5μm redistribution layer using low-stress dielectric dry film

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Fabrication and reliability demonstration of 5μm
redistribution layer using low-stress dielectric dry film
Abstract- Low-stress and low-warpage dielectrics are gaining
importance as we move towards large-body Multi-chip Modules
(MCMs). This paper demonstrates fabrication of redistribution
layer (RDL) with 5 μm linewidth/spacing using a novel low-stress
dielectric dry film- PLSF (Panasonic low stress film) as a build-up
layer. Microvias formation down to 7 μm diameter has also been
demonstrated in this paper. The main feature of PLSF is its low-
stress and low-warpage. In this paper, we have studied residual
stress characteristics of PLSF and its comparison with the
industry-standard dielectric (ISD). The lower tensile modulus of
PLSF as compared to ISD results in significantly lower residual
stress and warpage on the substrate. Electrical and
thermomechanical reliability of RDL with PLSF as build-up layer
has also been studied and the results are presented in this paper.
Keywords- Low warpage, low-stress, large body, Multi-chip modules,
Redistribution layers
I.
INTRODUCTION
The current trend in electronic packaging for high
performance computing is focused toward large body Multi-
chip Modules (MCMs) with higher interconnection density.
One major factor limiting this transition to large packages is
warpage which has contributions from the substrate, die size,
RDL dielectric as well as symmetric or asymmetric architecture
of package. This has made warpage of the substrate a critical
issue to resolve to achieve larger package sizes. In current
generation 2.5D interposers consisting of multi-layer RDL,
polymer dielectrics have enabled us to achieve high electrical
performance owing to their low dielectric constant. However,
polymer dielectrics have a high coefficient of thermal
expansion (CTE) which leads to various challenges during RDL
fabrication. Panel-scale processes for packaging with high-
density RDL are very important for achieving low cost, large
body size fan-out packages and interposers. There are various
problems faced during fabrication of large body size packages
with high density RDL, and the most important one is the large
warpage of the substrate. The large warpage of the substrate in
turn leads to additional problems such as defocusing during
lithography, residual stresses resulting in mechanical reliability
issues, as well as problems during assembly. Therefore,
warpage is the main factor that needs to be addressed to achieve
larger body sizes required for High Performance Computing
(HPC) applications. Polymer dielectrics have been used as
build-up layers in 2.5D interposers with multilayer RDLs.
Because of the low dielectric constants of polymers, we have
been able to achieve high interconnection densities with good
electrical performance. However, one major limiting factor here
is the high CTE of polymers which causes the large warpage of
the substrate. Low-stress and low-warpage dielectrics are in
great need to achieve larger body MCMs with higher RDL
densities.
There have been numerous reports of demonstration of
fine line RDLs with copper trace widths down to 5 μm and
below [1-3]. Also, microvias with a diameter of 5 μm and below
have been demonstrated [4-7]. However, there are very few
reports on fine line RDL demonstration with low-stress, and
low-warpage dielectrics. Polyimides have been traditionally
used as dielectric material [8], but they induce very high
residual stress on substrates mainly because of its high curing
temperature and large curing shrinkage [9, 10]. Clearly,
polyimides are not suitable as build-up layers in RDL for large-
body sizes.
In this paper, we have evaluated a novel low-stress and
low-warpage dielectric dry film for potential applications in
large body MCMs. We have studied the residual stress and
warpage characteristics of this dielectric. We have also
demonstrated RDL and microvia fabrication using the PLSF
dielectric and presented preliminary results on the reliability
studies.
Pratik Nimbalkar
Packaging Research Center,
Georgia Tech,
Atlanta, GA, USA
pratiknimbalkar5@gatech.edu
Cheng Ping Lin
Panasonic Corp.,
Japan
lin.chengping@jp.panasonic.com
Naoki Watanabe
Panasonic Industrial Devices Sales Company of America,
USA
naoki.watanabe
@
us.
p
anasonic.com
Atsushi Kubo
TOK Co. Ltd.,
Japan
akubo6@gatech.edu
Fuhan Liu
Packaging Research Center,
Georgia Tech,
Atlanta, GA, USA
fuhan.liu@ece.gatech.edu
Atom Watanabe
Packaging Research Center,
Georgia Tech,
Atlanta, GA, USA
atom@gatech.edu
David Weyers
Packaging Research Center,
Georgia Tech,
Atlanta, GA, USA
dweyers3@gatech.edu
Mohanalingam Kathaperumal
Packaging Research Center,
Georgia Tech,
Atlanta, GA, USA
kmohan@ece.gatech.edu
Madhavan Swaminathan
Packaging Research Center,
Georgia Tech,
Atlanta, GA, USA
madhavan.swaminathan@ece.gatech.edu
Rao Tummala
Packaging Research Center,
Georgia Tech,
Atlanta, GA, USA
rao.tummala@ece.gatech.edu
Fukuya Naohito
Panasonic Corp.,
Japan
Toshiyuki Makita
Panasonic Corp.,
Japan
62
2020 IEEE 70th Electronic Components and Technology Conference (ECTC)
2377-5726/20/$31.00 ©2020 IEEE
DOI 10.1109/ECTC32862.2020.00023

II. LOW-STRESS DIELECTRIC DRY FILM
In order to minimize warpage, it is important to achieve a
good balance between the CTE and tensile modulus of polymer
dielectric. PLSF is a dielectric dry film with a very low tensile
modulus of 1.8 GPa as compared to the industry standard
dielectric (ISD) having a tensile modulus of 5 GPa. The low
tensile modulus of PLSF facilitates stress relaxation leading to
lower warpage of the substrate. A comparison of various
physical properties of both films is shown in Table 1. PLSF has
higher CTE than the industry standard film which arises
primarily due to the inverse relationship between the tensile
modulus and CTE. The dielectric constant (D
k
) of PLSF is 2.99
which is very low and thus crucial for achieving low
capacitance in fine line RDL.
Table 1: Comparison of PLSF vs ISD
III. RESIDUAL STRESS
The most important characteristic of PLSF is that it’s a
low-stress, low-warpage dielectric. Thus, we studied residual
stress characteristics of a dummy RDL with PLSF as a buildup
layer. The residual stress on the substrate was estimated by
measuring the bow of the wafer at various stages of fabrication
and calculated by using Stoney’s formula [9, 10]. Figure 1
shows the residual stress measured at various stages of
fabrication namely, lamination & curing of dielectric, plating
and annealing for a single layer of RDL. The schematic of RDL
stack up is shown in Figure 1. The convention followed for the
sign of stress values is also shown in Figure 1. Increasing
convex curvature is referred as positive and concave curvature
is referred as negative.
Figure 1. Residual stress at various stages of fabrication
We have compared the residual stress characteristics of
PLSF with ISD which has a higher tensile modulus. Figure 1
also shows the residual stress values for different thicknesses of
PLSF and ISD dielectrics as indicated in parenthesis. The stress
induced by PLSF after lamination and curing is lower than that
of ISD. This means that either PLSF has low curing shrinkage
or the stress is relieved due to its low tensile modulus. Thicker
dielectric showed better stress relaxation as seen in Figure 1.
Ti/Cu seed layer was sputtered on the dielectric and annealed
before plating. However, no change in the bow of the wafer and
residual was observed. This might be due to very low thickness
of the seed layer (Ti-50 nm, Cu-200 nm). Blank copper of 7 μm
thickness was electroplated on the sputtered samples which
then led to a drop in stress. Electroplated copper tends to self-
anneal which leads to slow and continuous increase in stress
[11-13]. Therefore, in order to stabilize the stress in RDL in a
short time, it is important to anneal after electroplating. After
annealing at 200
o
C for one hour, a significant increase in stress
was observed. The difference in stress values was observed to
be lowered after copper plating and annealing. The reason for
this might be that copper is more dominant over the polymer in
stress development because of its higher tensile modulus.
However, for a thicker dielectric, stress is always lower than a
thinner dielectric as can be seen from Figure 1. This means, the
ratio of copper thickness to dielectric thickness affects the stress
in RDL.
To study the effect of electroplated copper thickness on
residual stress, we plated PLSF (7) & ISD (10) samples in steps
and measured stress after every step. The plot and the schematic
of RDL stack are shown in Figure 2.
Figure 2. Effect of thickness of plated Cu on stress
As we go on increasing the thickness of copper, both PLSF
and ISD films exhibit a decrease in stress values. The drop in
stress is faster for ISD than PLSF, which means PLSF is more
pliable due to its lower tensile modulus and this relaxes the
stress induced by copper. At higher thickness of copper, it can
be clearly observed that the two lines nearly converge, which
means as we plate more copper, it becomes more dominant in
stress development due to its higher tensile modulus. In other
0
20
40
60
80
100
Stress (MPa)
ISD(15)
ISD(10)
PLSF(15)
PLSF(7)
Reference Curing Plating Annealing
0 2 4 6 8 10 12 14 16 18
10
15
20
25
30
Stress (MPa)
PLSF(7)
ISD(10)
Cu Thickness
(
μ
m
)
ISD PLSF
Tensile modulus
(GPa)
5 1.8
Tensile strength
(MPa)
98 21.4
T
g
(
o
C) 153 (TMA) 225 (TMA)
CTE (ppm/K) 39 (25-150
o
C) 63 (50-100
o
C)
120 (150-240
o
C) 106 (240-260
o
C)
Dk 3.2 (@5.8 GHz) 3 (@10 GHz)
Df 0.017 (@5.8 GHz) 0.02 (@10 GHz)
63

words, PLSF shows lower stress at low copper thickness. The
two lines corresponding to the stress values of the two
dielectrics in Figure 2 are not continuously dropping as there
are slight fluctuations. This is because of the tendency of
electroplated copper to self-anneal [11-13]. After every step of
plating, the copper self-anneals leading to a slightly higher
stress and variations.
IV. WARPAGE
Furthermore, we also studied the warpage behavior of
dummy RDL for both PLSF and ISD dielectrics using Shadow
Moiré technique. In this technique, the plated side of the wafer
was coated with a thin non-reflective coating before
measurement. Warpage was measured over a temperature range
of 25
o
C to 200
o
C. As the temperature increases, the warpage of
the substrate changes and the position of Moiré fringes changes.
From this, the vertical displacement at every point on the
substrate can be determined using an image analysis software
and thus, warpage can be determined. Figure 3a and 3b shows
the Shadow Moiré setup from Akrometrix and a representative
image of Moiré fringes respectively.
Figure 3. (a) Shadow Moiré setup & (b) Moiré fringes
Figure 4 & Figure 5 show the JEDEC full-field signed
warpage of dummy RDL over a range of temperature from 25
o
C
to 200
o
C. The arrows indicate the direction of data points
collected during heating and cooling. The sign convention used
for warpage is shown in Figure 4 which is opposite to that for
stress. The maximum warpage in the decreasing order is as
follows- ISD(10)>PLSF(7)>ISD(15)>PLSF(15) corresponding
to the values- 86, 76, 67 & 62μm respectively. There’s a sharp
transition from negative to positive warpage for both
dielectrics. However, a thicker dielectric shows a delayed
transition. PLSF(7) shows the transition between 40 to 50
o
C
whereas, PLSF(15) shows transition between 60 to 70
o
C during
heating. Also, PLSF shows a delayed transition during heating
when compared to ISD of comparable thickness. Transition at
higher temperature means the dielectric can handle larger
extension of the RDL stack. From this, we can infer that a
thicker and lower tensile modulus dielectric provides better
stress relaxation.
Figure 4. Warpage behavior of RDL dielectric PLSF(7) vs ISD(10)
Figure 5. Warpage behavior of RDL dielectric PLSF(15) vs ISD(15)
V. 5 μm L/S DEMONSTRATION
We have fabricated fine L/S RDL on PLSF using the
standard semi-additive process (SAP) route as shown in Figure
6. The dielectric film was laminated on a 4-inch silicon wafer.
Copper seed layer with 200 nm thickness was sputtered with
titanium (50 nm) as an interlayer between the dielectric and the
copper. A high-resolution photoresist (dry film PC) from TOK
(Tokyo Ohka Kogyo Co. Ltd.) was laminated on the copper
surface. An advanced projection stepper, UX-44101 from
20 40 60 80 100 120 140 160 180 200 220
-80
-60
-40
-20
0
20
40
60
80
100
Warpage (μm)
Temperature (
o
C)
PLSF(7)
ISD(10)
↑
↑
↑
↑
20 40 60 80 100 120 140 160 180 200 220
-80
-60
-40
-20
0
20
40
60
80
100
Warpage (μm)
Temperature (
o
C)
PLSF(15)
ISD(15)
↑
↑
↑
↑
(a)
(b)
64

Ushio Inc., was used for photolithography. This tool uses a high
power i-line (λ = 365 nm) light source and has 2 μm resolution
in a 100 mm diameter or 70 mm × 70 mm large-panel exposure
area. After development in 2.38% TMAH solution,
electroplating was done at a current density of 1A/dm
2
to plate
5 μm of copper. After stripping of the photoresist, copper seed
layer was etched off by using a differential seed etcher and the
titanium seed was etched off by reactive ion etching (RIE) using
CHF
3
plasma. Using this process flow, we were able to
demonstrate down to 5 μm L/S as shown in the optical image in
Figure 7.
Figure 6. Process flow of fine line RDL fabrication
Figure 7. Optical image of 5/5 µm L/S fabricated on PLSF
VI. MICROVIAS FABIRCATION
Microvia formation was demonstrated on PLSF using a
picosecond pulsed UV laser, Corner Stone, developed by
Electro Science Industries (ESI). The tool is equipped with a
coherent solid-state laser that generates picosecond pulses at 80
MHz repetition rate with an output power of 16 W. The
wavelength of the UV laser used is 355 nm, with a pulse width
of 5 ps. An organic laminate with a smooth surface profile and
a thin copper foil was employed as the core substrate. The
dielectric film was laminated on top of this substrate. A matrix
was designed for the pulse punch test. The pulse power was
varied from 0.1 to 1 W with an increment of 0.1 W and with
punch numbers ranging from 1 to 10. Experiments showed that
the minimum power required for via opening was 0.2 W with
respect to 1 punch and 0.1 W with respect to 2 punches. Bottom
up plating process was used to plate copper into the vias. Figure
8 shows the optical image of the small microvias in the PLSF
by pulse punch method after bottom-up copper plating. The
minimum diameter of via was 7 μm.
Figure 8. Demonstration of 7 µm diameter microvia on PLSF
VII. RELIABILITY STUDIES
A. Adhesion of Cu with PLSF
In addition to the warpage and stress measurements, we
have also measured the adhesion strength of electroplated
copper with PLSF by 90-degree peel test. For this test, PLSF
was sputtered with a seed layer and electroplated to get 25 μm
copper followed by annealing at 200
o
C for one hour. To study
the effect of Highly Accelerated Stress Test (HAST) on
adhesion strength, the PLSF film was subjected to HAST and
its adhesion strength was measured. The adhesion strength
before HAST was 11.3 N/cm and after HAST it reduced to 7.9
N/cm. The reduction in adhesion strength is attributed to the
absorption of moisture during HAST and thus leading to a
weakening of polymer bonds leading to a cohesive failure as
opposed to adhesive failure in the original sample.
B. Test vehicle fabrication
For biased HAST (bHAST) test, comb structures with
various lines and spacings were fabricated using a standard SAP
route as shown in the flowchart in Figure 5. For thermal cycling
reliability test, a daisy chain structure was fabricated. The
65

process flow for the fabrication of daisy chain structure is
shown in the Figure 9.
C. Biased HAST
B HAST test was performed on the comb structures to
measure leakage current characteristics of the PLSF under and
applied voltage and environmental conditions. The conditions
used for bHAST as per JESD22-A110E standard were as
follows: temperature: 135
o
C, relative humidity: 85% and
duration: 96 hours. The failure criteria as per the JEDEC
standard is a measured resistance of 1 MΩ. The RDL L/S was
considered failed if the resistance dropped below 1 MΩ. The
applied voltage (bias used during the test) was 5V. The comb
structures with minimum L/S 10 μm/5 μm passed the test as the
resistance after b-HAST was 3 MΩ, which is above the JEDEC
criteria.
Figure 9. Process flow for TCT test vehicle fabrication
D. Thermal Cycling Test
Thermal cycling test (TCT) for thermomechanical
reliability is currently in progress. The daisy chain structures
fabricated by SAP route (Figure 9) will be subjected to TCT
after MSL-3 pre-conditioning. Figure 10 shows the design of
daisy chain structure used for TCT reliability. The air-to-air
thermal cycling conditions as per JESD22-A104E standard
include a hold time of 15 mins at -55
o
C, ramp up to 125
o
C in 15
mins and a hold time of 15 mins at 125
o
C. The samples will be
exposed to 1000 such thermal cycles. The results will be
reported during the presentation in May at ECTC 2020.
Figure 10. Design of daisy chain structure for TCT reliability
VIII. SUMMARY AND CONCLUSION
In summary, we have demonstrated fine L/S fabrication on
PLSF down to 5/5 μm and microvia formation down to 7 μm.
PLSF shows good adhesion to plated copper before and after
HAST. Also, PLSF showed good resistance to electromigration
under biased-HAST conditions. This makes PLSF a reliable
dielectric for fine line RDL. We studied the residual stress and
warpage characteristics of PLSF and compared it to the industry
standard dielectric (ISD). PLSF shows lower stress and
warpage as compared ISD of comparable thickness. At low
copper thicknesses, the stress in RDL is significantly lower with
PLSF as a build-up layer. This characteristic is critical for a
low-stress, fine line RDL with high mechanical reliability. This
makes PLSF a good candidate for potential applications in
large-body MCMs with high density interconnects.
IX. ACKNOWLEDGEMENT
This work was supported by the Industry Consortium at the
Georgia Tech Packaging Research Center (PRC).
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