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Design and Development of a 32-bit ALU
G.M.K.B. Karunasena
Faculty of Engineering Technology
The Open University of Sri Lanka
gmkar@ou.ac.lk
1. Introduction
The goal of this article is to show the basics of building complex circuit from simple AND, OR,
NOT and XOR logical gates. This article will show you how to build an Arithmetic Logic Unit
(ALU) from scratch, using these simple logic gates and other components. The ALU will take in
two 32-bit values, and two control lines. Depending on the value of the control lines, the output
will be the addition, subtraction, bitwise AND or bitwise OR of the inputs. The Fig. 1 shows the
block diagram of 32-bit ALU. The ALU design and develop by using Logisim software.
Figure 1. 32-bit ALU
Basic components required for 32-bit ALU
AND Gate
OR Gate
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XOR Gate
NOT Gate
Multiplexor
32-bit wide two-way multiplexor
2. Bitwise 32-bit AND
Building the logic to do 32-bit AND on two inputs by using 32 AND gates in parallel, each bit is
independent as shown in Fig. 2
Figure 2. 32-bit AND
The interface diagram on the left, include all the 32 AND gates as shown in right side.
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3. Bitwise 32-bit OR
Building the logic to do 32-bit OR on two inputs by using 32 OR gates in parallel, each bit is
independent as shown in Fig. 3
Figure 3. 32-bit OR
The interface diagram on the left, include all the 32 AND gates as shown in right side.
4. 32-bit Addition
For the development of 32-bit Addition, we need to use 32 full adder circuits for each single bits.
This component, which will perform a 1-bit ADD, receiving a carry in and producing a 1-bit output
and a carry out. The interface block and circuit diagram of Full Adder is shown in Fig. 4.
Figure 4. Full Adder interface block and circuit diagram
To make a 32-bit full adder, we simply have to string 32 of these 1-bit full adders together as
shown in Fig. 5
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Figure 4. 32-bit Full Adder Circuit
For the most significant bit, if the carry is a 1, then we ran out of bits to store the result.
When the final carry output is 1, this indicates that the result was too big to fit into 32 bits.
5. 32-bit Subtraction
For the subtract operation we are going to negate one of the inputs and we could use the existing
32-bit full adder, to negate a twos complement binary integer: invert every bit in the number, then
add 1.
We can make above equation by set the initial carry-in to 1 instead of 0, thus adding an extra 1 to
the sum by using XOR gates as shown in Fig.5
If we are doing addition (Control=0), then one arm of the XOR gates is zero, and the B bits go into
the adders unchanged, and the carry-in is zero.
If we are doing subtraction (Control=1), then one arm of the XOR gates is one. This inverts all of
the B bits before they get to the adders. As well, the carry-in is now 1, so we achieve the result of
doing A - B = A + ~B + 1!
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Figure 5. 32-bit Full Adder circuit with subtraction
Figure 6. 32-bit Full Adder external view
6. Overflow Output
The carry occurs when the final addition or subtraction is too big to fit into 32 bits. A related
mathematical output is overflow. This indicates that the sign of the mathematical result differs
from the sign of the two inputs. Overflow occurs when the size of the inputs is such that there is a
carry, which changes the most-significant sign bit. The Fig. 7 shows the overflow circuit.
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Figure 7. Overflow circuit
7. Combine All The Units (AND,OR,ADD/SUB)
The below schematic diagram (Fg.8) shows how to connect all the sub blocks together for
complete 32-bit ALU.
Figure 8. Block diagram of 32-bit ALU
Next we are going to develop this on Logisim by using develop sub blocks. Figure 9 shows the
complete 32-bit ALU in Logisim
Multiplexor 1
Multiplexor 2
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Figure 9 Complete 32-bit ALU
When C1=0, the ANDOR result is A OR B, and the ADDSUB result is A + B.
When C1=1, the ANDOR result is A AND B, and the ADDSUB result is A - B.
The second multiplexor C2, which chooses either the bitwise logic result or the mathematical
result.