Enabling adaptable IEC 61499-based cyber-physical systems using SoC FPGAs and partial reconfiguration

Abstract

In this paper we analyze the state of the IEC 61499 standard for the specification of distributed control systems (DCS). First, we discuss the limitations of previous efforts regarding the implementation of DCS, as well as the rationale for the introduction of the IEC 61499. Then, we embark then in a succinct analysis of the standard and the associated models for DCS platforms, outlining the main barriers that have hindered its widespread adoption. We argue that a common architectural framework (which is currently lacking) for implementing full-fledged IEC 61499 is necessary, especially if features such as fine-grained distribution and reconfiguration are to be supported. We posit that Dynamically Reconfigurable Systems on Chip (DR-SoCs) represent an excellent implementation choice for enabling such platforms, in great part to the strides made by the reconfigurable computing community in recent years, in terms of the advances in tools and methods for implementing such systems. Moreover, we provide some compelling reasons for bringing those two domains together, as well as the challenges that need to be overcome in order to harmonize both efforts.

Full text

–
Enabling adaptable IEC 61499-based cyber-physical systems using
SoC FPGAs and partial reconfiguration
Gilberto OCHOA-RUIZ, Tecnologico de Monterrey (Mexico)
In this paper we analyze the state of the IEC 61499 standard for the specification of distributed control
systems (DCS). First, we discuss the limitations of previous efforts regarding the implementation of DCS, as
well as the rationale for the introduction of the IEC 61499. Then, we embark then in a succinct analysis of
the standard and the associated models for DCS platforms, outlining the main barriers that have hindered
its widespread adoption. We argue that a common architectural framework (which is currently lacking) for
implementing full-fledged IEC 61499 is necessary, especially if features such as fine-grained distribution
and reconfiguration are to be supported. We posit that Dynamically Reconfigurable Systems on Chip (DR-
SoCs) represent an excellent implementation choice for enabling such platforms, in great part to the strides
made by the reconfigurable computing community in recent years, in terms of the advances in tools and
methods for implementing such systems. Moreover, we provide some compelling reasons for bringing those
two domains together, as well as the challenges that need to be overcome in order to harmonize both efforts.
Categories and Subject Descriptors: C.1.3 [Computer Systems Organization]: Processor Architectures -
Adaptable Architectures; D.2.2 [Software Engineering]: Design Tools and Techniques
General Terms: Design, Hardware, Algorithms, Control, Machines, Industrial Plants
Additional Key Words and Phrases: IEC 61499, Distributed Control Systems, DRSoCs, Reconfiguration
ACM Reference Format:
Ochoa-Ruiz, G., Bevan, R., Lamotte, F., and Diguet, J.-P., 2019. Enabling adaptable IEC 61499-based cyber-
physical systems using SoC FPGAs and partial reconfiguration ACM Comput. Surv. -, -, Article – (September
201-), 45 pages.
DOI:http://dx.doi.org/10.1145/0000000.0000000
1. GENERAL INTRODUCTION
Today’s fast-changing manufacturing markets and the stringent requirements in
terms of decreasing time-to-market are forcing a paradigm shift in the manufactur-
ing processes. These tight requirements point towards an increased complexity of the
industrial environments and the associated control settings, largely driven by the aug-
menting necessities of the current mass production markets: lean and flexible produc-
tion, with the inherent high-performances requirements, such as zero defects, declin-
ing costs, increased production flexibility (for product diversification), and improved
dependability, among others. Hence, in order to cope with those demands and other
emerging requirements, new manufacturing infrastructures and production facility op-
eration methods are very much required, as well as new devices and embedded tech-
nologies to support them.
*Gilberto Ochoa Ruiz is Associate Professor at Tecnologico de Monterrey: gilberto.ochoa@tec.mx
Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted
without fee provided that copies are not made or distributed for profit or commercial advantage and that
copies show this notice on the first page or initial screen of a display along with the full citation. Copyrights
for components of this work owned by others than ACM must be honored. Abstracting with credit is per-
mitted. To copy otherwise, to republish, to post on servers, to redistribute to lists, or to use any component
of this work in other works requires prior specific permission and/or a fee. Permissions may be requested
from Publications Dept., ACM, Inc., 2 Penn Plaza, Suite 701, New York, NY 10121-0701 USA, fax +1 (212)
869-0481, or permissions@acm.org.
c
201- ACM 0360-0300/201-/09-ART– $15.00
DOI:http://dx.doi.org/10.1145/0000000.0000000
ACM Computing Surveys, Vol. -, No. -, Article –, Publication date: September 201-.

–:2 G. Ochoa-Ruiz
Fig. 1. Typical IPMCS hardware architecture for factory floor automation
One of the main challenges in the implementation of effective Distribution Control
Systems (DCS) concerns the development of the encompassing control algorithms. It
has been widely recognized that the current design practices in the development of
control applications, in tandem with their deployment in centralized DCS represent
the main barrier hindering the much sought improvements in the manufacturing and
distributed control domains. Moreover, the hardware control architectures in which
they are typically integrated do not lend themselves very well for the much needed
adaptability and flexibility.
Therefore, in recent years, many research endeavors have been conducted to improve
the capabilities of such manufacturing control systems, mainly based on the concept of
distributed intelligent control. The resulting automation models are encompassed by
wide networks of DCS (interconnected through field area networks, using fieldbuses),
as depicted in Figure 1, an approach that can potentially bring many advantages in
the domain, such as modularity and decentralization, and thus increased resilience.
This DCS paradigm poses very specific issues and stringent requirements in terms of
the latency, reliability and availability of the of the control system and thus, it is widely
accepted that traditional frameworks, based on PLC architectures are not effective
enough for meeting such constrains, a limitation that stems from the cycle-scan execu-
tion of the underlying platforms. These limitations have been especially evident with
the advent of new automation paradigms, such as the IEC 61499 standard. Therefore,
practitioners in the domain have been looking for manners to respond to these hetero-
geneous and often contradictory constraints [Gerber et al. 2008]. In recent years, there
has been a trend towards the creation and use of Intelligent Electronic field Devices
(IEDs) or Intelligent Mechatronic Components (IMCs), which contain a certain amount
of computing power and communication capabilities [Thramboulidis 2008].
In this context, complex functions could then be distributed over or allocated onto
such IEDs, resulting in a decreased processing load for the main PLCs and a consid-
erable reduction in the necessary bandwidth requirements of the overall application,
making the devices smarter, and more easy to design and validate, as well as leading
to ”processing at the edge” approaches. Such IMCs, with tightly integrated communi-
cation and configuration services, and coupled with embedded control functions could
expedite system integration, whilst fostering extended features such as run-time re-
configuration and monitoring [Sunder et al. 2008].
However, a major hurdle for the interoperability of such IEDs is represented by the
plethora of communication protocols used in current DCS [Andren et al. 2012], both
for the wired and wireless sections of the plant (Figure 1).
ACM Computing Surveys, Vol. -, No. -, Article –, Publication date: September 201-.

Enabling adaptable IEC 61499-based cyber-physical systems –:3
Therefore, new platforms should integrate the infrastructure for supporting multi-
ple industrial protocols, in a cost-effective manner, while enabling to cope with new
developments, first at the device level, via features such as on-demand reconfigura-
tion and distribution, and secondly, through the use of configurable and customizable
on-demand communication gateways [Patil et al. 2013].
These configurable and intelligent gateways [Astarloa 2016] , in tandem with a cus-
tomizable and reconfigurable platforms, could bring many benefits in the specification
and implementation of full-fledged IEDs and other components in DCS, in particular
those advocated by the IEC 61499 standard, as we will thoroughly argue in this article.
Indeed, current paradigms and tools are regarded as too limited by many specialists,
since they impose the use of platform-specific and fixed interfaces for implementing
events and data transfers over the industrial Ethernet network and to communicate
with the I/O sub-system of the sensors and actuators they service.
In this paper, we posit that using FPGA devices, in tandem with advanced partial
reconfiguration techniques, could coalesce into an effective implementation choice for
creating highly configurable, customizable and adaptable DCS and of the constituent
intelligent electronic devices (IEDs). Such systems, capable of mixing heterogeneous
functionalities which can be dynamically reconfigured and distributed, are henceforth
referred to as Dynamically Reconfigurable Systems on Chip (DRSoCs).
The rest of the article is organized as follows. First, we provide ample motivations
for a shift in the design of DCS, based on the limitations of the current device and
programming paradigms in Section 2. Afterwards, we present the IEC 61499 standard,
which was introduced a decade ago to address many of the limitations in DCS; we
analyze some of the provisions of the standard, and discuss how the current hardware
models are hampering its effective implementation. Then, in Sections 4 - 6, we provide
some compelling reasons for using programmable devices and DRSoCs in the design
and implementation of IEC 61499-based DCS platforms. Subsequently, in Section 7 we
discuss what needs to be done, in terms of methods and tools, to make this convergence
possible, as well as the current limitations. Finally, we conclude with some research
directions that we consider worth pursuing.
2. MOTIVATION: LIMITATIONS OF CURRENT DISTRIBUTED CONTROL SYSTEMS
Most of the current process control platforms, globally known as Industrial Process
Measurement and Control Systems (IPMCS) are based on the well-known and widely
used IEC 61131-3 standard [IEC 1993], which was introduced by the International
Electrotechnical Commission (IEC). These systems are typically built around tradi-
tional PLC architectures, which are generally oriented towards centralized applica-
tions, in which several nodes retrieve data from the plant and adjust their behavior
through actuators. These solutions are not well suited for implementing complex DCS
for many reasons, the most important being that existing approaches are designed
under the execution constraints imposed by the cycle-scan nature of the PLC devices.
This leads to significant limitations in the management of incoming events, as well as
the throughput and real-time response of the underlying control software, especially if
communication latencies are taken into consideration.
Recent developments in the automation domain point towards a shift in the underly-
ing Intelligent Control Production Systems: they need to be thoroughly re-architected
so that heterogeneous systems can be flexibly and seamlessly composed, from single
machines to entire plants and distributed systems. This entails a paradigm shift from
current practices and formalisms (i.e., programming languages, execution semantics),
as well as the conception of new technologies and devices, as depicted in Figure 2
(adapted from [Vyatkin et al. 2003]).
ACM Computing Surveys, Vol. -, No. -, Article –, Publication date: September 201-.

–:4 G. Ochoa-Ruiz
Fig. 2. Requirements for effective agile production systems, according to the OONEIDA framework
The so-called Agile Production Systems paradigm entails many benefits in the de-
sign, configuration and adaptation of production systems, since it encourages the en-
capsulation and reuse of control algorithms and other development libraries from the
automation domain through the use of mechatronic components, which can signifi-
cantly ease the integration and programming of complex DCS. However, such novel
engineering frameworks need to be accompanied by widely used and accepted open de-
sign tools and facilities, encompassed by visual editors, compilers and generators as
well as platforms and validation tools. Moreover, in order to cope with the increased
capabilities required by DCS, novel Open Run-time Platforms need to be conceived in
order to support the much sought Intelligent Technologies described above, capable of
reconfiguration, distribution, diagnosis and fault recovery. The latter represents not
only technological paradigm, but also a methodological one, in which the various as-
pects of the design process can be holistically defined.
The rigid character and insufficient agile capabilities of the current manufacturing
systems can be deemed to the existing design approaches, based on centralized archi-
tectures and hierarchical control infrastructures. Most of these approaches are based
on the well-known IEC 61131-3 standard and the associated programming languages,
which although represented a successful endeavor for the convergence of PLC-based
systems, is currently hindering the adoption of new paradigms.
The main rationale behind the introduction of the IEC 61131-3 standard was to
harmonize disparate programming concepts from the industrial control domain [Zoitl
et al. 2009], by introducing software engineering concepts into the former. A great deal
of progress was made by the IEC in this regard, by defining a set of common languages
for PLC programming, which led to a widespread adoption of the standard. However,
due to extensions added by vendors, interoperability and straightforward reuse are
still not completely feasible. Moreover, some of the extensions introduced a handicap
in the modularity and encapsulation of the basic unit of control, the Function Block,
through the use of global variables.
During the last few years, these issues have been tackled by the industry and the
academia at large, specifically through endeavors such the Intelligent Manufacturing
Systems (IMS) initiative, which aimed at defining new means for developing and ac-
celerating the adoption of the next generation of open, modular, reconfigurable, main-
tainable and dependable manufacturing systems. The resulting IEC 61499 standard
[IEC 2005] for DCS was conceived as a framework for modeling exchangeable and dis-
tributed IPMCS applications [Lewis 2001].
The specification represents an evolution over the IEC 61131-3 standard to incor-
porate the demands of flexible and adaptive paradigms into DCS. One of the main
goals of the standard is to obtain vendor-independent application and hardware con-
figuration descriptions, based on the integration of control algorithms in the so-called
Function Blocks (FB), with improved encapsulation features.
ACM Computing Surveys, Vol. -, No. -, Article –, Publication date: September 201-.

Enabling adaptable IEC 61499-based cyber-physical systems –:5
The rationale for this encapsulation is that fosters reuse in application-centered mod-
eling methodologies (in a platform independent manner, later refined to be deployed in
a given compliant hardware device). An application is represented as a network of
distributed and communication FB instances that monitor signals from cyber-physical
system through sensors, and produces events and data that are retro-alimented through
actuators. Therefore, the standard was conceived as an effort to address the limitations
of current IPMCS systems by promoting the advantages of DCS in terms of modularity,
ease of integration (and reuse), reconfigurability, and deployment in multiple devices
(interoperability and distribution) [Dubinin and Vyatkin 2008].
Another major change with respect with the previous standard is the introduction of
an event-driven approach for the execution of control algorithms embodied by Function
Blocks. This entails a larger flexibility in the scheduling of the underlying function-
alities, and the use of the associated resources, as well as gains in terms of the real-
time response of the individual sub-components. Some of the main concepts of the IEC
61499 standard, as well as its limitations will be discussed in the next section.
3. THE IEC 61499 STANDARD FOR DCS: CONCEPTS, CHALLENGES AND LIMITATIONS
In the previous section, we discussed some the challenges faced by the current indus-
trial automation methodologies, in terms of the procedural and architectural paradigm
shifts that are required for addressing the much-needed agile capabilities of future
manufacturing infrastructures. The IEC 61131-3 standard represented a first attempt
at addressing many of the issues hindering the adoption of a common base for program-
ming for Programmable Logic Controllers, but it suffers of poor real-time performances
and scalability issues (especially in highly distributed plants), due to the scan-based
nature of the execution platforms.
However, the most limiting aspect of the standard can be attributed to the poor
encapsulation previsions for the Functions Blocks (FBs), as well as the use of global
variables used for data exchange among processes. These limitations impede its de-
ployment in the creation of truly distributed and reconfigurable systems, characteris-
tics regarded as essential in the future of manufacturing systems by the influential
Iacocca Institute [Wenbin and Vyatkin 2012].
The Holonic Distributed Systems paradigm has been introduced as a concept that
encompasses the requirements for creating full-fledged distributed control systems.
The approach aims at providing means for enabling the creation of highly integrated
DCS, mainly through: reusability, configurability, portability, flexibility and reconfigu-
ration, which have been accounted for during specification of the IEC 61499 standard,
as depicted in Figure 3. These requirements are briefly described as follows:
—(a) Portability: The capability of the control software to be ported or exchanged in
a seamless manner across different platforms.
—(b) Configurability: Any device, regardless of the vendor, can be programmed using
a piece of code compliant with the standard and configured by other tools/devices.
—(c) Interoperability: Embedded control systems can operate in unison to perform
the overall distributed application (by using common communication protocols and
other data exchange mechanisms). Several accompanying standards by the IEC have
been conceived to further promote this convergence, such as the IEC 62424.
—(d) Reconfiguration: The capability to dynamically modify control hardware and
software functions at run-time and on-demand, without affecting the rest of the sys-
tem, supporting various granularities (i.e., functions, complete device configuration).
—(e) Distribution: The allocation of portions of the application (control algorithms in
the form of FBs) onto different devices, with varying degrees of granularity.
ACM Computing Surveys, Vol. -, No. -, Article –, Publication date: September 201-.

–:6 G. Ochoa-Ruiz
Fig. 3. Desirable features of a DCS platform based on the IEC 61499 standard
The main scope of the IEC 61499 specification was not to produce a programming
methodology per se, but to introduce first and foremost a common model for DCS: it can
be seen then as a model-based approach with many commonalities with Model-Driven
Engineering (MDE) [OMG 2014]. The standard provides a common terminology, as
well as concepts that allow the specification of applications, where the atomic unit is
the Function Block (FB) (Figure 4). The main rationale is to enable the exchange of
IPMCS platform descriptions in a formal manner [Lewis 2001]. In this manner, the
IEC aims at encouraging the adoption of the standard and of DCS systems at large in
automation applications, since the common concepts can be used to validate, compare,
reuse and exchange intellectual property control algorithms. As we will discuss in the
following sub-sections, the standard covers all the aspects described above, although
many nuances have been left open for interpretation (or as implementation specific
options) and have led to disparate research endeavors [Strasser et al. 2011].
3.1. The IEC 61499: the Function Block concept
At the very heart of the IEC standards, it’s the function block (FB) model that under-
pins the entire modeling approach (Figure 4), upon which various programming lan-
guages and execution models have been developed [Vyatkin 2009]. A FB is described
as a functional component with its own data structures, which can thus be accessed
and modified during the application execution. A FB type definition provides a formal
description of these data structures, and the algorithms to be applied to the incoming
signals, which are encoded within the various instances.
The rationale for this encapsulation is that promotes reuse in application-centered
modeling methodologies (in a platform independent manner, later refined to be de-
ployed in a given networked hardware system). An application is defined as an array
of interconnected FBs that accepts incoming signals from the plant through sensors,
and produces results that are sent back to the controlled system though a feedback
loop. Therefore, the standard was conceived as an effort to address the limitations of
current IPMCS systems, by promoting the advantages of DCS in terms of modularity,
ease of integration (and reuse), reconfigurability, and deployment in multiple devices
(interoperability and distribution).
In the IEC 61499 reference model, the FB encompasses an set of events, which can
be concurrently propagated or processed, as depicted in Figure 4 b), in contrast with
the IEC 61131-3 FB, in which the I/Os must be scanned at the end of each cycle of the
program Figure 4 a). The main advantage of these event-based execution approaches
is that it enables the independent execution of control processes, without the timing
penalties associated with scan-based automation systems. The events enable the exe-
cution of internal, user defined processes (i.e., control algorithms) under the control of
a federating control unit, known as the Execution Control Chart (ECC).
ACM Computing Surveys, Vol. -, No. -, Article –, Publication date: September 201-.

Enabling adaptable IEC 61499-based cyber-physical systems –:7
Fig. 4. Comparison between Function blocks in the a) IEC 61131-3 and b) IEC 61499 standards. c) An
example of the graphical representation of the Execution Control Chart associated with the IEC 61499 FB
There are four elements that define the properties and behavior of a FB: (i) the
external interface declaration, (ii) internal variables, (iii) the internal algorithms and
(iv) the execution of the latter through the transitions defined by the ECC. This is,
the internal algorithms process the incoming data and produce outcomes following
the state transitions specified by the ECC, which is merely a state machine in charge
of federating the various stages or life-cycle of a given sub-application component, as
depicted in Figure 4 c) .
The various algorithms in the FB are invoked by the resource scheduling function (to
be discussed in a subsequent section) in response to a particular combination of input
events arriving the FB interface. The associated algorithm is then allowed to process
data from internal variables/parameters and incoming data, which is only taken into
account during the arrival of the associated event. The transitions between states in a
ECC can be triggered either by an event or as a combination of an event and a Boolean
expression using incoming data or internal variables. When an internal function has
completed its execution, it may trigger output events to signal that output data is
ready to be consumed by other function blocks, either in the same device or a across
the DCS. Then the resource manager executive is responsible for transmitting such
data to other sub-components of the application.
The IEC 61499 does not define the language that should be used for the algorithms
implementation. Any high-level language can be used, provided that a mapping be-
tween the input and output data variables and their data types is specified; the same
applies for the variables within the algorithm descriptions. These algorithmic imple-
mentations have been traditionally carried out using Structured Text (one of the five
languages of the IEC 61131-3 standard for implementation in PLC machinery), or as
in more recent implementations for general-purpose MCUs, Java or C code has been
used instead. The same applies for the ECC, which can be described textually or graph-
ically, but it needs to be converted to code in order to be used within the IEC 61499
context [Zoitl et al. 2009]. The textual syntax is rather like a built list for electronic
circuits, which was developed to be used as a generic and portable algorithm descrip-
tion. Nonetheless, graphical representations help at making the control code easier to
develop and maintain, and many efforts have been done to coalesce both efforts.
ACM Computing Surveys, Vol. -, No. -, Article –, Publication date: September 201-.

–:8 G. Ochoa-Ruiz
3.2. The IEC 61499 standard: application and device models
At the physical level, a DCS can be seen as a set of devices which communicate through
several networks, comprised of various concurrent applications, which could require
the cooperation of software code running in a number of resources. Such resources can
be either within a single device or split among various devices located in different sites.
Such application can thus be modeled as a network of interconnected FBs.
As discussed above, the standard nurtures an MDE-like paradigm in which the ap-
plication is modeled in a platform independent manner (PIM) to enable exploring dif-
ferent design options. When mapping an application, the system designer assigns frag-
ments of the application (Composite FBs -CFBs- or single FBs) onto different devices
and resources (Platform Specific Model, PSM). Communication services (via the Ser-
vice Interface FBs, SIFBs) and management capabilities within the device guarantee
that the application is properly executed and scheduled, and caters for reconfiguration
and task allocation services as well.
An IEC 61499 compliant device, as depicted in Figure 5 a), should be able to support
one or more resources, which are broadly defined in the standard as any entity capa-
ble of providing self-reliant execution of FBs. As shown in Figure 5 b), the executed
applications rely on the support of their containing resources to access the device man-
agement services (such as external communications interfaces and scheduling events)
and to map requests to the controlled process via the associated I/O interface (process
interface). Moreover, the system configuration might change over time, either in its
entirety or by modifying functions allocated to some of the resources, which entails
various scheduling policies, as well as distribution and reconfiguration granularities.
Hence, a resource can be seen as the hardware underlying device (i.e., MCU), but
also as the associated execution environment for a process (i.e., a real-time OS). It is
clear that the resource sets the boundary that exists between the provisions in the IEC
61499 standard, and what represents device specific functionality.
3.3. The IEC 61499 standard: management, execution and reconfiguration
In order to carry out the management of the applications within a device, the speci-
fication provides guidelines for the features the device management should have, em-
bodied by the device management executive, as depicted on Figure 5 a). The device
management implements an executive application that can be seen as a middle-ware
layer between the high-level control software (known as the run-time environment)
and the underlying resources within the device, providing the necessary mechanisms
to exchange control commands and data among device networks, and to federate the
execution of the encompassing application FBs within the device’s resources.
Fig. 5. IEC 61499 concepts: a) The device model and b) Resource model
ACM Computing Surveys, Vol. -, No. -, Article –, Publication date: September 201-.

Enabling adaptable IEC 61499-based cyber-physical systems –:9
Fig. 6. a) IEC 61499 Device management concepts and b) Operational FSM for an execution thread
This managerial application should have higher privileges than normal applica-
tions, since it is indeed not only responsible of catering the communication with other
devices, but also of the scheduling of the internal application FBs by decoding the
high-level application commands, and monitoring incoming events from the encom-
passing resources. Furthermore, the device management application could also cater
for other, more supervisory, monitoring and security functions (SCADA), not yet de-
fined in the standard, but which are quite important due to the increased risks in the
use of interconnected industrial control systems (ICS). Nonetheless, and perhaps the
most important role of the device manager is that of enabling the necessary on-line
and on-demand reconfiguration capabilities within the application.
As depicted in Figure 6 a), the device manager needs to provide several services for
the management of its resources, so that the life-cycle of a given task can be properly
controlled: from its creation/allocation to its eventual removal, as depicted on Figure
6 b). An important feature of a resource is that it supports autonomous operation: a
resource can be initialized and configured, and subsequently stopped without inter-
fering with other resources in the same device, enabling zero-downtime, on-demand,
glitch-less reconfiguration. Finally, in order to schedule, load and execute the function-
alities within the a resource, a run-time environment must be provided [Zoitl 2009].
The above-mentioned aspects are not yet well defined in the standard, and represent
interesting research avenues to be explored.
The majority of the existing IEC 61499 solutions are based on general purpose CPUs.
As with traditional PLCs, their performance suffers from the manner in which the
event-based nature of the standard has been implemented (based on traditional se-
quential architectures): different interpretations of the standard have led to heteroge-
neous models of execution, event dispatching, and scheduling, and in general, to rather
poor real-time performances [Strasser et al. 2011]. Recent proposals in the literature
[O’Sullivan and Heffernan 2010] point at the use of FPGAs for implementing IEC
61499 platforms, with the aim of attaining full-fledged parallel event-based systems,
with much shorter control periods and streamlined execution semantics, which has
been demonstrated in other fields (i.e., motion controllers [Monmasson et al. 2011]).
3.4. The IEC 61499 standard: Limitations, challenges and open problems
The IEC 61499 standard has been available for over a decade and has gained consider-
able traction within the academic community, resulting in many disparate approaches
regarding the various aspects of the reference model (i.e., application semantics, execu-
tion polices, scheduling, reconfiguration, etc.). Several survey articles and collections
have been published, pointing at the current status of the standard[Vyatkin 2013].
ACM Computing Surveys, Vol. -, No. -, Article –, Publication date: September 201-.

–:10 G. Ochoa-Ruiz
Most works point at the relatively slow adoption rate of the IEC 61499 standard
in actual industrial applications. This should not be surprising given the significant
paradigm shift promoted by the norm, which requires to move from device-centric ap-
proaches to applications running in multiple target technologies. Indeed, with the in-
troduction of IEDs, the focus is no longer only on PLC devices, but on more varied
ecosystems, encompassed by micro-controllers and more recently, reconfigurable devices
and architectures (FPGAs). Therefore, the languages that can be used to implement
DCS extend beyond those in the IEC 61131-3 specification [Dai et al. 2013].
Another issue, repeatedly discussed in the literature, concerns the open-ended na-
ture of the IEC 61499 specification, which was conceived more in the manner of gen-
eral guidelines than a programming language, as discussed above. It has been argued
that leaving actual implementation recommendations out of the specification standard
is hindering its adoption, in detriment of the overall endeavor [Thramboulidis 2012].
Furthermore, the lack of mature reference hardware implementations, to demonstrate
both the applicability and the advantages of the DCS paradigm, and on the other hand,
the required learning effort can also explain such slow adoption rate.
Several experimental academic tools or integrated development environments (IDEs)
have been developed to facilitate the development of IEC 61499 applications, such as
FBDK (from Holobloc) and the Framework for Distributed Automation and Control
(4DIAC)[Zoitl et al. 2013], whereas industrial-grade tools such as ISaGRAF have been
introduced recently. However, these tools implement the guidelines of the standard in
very different manners, first in terms of the programming languages used and sec-
ondly, in the manner the applications are simulated, scheduled and executed (i.e. the
execution semantics of the run-time environment, RTE) [Strasser et al. 2011].
Moreover, it has been widely recognized within the automation community that a
great deal of research avenues remain uncharted in regard with the provisions of the
IEC 61499 standard. In particular, current tools and models do not fully support device
management applications nor reconfiguration modeling. Especially, novel and more
heterogeneous platforms are required to articulate the efforts in this domain, and to
fully harness the capabilities sought by the standard, enabling fully customizable and
adaptable IEC 61499-based DCS systems.
We believe that reconfigurable devices (i.e., FPGA-based SoCs) [Goeders et al. 2015]
could help to alleviate these issues, implementing the device management services,
while enabling faster execution time and true distribution of FBs in the programmable
logic, and adapting the communication protocol for a given scenario (and thus widen-
ing the options available for implementing several types of SIFB in hardware). The
former issue could be simply solved by the specialization capabilities afforded by using
reconfigurable devices, or through a more sophisticated approach, which tackles both
issues. Indeed, the use of reconfigurable devices in tandem with partial reconfigura-
tion, and the associated and well researched management capabilities of DRSoCs could
have major implications in the development of IEC 61499-based platforms.
Some initial efforts have pointed at the utilization of reconfigurable devices (i.e., FP-
GAs) for implementing automation systems, but traditional approaches do not support
reconfiguration and thus features such as distribution. Moreover, there are two ma-
jor approaches for tackling such kind of implementations: they either transform IEC
61131-3 code (i.e., ladder diagrams) into full configuration images for the FPGA, or into
programs to be run by multi-processor SoCs within a reconfigurable device. The former
approach trades reuse for performance, whereas the latter sacrifices performance but
gains in reconfiguration and distribution capabilities. Moreover, most of these systems
do not fare very well regarding what type of algorithms can be implemented, because
they either target software or hardened IEC 61131-3 implementations, but rarely a
mix of both, which can prove useful in many instances.
ACM Computing Surveys, Vol. -, No. -, Article –, Publication date: September 201-.

Enabling adaptable IEC 61499-based cyber-physical systems –:11
Some of these efforts will be discussed in the next section, along some still very
incipient implementations of the IEC 61499 standard in FPGAs. These efforts seek
to improve the IP reuse and virtualization aspects inherent to the standard, albeit
without tackling other important features, since they do not support reconfiguration
and/or distribution of FBs and resources, leading to poor implementations in terms of
the consumed resources.
4. RECONFIGURABLE SYSTEMS IN AUTOMATION: TRENDS AND OPPORTUNITIES
For quite some years, reconfigurable platforms such as FPGAs have been successfully
used in many products, first as ASIC replacements and increasingly as a means of
closing the gap in HW/SW development, through the combination of high-performance
processors and reconfigurable logic. The use of FPGAs generally entails higher perfor-
mances than microprocessor-based solutions, while ensuring a higher degree of flexi-
bility than ASICs, due to their capability to be updated in the field [Hartenstein 2007].
Moreover, FPGA devices enable faster prototyping turn-around times compared to
the latter, a fact that has increased their integration in high-end/low-volume products.
In recent times, there has been an augmented interest in deploying FPGA devices in
industrial applications such as motor controllers [Santarini 2010], both for the im-
plementation of Intelligent Electronic Devices (IEDs) [Gomes et al. 2013], and for the
creation of PLC-like solutions [Chmiel et al. 2010], as well as intelligent comunication
gateways [Chang 2015]. Thus, as we will discuss in the following sections, a harmo-
nization of both axes is possible through IEC 61499 compliant SoC FPGA solutions,
for the reasons discussed at the end of the previous section.
4.1. FPGA architecture principles
An FPGA device is an integrated circuit with a central array of logic blocks that can be
connected through a configurable interconnect routing matrix. Around the periphery
of the logic array is a ring of I/O blocks that can be configured to support different
interface standards, as depicted in Figure 7.This flexible architecture can be used to
implement a wide range of synchronous and combinatorial digital logic functions.
This is due to the fact that their underlying fabric predominantly consists of large
numbers of relatively simple programmable logic block islands embedded in a sea of
programmable interconnect. In this manner, the user can map a great deal of different
Fig. 7. Example of FPGA architecure
ACM Computing Surveys, Vol. -, No. -, Article –, Publication date: September 201-.

–:12 G. Ochoa-Ruiz
types of algorithms onto this reconfigurable fabric, which can be generated in a number
of ways, as we will briefly discuss in the next sub-section.
Furthermore, in order to provide greater performance or flexibility in the applica-
tions that can be mapped to reconfigurable devices, FPGA vendors have gradually in-
corporated more functionalities into their programmable chips [Kuon and Rose 2010].
These functionalities are embedded among the circuit logic resources, producing a het-
erogeneous structure, where the capabilities of the logic cells are not the same through-
out the system. This approach has become a necessity due to the widespread adoption
of FPGAs for implementing complex platforms, such as Systems on Chip, where mul-
tiple processors, communication standards and memory controllers are required.
Furthermore, many applications (such as control and signal processing) often re-
quire of complex functions such adders and multipliers, along complex and highly pa-
rameterizable DSP Blocks. In both scenarios, such modules are difficult to implement
in an optimal manner using generic FPGA logic resources; therefore, FPGA vendors
have introduced such complex blocks in the form of hardwired functions.
These blocks are designed to be as efficient as possible in terms of power consump-
tion, silicon real estate, and performance. Each FPGA family features different combi-
nations of such blocks, together with varying quantities of programmable logic blocks,
which enables the designer to choose the correct device for a given application.
Another type of heterogeneous logic structures are memory blocks, known as Block-
RAMs, which are scattered throughout the reconfigurable hardware. These blocks en-
able the storage of frequently used data and variables, and permit a quick access to
these values due to the proximity of the memory inside the FPGA to the logic. These
blocks can also be used for a variety of purposes, such as implementing standard
single- or dual-port RAMs, FIFO functions, state machines, and so forth.
Another major trend has been a move towards the introduction of complete micropro-
cessor solutions into the FPGA fabric [Hartenstein and Kaiserslautern 2007]. For in-
stance, soft-core processors (i.e. components that made use of the FPGA logic resources
for their implementation) have been deployed in a variety of applications where some
form of management or intelligence is required. Additionally, the use of embedded
processors brings many advantages, particularly the reduction in chip count, signal
integrity issues, and a decrease on the board complexity.
Similarly, as performance and throughput become increasingly important, modern
FPGA devices offer support for various high-speed communication standards. This
is due to the high-performance of FPGA in accelerating complex computations: data
needs to be transmitted rapidly and efficiently to other nodes of the system, while pre-
venting the device to become the bottleneck of overall the platform. Examples of these
standards are Infiniband, PCI Express, RapidIO, and 10-gigabit Ethernet, among oth-
ers. In a similar manner, vendors offer optimized hardwired cores for a variety of solu-
tions; examples of these cores are memory controllers (for DDR, DDR2 and DDR3 type
memories), MAC controllers (for implementing the physical layer of Ethernet-based
communication standards), and LVDS Transmitters [Maxfield 2009].
At the other end of the spectrum, soft IP refers to a source-level library of high-level
functions that can be included in the design. These functions are typically implemented
using or transformed to a hardware description language, or HDL, such as Verilog or
VHDL at the Register Transfer Level (RTL) of abstraction. Any soft IP functions the
designers decide to use are incorporated into the main body of the design, which is also
specified in RTL and subsequently synthesized down into a group of programmable
logic blocks (possibly combined with some hard IP blocks like multipliers, DPR and
BRAMs) and then mapped onto the FPGA. In the next section, we will briefly discuss
some of the approaches for creating and integrating such soft IP blocks into a design,
since it will be helpful for the discussion that follows.
ACM Computing Surveys, Vol. -, No. -, Article –, Publication date: September 201-.

Enabling adaptable IEC 61499-based cyber-physical systems –:13
4.2. Approaches for mapping algorithms to reconfigurable logic
The evolution of computing architectures, spurred by the relentless growth in silicon
integration technology, has seen the development of great number of algorithmic im-
plementation approaches. These platforms include single chip Multiprocessor or het-
erogeneous system-on-chip (MPSoC) solutions, Networks on Chip and indeed, FPGA-
based implementations of such types of architectural paradigms [Dubey 2009].
Modern applications implemented in FPGA-based MPSoC platforms are encom-
passed mixture of heterogeneous processing architectures, including Microcontroller
Units (MCU), increased computationally capable processors such as VLIW DSP micro-
processors, or dedicated hardware, in the form of soft IP for efficient hardware acceler-
ated implementations (often as a substitute or complement to existing software-based
platforms) [Woods et al. 2008]. Nonetheless, the use FPGA-based embedded platforms
entails entirely different and more complex implementation issues to the designer, due
to the lack of a pre-defined processing architectures and the level of expertise required
for successfully implementing complex systems in reconfigurable devices.
This wide range of target processing platforms and corresponding implementation
techniques makes algorithmic implementations, at the current levels of design abstrac-
tion, an arduous task. Consequently, the use of novel rapid implementation frame-
works (for facilitating tasks such as code generation and function wrapping, system
integration, HW/SW co-design, and systems validation) is essential, and has been an
active area of research for some time within the SoC and EDA communities.
As the complexity and density attainable by FPGA vendors has increased with
Moore’s Law, FPGAs passed from simple glue-logic devices to more complex systems
for DSP applications and in packet processing in networking applications, becoming in
many instances the federators and control management units of the devices they are
integrated, and showing significant speed-ups in many applications.
This substantial jump in performance required similarly substantial advances in
FPGA design tools [Maxfield 2009]. The key feature of HDL-based design flows is their
use of logic synthesis technology, as depicted in Figure 8, which began to appear on the
market around the mid-1980s. FPGA tools traditionally take as input an RTL repre-
sentation of a design, along with a set of timing constraints.
The logic synthesis process automatically transforms the RTL code into a mixture of
registers and Boolean equations, performs a variety optimizations (i.e., area and tim-
ing), and then generates a gate-level netlist that should meet the specified timing con-
straints. Subsequently, technology-specific placement and place-and-route algorithms
are deployed for generating a physical implementation of the original specification,
which can then translated into an actual bitstream for configuring the device. An al-
ternative process might consist in packaging the RTL implementation using a bus
wrapper, with the associated metadata for IP reuse in SoC-based designs.
Fig. 8. Basic HDL-based design flow for FPGA implementation
ACM Computing Surveys, Vol. -, No. -, Article –, Publication date: September 201-.

–:14 G. Ochoa-Ruiz
Despite the success of HDL-based FPGA implementations, the associated design pro-
cess has some major drawbacks [Blouin et al. 2015]: i) Capturing and verifying RTL
design is time-consuming, ii) evaluating alternative implementations is difficult, since
it requires a long and time-consuming re-design process, iii) accommodating specifica-
tion changes and evolving a design can be rather difficult and finally, iv) RTL specifi-
cations are often implementation specific (retargeting a complex design represented in
RTL from one implementation technology to another can be a complex process).
Furthermore, the traditional FPGA design flow, based on traditional HDL specifica-
tions is less than ideal for hardware-software co-design strategies in SoC implementa-
tions. Irrespective of whether these designs are to be realized using ASICs or FPGAs,
todays SoCs are exhibiting an ever-increasing amount of software content [Densmore
and Passerone 2006]. When coupled with increased design reuse on the hardware side,
in many cases it is necessary to verify the software and hardware concurrently so as to
completely validate such things as the system diagnostics, RTOS, device drivers, and
embedded application software. Generally speaking, verifying the underlying hard-
ware represented in VHDL or Verilog, in conjunction with the software described in C
or assembly language is becoming a very complex process to manage efficiently.
FPGA-specific system synthesis problems are numerous. Three concerns are most
prominent for the SoC community at present: synthesis of dedicated hardware intellec-
tual property (IP) cores and their integration in MPSoCs; software synthesis for multi-
processor architectures which caters for HW/SW co-design practices, and finally large-
scale system level design and fast prototyping techniques for deriving and automatically
realizing a given application onto an heterogeneous FPGA architecture.
One of the approaches in vogue in recent years has been the use of high-level lan-
guages (HLLs), as well the introduction of the associated compilation techniques to
facilitate the design process of SoC platforms in general and of FPGA-based archi-
tectures in particular, by facilitating the mapping of domain-specific applications into
reconfigurable devices, closing the gap between software and hardware development
and shortening the design process [Coussy 2008].
During the 1990s, the first generation of commercial High-Level Synthesis (HLS)
tools was made available commercially. Around the same time, research interest on
hardware-software co-design, including estimation, exploration, partitioning, interfac-
ing, communication, synthesis, and co-simulation has gained momentum, as thor-
oughly discussed in [Sangiovanni-Vincentelli 2007]. Futhermore, the concept of IP
reuse and platform-based design started to emerge in the 2000s, with a shift to an
electronic system-level (ESL) paradigm that promises to improve the exploration, syn-
thesis, and verification of complex SoCs.
One of the major trends in ESL is the use of HLS techniques for implementing a
variety of complex algorithms into hardware [Coussy et al. 2009]. HLS tools transform
an untimed high-level specification into a fully timed implementation. They automat-
ically or semi-automatically generate a custom architecture to efficiently implement
the specification. In addition to the memory banks and the communication interfaces,
the generated architecture is described at the RTL level and contains a data-path and
a controller, as required by the given specification and the design constraints. Such
specification can be further packaged and wrapped using bus interfaces for promoting
IP reuse, facilitating system integration and fostering HW/SW co-design strategies.
The principles behind HLS techniques, as well successes, advantages and disadvan-
tages of such approaches are out of the scope of this article, but the reader is directed
to excellent sources in this domain [Gerstlauer et al. 2009]. Nonetheless, in the next
section we will explore some incipient attempts at exploiting HLS techniques and in
some instances, the MPSoC paradigm for implementing automation systems in FPGA,
based both in the IEC 61131-3 and IEC 61499 standards, as well as their limitations.
ACM Computing Surveys, Vol. -, No. -, Article –, Publication date: September 201-.

Enabling adaptable IEC 61499-based cyber-physical systems –:15
4.3. Initial efforts for implementing algorithms based on the IEC norms into FPGA
The study of the possibilities of FPGAs for implementing PLC-based systems has been
a dynamic area of research in recent years [Milik 2016]. The most important benefits
of using reconfigurable devices for implementing PLC platforms are related to per-
formance, both in terms of the execution speeds that can be attained by massively
parallel architectures, in tandem with significantly larger I/O processing capabilities,
which have been regarded as essential for overcoming the limitations of cycle scan-
based solutions.
Several approaches have been proposed in the literature, which we have broadly
divided in the next two sections: the former analyses efforts for transforming IEC
61131-3 into synthesizable code for PLC in FPGA implementations, whilst the latter
discusses incipient implementations of IEC 61499 systems in programmable devices.
4.3.1. Implementations of the IEC 61131-3 norm in FPGA devices.In recent years, several
tools and design methodologies have been developed, which aimed at providing means
to transform IEC 61131-3 algorithms (based mostly on Sequential Function Charts -
SFC- or Ladder Diagrams -LD-) into executable code, which can be directly deployed
into custom architectures running in FPGA devices.
From the existing literature, we can distinguish two main architectural approaches
to implement such kind of devices: the first one tackles the problem by transforming
IEC 61131-3 code into HDL code, whereas the second takes advantage of the possibility
to implement multiple processors into a single FPGA device and the availability of
hundreds of I/O signals to expedite the performance.
The former approach can be indeed lumped to other ongoing efforts in applying HLS
techniques to the design and implementations of complex control algorithms in recon-
figurable devices, with the aim of shielding the designer of domain and technology spe-
cific aspects of FPGA technology. Some incipient solutions can be found in [Du et al.
2010], where the authors describe a methodology for converting PLC programs into
Verilog code, whereas the work of [Ichikawa et al. 2011] caters for the generation of
FPGA systems from LD diagrams.
A more comprehensive and formal approach to this problem has been presented in
[Milik 2016], where the authors make use of a language-independent PLC program
representation as a passage between LD and SFC programs and hardware dependent
functions in the FPGA, based on an Enhanced Data Flow Graph (EDFG) approach for
HLS. Once converted to this representation, the control algorithms undergo a series
of optimization techniques for implementing a variety of functions, either in general
purpose logic (CLB and LUTs) or using specialized DSP48 blocks of the FPGA. Several
experiments have been carried to demonstrate the suitability of this latter approach;
for instance, the authors present the implementation of various LD and SFC-based
programs encompassing logic, timers and PID controllers and combinations thereof as
depicted on Figure 9.
Fig. 9. Comparison of various implementations of IEC 61131-3 algorithms into FPGA
ACM Computing Surveys, Vol. -, No. -, Article –, Publication date: September 201-.

–:16 G. Ochoa-Ruiz
We focus on the results of [Milik 2016] mainly due to space considerations, but the
results shown here, and those presented in other works clearly demonstrate significant
speed up factors compared to algorithms implemented in traditional PLCs (Sismatic
S7) and on soft-processor PLCs in FPGA [Chmiel et al. 2010]. The table represents a
summary of a more exhaustive study, in which several mapping strategies have been
carried out, to assess the effect of the various implementation options, as it can be seen
in the last two lines of the table, trading resource utilization for performance.
Despite their appeal, the systems and design methodologies described above (es-
sentially small FPGA-based PLC on Chip [Gawali and Sharma 2009]), represent cen-
tralized solutions, using mostly digital I/Os and furthermore, and can be seen as all or
nothing solutions, in the sense that the generated code is used for programming the to-
tality of the FPGA. Moreover, such approaches pose other issues, which stem from the
poor encapsulation of the deployed algorithms and the manner they are implemented
into hardware. First of all, these approaches do not foster IP reuse or take advantage
of the inherent programmability of the FPGA, and therefore, adapting them to new
applications even if small changes are required is rather cumbersome. These limita-
tions also hamper features necessary for implementing agile DCS, such fine-grained
distribution and reconfiguration, issues that arise from the poor encapsulation strate-
gies attained by efforts as those discussed above. This problem is only worsened by the
fact that several tools and design and implementation tools are required in order to
map the original IEC 61131-3 algorithm into the FPGA.
Thus, a second approach for implementing PLC-like functionalities around the IEC
61131-3 standard in FPGA devices has recently caught momentum, based on the use of
aMulti-processor Systems-on-Chip (MPSoC) paradigm, which aims at improving the
programmability of FPGA-based solutions, as well as the portability of the the gen-
erated code, aided in many instances by co-processing units for implementing bitwise
operations [Gawali and Sharma 2009]. Examples of this kind of approach for imple-
menting a single micro-PLC can be found in [Chmiel et al. 2010], which runs LD code
compiled to the processor architecture. More recent works [Hajduk et al. 2015] present
a design and compilation environment for multi-processor architectures, which enable
the authors to translate various forms of IEC 61131-3 control algorithms, either in
the form of executable code to run in the custom processor, or as custom hardware
accelerators, as depicted in Figure 10.
Fig. 10. MPSoC-based PLC architecture targeted to FPGA devices
ACM Computing Surveys, Vol. -, No. -, Article –, Publication date: September 201-.

Enabling adaptable IEC 61499-based cyber-physical systems –:17
Fig. 11. Comparison of various implementations of IEC 61131-3 algorithmis in
This architecture is encompassed by an scalable FPGA-based MPSoC architec-
ture, consisting in a number of individual soft-processors (designed and optimized
for running IEC 61131-3 code though a compilation chain that generates target-
independent virtual machine code), which can include specially designed floating-point
units (FPUs), for intensive and resource costly operations. The platform integrates a
communication interface for configuring the SoC and the various peripherals, which
include a programmable I/O expansion core. SD and SFC code can be mapped to the
various processors, which can work either independently or in coordination to imple-
ment a given application. The processor solution alone has been demonstrated to im-
prove the performance of various control algorithms, such as LD, PID and more com-
plex designs (a fuzzy rule-based system dubbed as P1-TS by the authors) as shown in
Figure 11, when compared to a plethora of PLC-based solutions, even using a single
processor. One of the advantages of the proposed methodology is that lets the designer
to transform complex algorithms into hardware function blocks, which is useful for
accelerating computing intensive functions of the application.
The latter implementation choice, dubbed by the authors as Hardware Function
Blocks (HFBs), are generated much in the same manner as in the methodologies dis-
cussed above (converting IEC 61131-3 software to HDL), but the obtained code is
wrapped to foster re-usability and thus facilitate the integration of complex systems.
The results shown here (in summarized form), and depicted in the last line of the ta-
ble, indicate that the execution times of some computation intensive algorithms can be
significantly shortened, and the use of MPSoCs in this particular context could enable
to carry out various HW/SW co-design strategies and design exploration techniques
if coupled with appropriate profiling tools. It is important to note the this kind of ap-
proaches, as those advocated by the IEC 61499 standard, have been seen by many
researchers as a means to overcome the performance bottleneck in many specialized
domains, since it could help unleash the potential of full-fledged heterogeneous multi-
core architectures for a plethora of applications [Hill and Marty 2008].
Nonetheless, and despite the fact that this MPSoC approach improves significantly
the programmability and encapsulation issues of other pure hardware implementation
of IEC 61131-3 design frameworks (hence promoting the distribution and reconfigura-
tion of the software tasks of a given application), the HFB portions of the architecture
still suffer from the handicaps of the design flows described above: if even a single
hardware task (HFB) is to be modified or relocated, the entire design would need to
pass the entire FPGA design and implementation phases, making more difficult the
verification process as well. Another issue is that these hardware functions need to be
present in the reconfigurable fabric during the the entire application lifetime, increasing
the resource utilization and power consumption in the FPGA. As we will see, the same
problems plague some initial implementations of the IEC 61499 in reconfigurable de-
vices, issues that could be alleviated through partial reconfiguration techniques and
Dynamically Reconfigurable systems on Chip (DRSoCs).
ACM Computing Surveys, Vol. -, No. -, Article –, Publication date: September 201-.

–:18 G. Ochoa-Ruiz
Fig. 12. Incipient FPGA implementations of the IEC 61499 for a) a Resource and a b) Function Block
4.3.2. Initial efforts for implementing FPGA-based IEC 61499 solutions .As with the sys-
tems discussed in the previous section, in recent years there has been an increased
interest in implementing automation and control systems in FPGA, based in the IEC
61499 norm. As we have thoroughly discussed in Section 3, the specification provides
means for modeling DCS, and provides general guidelines on how such systems should
operate to integrate the provisions of the standard. However, the actual implementa-
tion features that the hardware platforms should include have been left out of the norm
[Ferrarini and Veber 2004], as well as other more managerial aspects related to device
and resource managers. The only constraint is that the Functions Blocks should follow
the execution semantics briefly described in Section 3.2, regardless of the underlying
device management services and hardware implementation.
Despite the inherent advantages of reconfigurable devices, very few endeavors have
been carried out in the implementation of IEC 61499 systems, the work of [O’Sullivan
and Heffernan 2010] being the most prominent so far. The authors describe various
custom logic blocks necessary for implementing IEC 61499 applications onto FPGA
circuits. In particular, the authors focus on the implementation of the resources and FB
models using HDL descriptions, which are shown in Figure 12 a) and b), respectively.
The authors provide a thorough description of the implementation of these two mod-
els of the IEC 61499 standard, which encapsulate the basic features of the models as
bus-based hardware accelerators written in HDL and optimized for FPGA implemen-
tation. The resource implementation, depicted in the left side of Figure 12 implements
the communication infrastructure with the device through specialized receiver (RX)
and transmitter (TX) functions blocks, which in tandem with the resource manager,
federate the execution of the underlying function blocks (which may contain one or
several algorithms). The resource manager is also in charge of the polling the pro-
cess interface to detect any incoming data and/or events, which control the behavior
of the algorithms contained in the FB. Similarly, the manager caters for delivering
the results of the algorithms to the controlled process. The I/O signals are accessed
in both instances through specialized circuits known as I/O SIFBs, which are custom
hardware drivers in charge of granting the access to the external FPGA pins.
The resources encapsulate the function block models, which are essentially bus-
wrapped hardware accelerators that implement the basic services required for com-
municating with the high-level manager. As depicted in Figure 12 b), the function
blocks are wrapped by bus-handlers for writing and reading operations by the encom-
passing resource managers, delivering events to be used by the ECC to trigger the
various algorithms encapsulated by the FB.
ACM Computing Surveys, Vol. -, No. -, Article –, Publication date: September 201-.

Enabling adaptable IEC 61499-based cyber-physical systems –:19
The ECC Handler and Algorithm Handler modules in the figure are generated
though a high-level synthesis process in which IEC 61499 algorithmic descriptions
are converted to VHDL, which needs to be integrated in the FB wrapper. The authors
present some interesting results and case studies, but no performance analysis is pro-
vided. Furthermore, the results presented by the authors seem mostly preliminary,
since no provisions are described for the overall management of the device and the en-
compassing resources. Furthermore, the proposed architectures are inherently static,
in the sense that the totality of the original specification is mapped onto the FPGA,
without taking into account the much sought advanced features of the standard (in
particular distribution and reconfiguration).
As with some of the IEC 61131-3 architectures discussed in the previous section,
in order to modify the functionalities within a resource, the FPGA would have to be
completely reconfigured, which betrays the provisions of the IEC 61499 standard. Sec-
ondly, all algorithms must be present in the FB to be triggered by the ECC, incurring in
severe penalties in terms of the occupied resources in the reconfigurable fabric [Ochoa-
Ruiz et al. 2012b], much in the same manner as HFBs in the MPSoC architecture
described before [Hajduk et al. 2015].
Furthermore, the proposed interfaces and constituent sub-components need to un-
dergo a standardization process or at least be agreed upon by the community at large,
in order to promote IP reuse and exchange within the automation community, if the
efforts presented in these works are to have any lasting impact. These standardization
efforts have of course a long history in SoC design, with have slowly coalesced into a
handful of major bus architectures and interfaces, used today in the development of
many complex systems, both using ASICs and FPGAs.
As we will see in the next section, many of these standardization efforts have un-
dergone several developments within reconfigurable computing community for some
time [Hsiung et al. 2009], with the introduction of various SoC-based architectures
and standard hardware accelerators. In particular, many efforts have been carried out
to harmonize various research efforts to render such platforms more dynamic through
the introduction of partial reconfiguration techniques, which enable to modify compo-
nents of the architecture at run-time and on-demand. Many of these efforts share many
commonalities with the previsions of the IEC 61499 standard, and many works have
tackled the modeling, implementation and management of reconfigurable and dis-
tributable hardware accelerators, which is slowly coalescing into standards for DRSoC
hardware blocks [Navas et al. 2013b]. However, before proceeding, we will summarize
the main findings with regard with the limitations of current FPGA-based automation
solutions, and what can be gained through the introduction of partial reconfiguration
in this context.
4.4. Summary and comparison on IEC 61131-3 and IEC 61499 implementations
In the previous sections, we have discussed some incipient endeavors for implement-
ing control and various automation platforms in FPGA devices. Special emphasis has
been invested in developing fast-prototyping methodologies based on HLS techniques
for mapping the various languages used as basis for both the IEC 61131-3 and IEC
61499 norms. Some of the first endeavors in this regard have mapped the entirety of
an algorithmic implementation onto a reconfigurable device, leading to poor encapsu-
lation and reuse capabilities, as thoroughly discussed. Some other efforts have looked
to capitalize the developments made by the MPSoC community and proposed platform-
specific FPGA-based MPSoC PLCs [Ahmed et al. 2010]; such propositions improve the
degree of configurability and reuse, but still suffer of a lack of programmability, dis-
tribution, and reconfiguration regarding the hardware-accelerated components of the
described applications.
ACM Computing Surveys, Vol. -, No. -, Article –, Publication date: September 201-.

–:20 G. Ochoa-Ruiz
Fig. 13. Qualitative comparison between the two main automation languages and competing design tools
In what follows, we will attempt at making a brief qualitative comparison and sum-
mary of the existing implementations of automation systems based on the IEC norms,
based on the metrics in the first column of 13
—a) Configurability and interoperability: Software-based implementations of the
IEC norms found in the literature foster these features through software configura-
bility and standards. Some of the FPGA-based efforts discussed above achieve these
capabilities through the use of HLS techniques, thus making their programming
more transparent to the user. However, a more wide-ranging and holistic approach
based on the MDE paradigm is necessary to harmonize many of these efforts, as
widely recognized by many experts in the domain [Strasser et al. 2009].
—(b) Reconfiguration and distribution: Traditional, MCU-based implementations
of the IEC standards attain high degrees of programmability and thus, reconfigura-
tion and distribution of the atomic components of the underlying applications. On the
other hand, the FPGA-based platforms described in the two previous sections do not
support such features in their current form for the FBs implemented as hardware
components: as we will see in the next section, partial reconfiguration could help to
overcome these limitations.
—(c) Algorithmic Performance and Heterogeneous Processing Capabilities:
Implementing certain sections or componets of the application as hardware accel-
erators can have a signficant impact of the performance of the overall application,
expediting many otherwise time-consuming processes, as well as being able to han-
dle a larger number of events and I/Os concurrently.
—(d) Encapsulation and reuse: The initial FPGA-based efforts discussed above did
not foster encapsulation and reuse of control functions: they target the entirety of the
FPGA. Newer architectures make a better work by encapsulating FBs as software
components and hardware accelerators in a larger MPSoC architecture, fostering
reuse and HW/SW co-design strategies.
—(f) Device Scheduling and Management: Pure software implementations of the
IEC norms are mature enough, and a great deal of research has been carried out
regarding the management of applications running in MCU-based automation sys-
tems. This is less true in FPGA-based implementations, especially those based on the
IEC 61499 standard, which are still very incipient.
Despite the limitations of FPGA-based implementations discussed in this section,
such component-based frameworks can serve as a stepping stone in the creation of full-
fledged IEC 61499 systems. For this convergence to occur, these architectures and code
generation approaches need to be complemented with state of the art design tools for
implementing DRSoC platforms and dynamically reconfigurable hardware accelera-
tors [Navas et al. 2013a]. In the section that follows, we will introduce such concepts,
which as we will see, are strikingly close to those sought by the IEC 61499 standard.
ACM Computing Surveys, Vol. -, No. -, Article –, Publication date: September 201-.

Enabling adaptable IEC 61499-based cyber-physical systems –:21
5. IMPLEMENTING IEC 61499-BASED RECONFIGURABLE SYSTEMS IN FPGA-BASED SOCS:
OPPORTUNITIES AND CHALLENGES
We believe that the research in reconfigurable computing, and in particular many PR
features can have a positive impact in the development of full-fledged IEC 61499 plat-
forms, first as a common ground for the research community in the latter domain,
and subsequently for more industrial grade applications as the current limitations in
the language provisions are overcome. We will explore some of the benefits of bring-
ing these two domains together in this section, the current limitations, and some of
the challenges that need to be addressed methodologically and in terms of the current
tools to make this possible. The next section will then provide ample evidence of recent
strides in this front by the reconfigurable computing community in this regard, and
how these developments could help in attaining these goals.
5.1. Partial reconfiguration of FPGA devices: concepts and tools
Partial reconfiguration was introduced originally as means to increase the flexibility
of FPGA-based applications, and was initially geared towards enabling the designers
to modify small sections of the reconfigurable fabric, in a software-defined manner.
However, these initial implementations were rather limited since they only enabled to
swap soft IPs in and out the reconfigurable fabric with relatively large granularities,
and furthermore, several technological and tool limitations hindered its application to
more complex scenarios. Despite these disadvantages, a great deal of research has been
carried out to promote the development of FPGA-based Systems on Chip which exploit
the inherent advantages of software-defined partial reconfiguration [Ochoa-Ruiz et al.
2015]. This term implies that a management unit in the SoC (typically a soft processor,
but other hard processors have been used) can adapt sections of the SoC (i.e. typically
hardware accelerators in the form of peripherals or specialized functions) depending
on internal or external factors.
These efforts are very much aligned to those in reconfigurable computing for wrap-
ping functions in PLB or AXI interfaces, for static hardware accelerators [Ochoa-Ruiz
et al. 2012b]. A prototypical hardware accelerator for a basic FPGA-based SoC is de-
picted in Figure 14; as with the Hardware Accelerators described in Section 4.3 (for
implementing IEC 61131-3 algorithms hardware function blocks and IEC 61499 func-
tions blocks, respectively), most FPGA-based accelerators are encompassed by very sim-
ilar building blocks [Kirschberger et al. 2014].
Nowadays, most FPGA vendors provide means for interconnecting user defined logic
(i.e., the hardware accelerator, which can be written manually or generated through
HLS techniques or other means) to the bus interfaces, both for transmitting data and
commands to the underlying peripheral using the HW/SW interface and for retrieving
the results of the computation through the read interface.
Fig. 14. A prototypical implementation of a hardware accelerator in an FPGA-based SoC
ACM Computing Surveys, Vol. -, No. -, Article –, Publication date: September 201-.

–:22 G. Ochoa-Ruiz
Fig. 15. Dynamic partial reconfiguration basic concepts and process
As with those efforts discussed before, the hardware accelerator also requires of some
form of management unit, typically in the form of a command decoder and state ma-
chine for federating the life-cycle of the hardware task, and which strongly resembles
the Execution Control Chart of the FB in the IEC 61499 standard. Similarly, external
signals and events (i.e. hardware interrupts) can also be used by the IP block through
a GPIO interface for interacting with the outside world, much as in the same manner
of the process interface described in the IEC 61499 standard.
As it can be inferred from this succinct introduction, many overlapping concerns
exist between the aforementioned efforts and those discussed in Section 4.3, but the
use of partial reconfiguration has enabled to introduce features currently lacking in
those static implementations, namely the reconfiguration and distribution of hardware
accelerators into different zones of the FPGA.
The main rationale of PR is the ability to modify specific areas of the FPGA at run-
time, on-demand [Xilinx 2012], and in a quasi glitch-less manner, as depicted in Figure
15. For this, the designer needs to specify the zones of the reconfigurable fabric that
will be dynamically modified (known as PRRs, for Partial Reconfigurable Regions);
then, a set of hardware IPs are allocated to these PRRs (known as PRMs, for PR
Modules). Compared with the traditional approach, various HW tasks can be time-
multiplexed for sharing the same physical resources, avoiding many of the pitfalls of
the architectures discussed above [Gawali and Sharma 2009].
Several approaches for defining the reconfigurable areas have been proposed, falling
in two main camps: the reconfigurable module can either integrate the bus-wrapped
hardware accelerator and the accompanying modules (Figure 14) or in a second in-
stance, only the hardware accelerator is modified through partial reconfiguration. This
choice has some major implications, since the assigned logic blocks are subsequently
transformed into partial bitstreams, which configure the PRRs on demand at run-time,
in order to map the desired functionalities onto the FPGA, as depicted in the figure.
The larger the number of resources encompassing the PRM, the larger the configu-
ration process will take, and issue that can introduce timing penalties and affect the
overall system performance. Nonetheless, the added flexibility more than compensates
for this drawback in most applications: those architectures described in Sections 4.3.1
and 4.3.2 would require a complete reconfiguration of the FPGA, which will halt the
operation of the system during a significantly larger fraction of time.
The reconfiguration process requires some additional components to work. A mini-
mally functional DPR system is encompassed by a reconfiguration controller (RC), in
the form of an internal or external processor, to retrieve the generated partial bit-
streams from external memory (i.e., Flash or DDR can be used depending on the ap-
plication) and to drive an special internal port (the ICAP), through which the recon-
ACM Computing Surveys, Vol. -, No. -, Article –, Publication date: September 201-.

Enabling adaptable IEC 61499-based cyber-physical systems –:23
figuration process is carried out. Such minimal system can be used for other purposes
than coordinating the partial reconfiguration process, taking more on some manage-
rial role, much in the same manner as the IEC 61499 systems discussed in Section
3.3. Such systems have had successful applications in applications such as software-
defined radio [Delahaye et al. 2007] and in video processing applications [Manet et al.
2008], among others.
Despite the strides made in the partial reconfiguration domain, the academic com-
munity and many system designers have long sought to develop systems in which the
underlying reconfigurable resources can be treated in a transparent manner, just as
simple threads in a traditional CPU-based design. Such mechanisms could provide a
virtualization layer of the hardware platform [Brebner 1997], by swapping functional-
ities in and out of the reconfigurable fabric, at run-time and on-demand. Such features
have been considered essential in order enhance the flexibility of FPGA-based appli-
cations, executing heterogeneous hardware tasks by time-multiplexing the access to
predefined physical resources. Additionally, these capabilities could permit the already
deployed systems to adapt to environmental or internal conditions, by modifying their
original configuration to perform a new mission or in self-healing scenarios [Beckhoff
et al. 2014].
Implementing such systems beyond simple case studies is however not trivial, as will
discuss in the next sub-section. We want to provide the reader with a glimpse of the
complexities associated with the tools, and the expertise originally required for success-
fully implementing Dynamically Reconfigurable Systems on Chip (DRSoC) using the
traditional DPR design tool flow. This will provide a framework for the discussion that
follows, which intends to demonstrate that new developments in the DPR domain are
mature enough to be effectively used in the implementation of the DRSoC architec-
tures necessary for successfully creating full-fledged IEC 61499 platforms.
5.2. Using DRSOC for implementing IEC 61499 platforms: advantages and opportunities
As depicted in Figure 16, a complete IEC 61499 device on a chip could easily be im-
plemented in a reconfigurable device. A central processor (either a soft-processor or as
in more advanced devices based on ARM cores) can cater for the device management,
making use of an RTOS executive. A common virtual bus could be defined and imple-
mented in FPGA, either via conventional bus protocols or through tailored PR buses
[Koch et al. 2008], fostering the development of component-based approaches for IEC
61499 FBs and promoting IP reuse. Moreover, the PR aspects discussed above could aid
in the development of full-fledged IEC 61499-based platforms, with increased adapt-
able heterogeneity. In the following, we briefly discuss some other potential benefits
that could be attained through the deployment of DRSoCs in this regard:
—(a) Configurability and interoperability: Using specialized IP wrapping tech-
niques, in tandem with some of the code generation methods discussed in Section 4.3,
could lead to better configurability of a DRSoC-based IEC 61499 devices, if matched
with an holistic model-driven engineering approach [Ochoa-Ruiz et al. 2015]. Such
efforts can also have a positive impact in interoperability as well, since the original
specification would consist in some of the languages defined by the IEC, and the code
generation methods would shield the designer of the technological specific details.
—(b) Attaining full-fledged reconfiguration and distribution: Many PLC-like
implementations in FPGA devices do not support full-fledged reconfiguration of the
control functions implemented in hardware, or distribution of the constituent tasks.
These issues can be solved by using the architectures and techniques discussed in
Section 6.2, to enable full-fledged IEC 61499 DCS platforms.
ACM Computing Surveys, Vol. -, No. -, Article –, Publication date: September 201-.

–:24 G. Ochoa-Ruiz
Fig. 16. A conceptual architecture for reconfigurable systems based on DRSoC
—(c) Increased performance through FPGA implementation: Implementing
control algorithms in FPGA can significantly improve their performance, as thor-
oughly discussed in Section 4.3. Such algorithms could be implemented as complex
FBs catered by a battery of resource managers (i.e., wrappers) allocated to a recon-
figurable regions in the FPGA (i.e.resources), interconnected via a standardized com-
munication interface. The algorithms could then be dynamically distributed using a
RecOS and the associated services (task relocation and context management).
—(d) Encapsulation, reuse and virtualization: Hardware tasks can co-exist with
other threads run by the RecOS: they can be swapped in and out of the reconfig-
urable logic, pre-empted by other processes and reinserted when necessary, or even
relocated. The RTE hypervisor caters for the context-management duties, simplify-
ing the application development and making the entire process transparent to the
user, and the specification more maintainable and easy to port and upgrade.
—(e) Mixing heterogeneous processing policies: In order to keep pace with the
stringent real-time constraints of complex control systems, heterogeneous automa-
tion FPGA-based platforms (using either hardened or software implementations of a
FB, or a combination of both), could enable extensive design exploration strategies,
so the best possible compromise in terms of performance, power consumption, and
area/resource utilization, among others policies can be met.
Another advantages of using FPGA devices for implementing control systems, and
which could have a significant impact in the implementation of IED are the following
—(f) Device specialization and support of multiple communication field-bus
protocols: The support for multiple fieldbus protocols in IEDs is an active area of
research, but most approaches concentrate on multi-protocol devices, that permit to
harmonize the ensemble of the DCS network. The use of partial reconfiguration could
permit the creation of customized IEDs, which can be tailored for a given application
or network configuration, for supporting a given industrial protocol.
—(e) Fault-tolerance diagnosis/prognosis: Monitoring and infotronics mechanisms
can be embedded within IEDs, which in tandem with device-to-business loops can
help in assessment and prediction of unacceptable behaviors (due to degradation,
as well as alterations introduced by faults). Many of such approaches have already
been investigated in the reconfigurable computing domain, in applications such as
hot spot mitigation, which enables to extend the lifetime of the devices. Moreover,
this prognosis approach enables to move beyond the traditional ’fail and fix’ practices
to ’predict and prevent’ approaches [Hammouda et al. 2014]
ACM Computing Surveys, Vol. -, No. -, Article –, Publication date: September 201-.

Enabling adaptable IEC 61499-based cyber-physical systems –:25
5.3. The partial reconfiguration design flow and its limitations
Partial reconfiguration as a concept has been around for some years [McDonald 2008],
but few vendors offer the tools and have the technological capacities to implement
full-fledged PR designs. The most studied and utilized methodology for implementing
DRSoCs has been developed by Xilinx [Xilinx 2012], and many methodologies, design
tools, as well as specialized circuits and tailored techniques have been created around
Xilinx tools and devices [Beckhoff et al. 2014].
The design flow differs significantly from the standard techniques used for creating
conventional (i.e., static, single context) FPGA-based designs, since it requires the use
of a HW/SW co-design phase, as well as significant knowledge of the low-level tech-
nological aspects, which are often device-specific and require a great deal of expertise
and the use of several toos, as depicted in Figure 17
The creation of PR systems is a complex process that requires a thorough planning
from the very beginning [Ochoa-Ruiz et al. 2015], at the platform specification stage.
The design methodology centers on identifying and designing a set of dynamically
reconfigurable partitions, which are the potentially reconfigurable areas of the over-
all reconfigurable platform. This system specification is performed using a top-level
VHDL description, created through a tool such as Xilinx ISE.
First, the designer or system architect must synthesize the static and reconfigurable
modules HDL descriptions (b) following strict guidelines (especially regarding the mod-
ules interfaces). Additionally, knowledge on processor-based development is also re-
quired, which entails using other tools (i.e., for hardware/software co-design purposes),
adding to the complexity of the entire endeavor.
Similarly, the third phase of the PR design process, in which the platform is floor-
planned and generated using PlanAhead (c), requires as well a great deal of expertise.
Firstly, an expert in FPGA post-synthesis must provide constraints for I/Os in the
design, and timing constraints for many of the signals; constraints for placing the
static and partially reconfigurable regions need also to be specified.
After the static and partial bitstreams are obtained using PlanAhead, a run-time
environment for controlling the reconfiguration process must be created. The develop-
ment of processor-based FPGA platforms is facilitated by the use of the Embedded
Development Kit (such as Platform Studio or more recently, Vivado) (d).
Fig. 17. Dynamic Partial Reconfiguration design flow and the required expertise
ACM Computing Surveys, Vol. -, No. -, Article –, Publication date: September 201-.

–:26 G. Ochoa-Ruiz
This tool is used for creating the hardware platform, whilst an SDK is employed for
developing code for the target processor, as shown in the figure. The software devel-
oper can then create an application, taking into account the reconfiguration control
logic [Guillet et al. 2014], with precise knowledge about the various IP functionalities
and APIs. This function can be a simple control software that interacts with the appli-
cation through the I/O subsystem and other hardware and software components, or a
more sophisticated operating system in charge of the entire application and reconfigu-
ration management, much in the same spirit of the device manager of the IEC 61499
specification, as we will see in Section 6.3.
After the DPR system has been created using PlanAhead, the configuration bit-
stream can then be combined with the application configuration executable, generating
a complete system bitstream. This bitstream is to reside in non-volatile memory for
configuring the FPGA at power-up, along the partial-bitstreams [Neuendorffer 2010]
to be charged by the reconfiguration manager at run time. Thus, once the FPGA has
been configured, the partial bitstreams can be loaded onto the reconfigurable regions
on demand, depending of the intended application scenarios. The control logic needs to
be carefully validated in order to guarantee the correctness and safeness of the recon-
figuration process, which complexity grows as the number of possible configurations
increases, which demand proper verification methodologies (e).
Despite the complexities inherent to such an intricate design flow, a great deal of
research has been carried out within the reconfigurable computing community, and
many successful applications and new avenues of research have emerged around this
topic. Nonetheless, it is widely accepted that the required level of expertise for im-
plementing PR systems and more in general, DRSOCs, has hampered their adoption
beyond some niche applications. This issue also stems from the complexity associated
to FPGA programming [Bacon et al. 2013] and their deployment by non-experts.
These problems have been tackled by both FPGA vendors and by the reconfigurable
computing community at large, in several fronts, as briefly discussed in Section 4.2:
improving IP reuse for HW/SW co-design [Sangiovanni-Vincentelli 2007], making use
of High-level Synthesis techniques [Coussy et al. 2011] for closing the technological gap
and facilitate the implementation of domain-specific algorithms onto programmable
logic, and lately, though model-driven engineering (MDE) techniques to provide a more
holistic approach to underpin the entire endeavor [Ochoa-Ruiz et al. 2015].
However, other aspects hampering the adoption of PR, as well as hindering to un-
leash its full potential, are related to methodological and tool-dependent aspects, but
also to technological constraints imposed by the FPGA vendors: the traditional PR
design flow does not support some of the much sought features of DRSoC platforms,
such as the capability to distribute or reallocate a hardware tasks onto any available
area (i.e. reconfigurable region). Such capability is of the utmost importance in order
to support many of the features discussed in Section 5.2 and thus, many researchers
have envisaged methods to circumvent such limitations by deploying techniques such
as bitstream modification, and developing more advanced tools, to be revised in the
next section.
We argue later in this subsequent section that such tools and techniques, developed
within the reconfigurable computing community, in tandem with appropriate code gen-
eration approaches and other more holistic paradigms such as Model-driven engineer-
ing (MDE) could be used to successfully implement usable, scalable and open IEC
61499-based platforms. However, such endeavors need to be accompanied by the devel-
opment of sophisticated and highly adaptable hardware platforms, capable of support-
ing multiple network protocols. Some efforts in this regard have been already carried
out, with open and scalable FPGA-based platforms such as the NetFPGA [Zilberman
et al. 2014] or the FlexTiles [Janssen et al. 2015] introduced in recent years.
ACM Computing Surveys, Vol. -, No. -, Article –, Publication date: September 201-.

Enabling adaptable IEC 61499-based cyber-physical systems –:27
6. RECENT TRENDS IN THE IMPLEMENTATION OF DRSOCS
A great deal of research has been made to facilitate the design process of DRSoC plat-
forms, both within the reconfigurable computing community [Lavin et al. 2011], and by
researchers working in the model-driven engineering domain (MDE, see for instance
[Ochoa-Ruiz et al. 2012a]). A survey of the former efforts will be provided in this sec-
tion, while a discussion on MDE endeavors FPGA-based SoCs can be find in [Ochoa-
Ruiz et al. 2015]. More recent work discusses the use of model-based design for the
specification of DRSoC-based applications [Ochoa-Ruiz et al. 2015].
The description provided here is rather synoptic; for a more in-depth discussion,
excellent surveys of some of the initial efforts in DPR [Garcia et al. 2006], and of recent
more developments [Beckhoff et al. 2014] are readily available. We will concentrate
our discussion on those aspects we deem essential for building a bridge between the
efforts carried within the reconfigurable computing domain, and the opportunities for
implementing IEC 61499 systems in reconfigurable devices discussed in Section 3.4.
First, we will revise some initial efforts to enable the distribution of tasks in DR-
SoCs, through a process known as bitstream relocation, which can be seen as an exten-
sion to the current Xilinx PR design flow. Subsequently, we will discuss how some CAD
tools have overcome many of the issues those initial approaches sought to solve, fur-
ther extending the capabilities of PR, while reducing the design effort in the process.
We posit that such tools could be harnessed to implement the necessary infrastruc-
ture to support the reconfiguration and distribution of software and hardware tasks
into mutitple IEC 61499 devices, overcoming the issues of previous FPGA-based IEC
implementations.
Afterwards, we will discuss yet another aspect of the design of DRSoC-based plat-
forms, which is concerned with the management of the reconfiguration process, which
entails not only allocating tasks into predefined physical areas, but taking into account
aspects such as life-cycle of a given task, the availability of a reconfigurable region, and
avoiding any potential conflicts [Compton and DeHon 2007]. These issues are also of
interest for the implementation of usable IEC 61499 based systems, in which aspects
related to the management of devices and resources have been largely unexplored, both
in microprocessor and FPGA-based implementations of the norm.
6.1. Bitstream relocation for improved task distribution and management
In a DRSoC platform, pre-established portions of a hardware platform (known as re-
configurable regions) can be changed on-demand, using partial bitstreams (PBs) that
map the functionalities of a given task onto the available resources. This entails that
this configuration data cannot be deployed in other resources within the device and for
configuring other devices. This limitation of the traditional design flow has long been
considered as a serious obstacle to the implementation of full-fledged reconfigurable
systems, since the generated PBs are bounded to such predefined PRRs.
Therefore, the PB cannot be deployed for configuring reconfigurable logic in a dif-
ferent location, even if the underlying layouts are identical. This limitation has some
significant implications: the required amount memory augments if multiple copies of
a task are needed (for instance, for scalable architectures) [Touiza et al. 2013] and
furthermore, hampers the relocation or distribution of tasks that is required in many
applications (i.e., hot-spot mitigation, fault-tolerant systems).
In order to alleviate some of these issues, and to increase the flexibility of DRSoCs,
a method known as Partial Bitstream Relocation, PBR) was originally proposed. Most
of the works in the literature (see Figure 18) rely on modifications upon the partial bit-
streams obtained from the traditional PR design flow, either by software or by custom
hardware accelerators (known as relocators, for instance BIRF [Corbetta et al. 2009]).
ACM Computing Surveys, Vol. -, No. -, Article –, Publication date: September 201-.

–:28 G. Ochoa-Ruiz
Fig. 18. Comparison of methods for bitstream relocation, adapted and extended from [Touiza et al. 2013]
The basic principle underpinning these methods is to manipulate and transform the
PB as depicted in Figure 19, typically online, in order to relocate the configuration
data onto a different zone. Configuration data is bounded to positions in the FPGA
configuration memory: by modifying certain pieces of data, a PB can be mapped onto
various zones. At run time, the configuration partial bitstreams are retrieved from
memory or sent by a remote configuration manager (1) and stored externally or using
internal memory (2), or directly retrieved from the PRR configuration data (3) through
a process known as read-back.
This process only works if certain conditions are met, specifically regarding the lay-
out of the PRR and if the static signals do not introduce conflicts with the routing of
PRMs [Ochoa-Ruiz et al. 2013]. In this regard, some approaches have enabled to map
a partial bitstream between PRRs with different layouts, a process that entails an
awareness of the characteristics of both the source and destination PRRs, since some
complex calculations and manipulation upon the bitstream have to be performed by
the relocator module, as implemented in Replica [Kalte and Porrmann 2005], which
additionally is in charge of driving the ICAP module.
A major hurdle in most of these approaches was that, since they were based on the
traditional PR design flow, the use of the so-called bus macros was a necessity. This
static interface infrastructure was difficult to use and prone to errors, with the addi-
tional drawback of consuming significant additional resources [Beckhoff et al. 2014].
This issue was subsequently solved with the introduction of proxy logic interfacing,
which in addition to consuming less resources, was introduced automatically by the
tools. Finally, most PBR approaches supported relatively simple layouts for the PRRs
configurations, either as a single or multiple square islands in the reconfigurable fab-
ric, or as slots in a bus-based architecture. In many cases, these design choices stemmed
from limitations in the deployed place and route strategies, which did not enable more
complex geometries and interconnection infrastructures [Wold et al. 2014]. As we will
see in the next sub-section, these issues have been largely tackled by new tools and
methods, paving the way to more sophisticated DRSoC platforms.
Fig. 19. The rationale for bitstream relocation in DRSoC platorms and main concepts
ACM Computing Surveys, Vol. -, No. -, Article –, Publication date: September 201-.

Enabling adaptable IEC 61499-based cyber-physical systems –:29
6.2. Recent developments in tools for partial reconfiguration
Many of the advances dicussed in the previous section have fostered new areas of
research, such as in Fault Tolerant Systems [Montminy et al. 2007] and in Hot Spot
Mitigation [Gupte and Jones 2009] to cite but a few, where the ability relocate tasks is
considered essential. However, such approaches for PBR have some serious handicaps,
the most prominent being that they are too dependent on architectural and design flow
decisions, making the portability and the reuse of the solutions rather difficult.
This issue has been recognized by the community at large, which have made strides
in the development of design tools to facilitate the design process of PBR-capable recon-
figurable systems. In order to circumvent the above mentioned issues, such design tools
need to access low-level FPGA primitives such as LUTs, FFs, and switch matrix mul-
tiplexers [Beckhoff et al. 2014], which cannot be directly manipulated using hardware
description languages such as Verilog or VHDL.
Therefore, several design tools, such as RapidSmith [Lavin et al. 2011], have ex-
ploited an intermediate design descriptions, such as the Xilinx Description Language
(XDL), which offers a readable and manipulable description of low-level netlists, en-
abling the designer a greater control over the mapping and place and route stages
of the FPGA design process. This increased control on the placement and routing of
reconfigurable modules has the additional benefit of creating more resource-efficient
DRSoCs [Ochoa-Ruiz et al. 2017].
A great deal of research and tool development, based on the original propositions of
RapidSmith has been carried out, with increased levels of sophistication and easy-of-
use. Due to space considerations, we will just briefly describe some of the most promi-
nent features of such tools, summarized in Figure 20, to showcase the progresses made
in the domain; for a more detailed account of the evolution of the such tools, excellent
sources exist [Koch et al. 2012].
Some initial endeavors were represented by the DAPR [Yousuf and Gordon-Ross
2010] and OpenPR [Sohanghpurwala et al. 2011] design flows. Although interesting
in their inception, they had several issues, which stemmed mainly from their use of
bus macros for interfacing the RMs with the static design. This characteristic severely
limited their use in PBR-capable designs, since the former does not support reloca-
tion (it is basically an extension to the capabilities of PlanAhead), whereas the latter
supports distribution of tasks only between PRR with identical layouts. Moreover, the
implementation of PR platforms with such tools was deemed very time-consuming.
More recent tools have circumvented various drawbacks of the of the approaches
described above. For one, tools such as Dreams [Otero et al. 2012] and Reshape [Neely
et al. 2013] provide streamlined methods for floor-planning the PRRs, independent
from the cumbersome front-end provided by PlanAhead.
Additionally, these tools avoid resource consuming interfacing methods such as bus
macros, favoring proxy logic or partition pins, which are more latency-efficient and are
automatically inferred and inserted.
Fig. 20. Comparison of various extended DPR design tools adapted and extended from [Beckhoff et al. 2014]
ACM Computing Surveys, Vol. -, No. -, Article –, Publication date: September 201-.

–:30 G. Ochoa-Ruiz
These approaches enable as well complex PRR geometries (slot and grid-based sys-
tems are possible). However, only the former tool supports PBR, albeit with the lim-
itation of restricting the PRRs identical shapes and underlying resources (i.e., same
layout).
All the above tools suffer as well of relatively long compilation times (for the synthe-
sis of the module netlists, a curse in most FPGA-based design tools), exacerbated by
the time overhead incurred by the generation of the PR static and partial bitstreams,
which stems from the multiples passages through the design flow to avoid any routing
conflicts among the various static and partial bitstream configurations.
Many of these issues have been solved by new tools, in particular GoAhead [Beck-
hoff et al. 2014], which couples a floor-planning front-end with a battery of automated
scripts. Some features of the tool are the generation of constraints for the underly-
ing implementation tools (i.e., mapping, P&R), HDL code generation (of templates and
interfaces) and support for various static-PRR interfaces choices (BM, PL and the so-
called zero logic, which incurs in very low resource overhead).
Furthermore, various PRR layout types and relocation methods are supported.
These capabilities are possible due to the communication infrastructure upon which
GoAhead is based, ReCoBus (a homogeneously structured hard macro) [Koch et al.
2008]. This infrastructure enables a very fine-grained placement of modules, and im-
poses less restrictions on the relocation of tasks, which are not limited to the size of
the PRR nor the underlying physical resources. This approach has an additional ben-
efit: the PRRs do not need to be over-specified, a major hurdle in the vast majority of
approaches to DPR design [Marques et al. 2014].
Moreover, the tools described above have fostered the use of ESL techniques for the
creation of DRSoC [Ochoa-Ruiz et al. 2015], raising the level of abstraction. Further,
they have made the reconfiguration process more flexible and transparent, by shielding
the budgeting of resources and relocation of tasks from the designer.
6.3. Reconfiguration management and tasks relocation and reconfiguration in DRSoCs
The progresses in CAD tools for creating DRSoC platforms described in the previous
section have unleashed many possibilities in system design, since they have enabled
researchers to express and conceptualize on-demand hardware adaptability in a more
high-level manner, without the burden of being preoccupied with low-level implemen-
tation aspects inherent to the technology. Nonetheless, a PR platform only becomes
truly a dynamically reconfigurable SoC (DRSoC) through the use of an embedded re-
configuration management executive and a sufficient level of virtualization. The latter
is required to in order to make the management of the PRMs and their allocation onto
the reconfigurable resources less daunting from an application development perspec-
tive [Guillet et al. 2014]. In this manner, the hardware modules are no longer merely
static circuits performing a given function, but become resources that can be exploited
by the application (along traditional software functions) through a simplified program-
ming model [L ¨
ubbers and Platzner 2009].
In order to accomplish these lofty goals, the system management executive needs to
be conceived in a manner that goes beyond the relatively simple reconfiguration con-
troller outlined in Section 5.1, providing more OS-like capabilities to support features
such as task preemption, context management, relocation, and scheduling. In contrast
to software-based OS, the context of the hardware threads is not only stored in a mem-
ory stack, but some of the internal variables are located within logic resources used to
implement the module [Mignolet et al. 2003], and needs to be taken care of if the task
is to be preempted by another thread with a higher priority. This process, managed by
an augmented reconfiguration controller, is to be analyzed in the next section.
ACM Computing Surveys, Vol. -, No. -, Article –, Publication date: September 201-.

Enabling adaptable IEC 61499-based cyber-physical systems –:31
Fig. 21. Reconfiguration management for DRSoCs in tandem with relocation and context-management
6.3.1. Reconfiguration management of partially reconfigurable systems.A number of re-
search efforts have been undertaken during the last decade to build more flexible DR-
SoCs, with especial emphasis on the proposal of novel reconfigurable OSes (RecOS
henceforth) underpinning it all. The term of reconfigurable OS essentially refers to an
hypervisor augmented with services to manage the underlying reconfigurable areas
and execute functions on it [Iturbe et al. 2013], providing means for the management
of software and hardware tasks, as well as the access to the underlying hardware re-
sources (i.e., memory and PRRs, respectively).
The execution of the application and the implementation of the partial reconfigu-
ration process can follow different policies, enforced by the so-called Reconfiguration
controller, as depicted in Figure 21. Typically, the internal system configuration can be
modified (at run-time) depending on the arrival of external events a (i.e. a change of
format in a video chain), internal application dynamics (a task is to be preempted by
another) or for instance, to recover from unexpected faults. In the same manner, the RC
can also map an empty bitstream whenever a function is no longer needed, effectively
releasing the occupied resources and fostering power management strategies.
In basic PR systems, this configuration management function b can be as simple as
astate machine written by hand or a relatively complex management software running
on a processor. As discussed in Section 5.1, the basic role of the RC is dispatching the
partial bitstream for mapping the new functionality c . This entails taking control of
the ICAP controller, transmitting the reconfiguration data for a given reconfigurable
area, and retrieving the configuration bitstreams from external memory d .
In the vast majority of traditional DRSoC designs, the reconfiguration controllers
were only capable of mapping of non-relocatable bitstreams onto predefined reconfig-
urable regions. The main role of the RC was to coordinate the interaction between
the intended application and catering the correct reconfiguration management [Guil-
let et al. 2014], letting the tasks execution undisturbed if changes were not required e .
Conversely, a new task can be allocated a predefined region f when necessary, until
the completion of an application loop g .
This process was carried out without taking into account the internal state of the
task, this is, even if some thread was running before preempting it. This is due to the
fact that was usually assumed that a task is not to be resumed, and this its internal
context and location within the fabric were not taken care of. As mentioned previously,
such an approach severely limits the kind of applications thaat can be tackled with
DRSoCs and thus may endeavors have introduced context management capabilities
into the RC to support OS-like management of reconfigurable hardware tasks.
ACM Computing Surveys, Vol. -, No. -, Article –, Publication date: September 201-.

–:32 G. Ochoa-Ruiz
Fig. 22. Comparison of reconfiguration management and RecOes, extended from [Ochoa-Ruiz et al. 2017]
Nowadays, the vast majority of RecOSes provide software APIs for handling the
hardware and software tasks and support relocation of the former, using existing mech-
anisms in standard RTOSes [Ochoa-Ruiz et al. 2017]. The rational for this approach
is to take advantage of the scheduling algorithms integrated into the RTOSes, with
the additional benefits of of exploiting the HW/SW interface as a means of communi-
cation with the running processes, as well as fostering IP reuse through the use of bus
wrappers, as depicted in Figure 22.
In order to support context-management capabilities, the RC needs to be able to
interact with the underlying harware modules, in order to monitor their status (i.e.
whether or not it can be preempted), as well as to control their life-cycle, through com-
mands issued by the RecOS. Moreover, the RC also needs to be able to inject and re-
trieve the context h of the tasks during a removal or insertion operation (depending on
the availability of PRRs in the reconfigurable zone of the FPGA i ), an operation car-
ried out by the context allocation manager j . The communication with the hardware
tasks in achieved though the a virtualization layer provided by the HW/SW interface
of specialized context-management wrappers, which serve as the gateway between the
high-level RecOS and the reconfigurable regions and the allocated tasks.
As partial bitstreams (PBs) can be relocated to any available PRR, the tasks must
be correctly identified as to avoid any errors during the re-injection of a task with a
given context k . Hence, the RC requires an increased awareness of the state of the
reconfigurable section of the FPGA (in terms of which areas are occupied or not, and
with which contexts, which is aided by the use of an allocation table k ). These ele-
ments help the RC to manage the complexity of the underlying hardware resources,
allocating only a new context when necessary m , or otherwise inserting the original
context along the correct partial bitstream.
Several RecOSes implementations have been proposed in recent years, such as
OS4RS [Mignolet et al. 2003], ReconOS [L ¨
ubbers and Platzner 2009], RAMPSoCVM
[G¨
ohringer et al. 2011], and more recently R3TOS [Iturbe et al. 2013] and CODEZERO
[Jain et al. 2014]. A good overview of this area can be found in the last two references
(summarized in Figure 22). These approaches have progressively enabled, due to ad-
vances in PR tools, an increasing sophistication in the management of full-fledged DR-
SoCs, implementing many of the capabilities and characteristics sought by the device
management provisions of the IEC 61499 standard (Figure 6,Section 3.3).
These developments are very much aligned with what some researchers within the
automation community have proposed in recent years: using RTOSes as a means to
implement the run-time environment (RTE) for IEC 61499-based devices [Doukas and
Thramboulidis 2011]. This research points at the need of virtualizing the communica-
tion between the RTE and the various resources in a device, so that the control engi-
neers can develop applications for a neutral platform, leaving the low-level implemen-
tation details to designers of the function blocks.
ACM Computing Surveys, Vol. -, No. -, Article –, Publication date: September 201-.

Enabling adaptable IEC 61499-based cyber-physical systems –:33
In order to fully incorporate hardware virtualization in DRSoCs, the use of RecOSes
alone is not enough, since the entire endeavor has to be underpinned by preemptable
and relocatable hardware modules (Section 6.1). We have already discussed how re-
locatable modules can be created, using either bitstream modification means or more
advanced tools for creation DRSoCs (Section 6.2). The context management features,
as typically supported by today’s RecOes will be discussed in the next section.
6.3.2. Component-based framework context and relocation management.Supporting
thread-like features to hardware tasks entails conceiving the reconfigurable modules
(RMs) as fully independent objects, with consistent interfaces and a set of APIs for ef-
fective task preemption strategies. Similar to software tasks, reconfigurable hardware
modules in DRSoC platforms also need to be managed and scheduled, which entails
an awareness of the modules’ placements and current contexts. Hardware threads are
no longer merely passive components attached to the bus and controlled though a soft-
ware API: they can be reactive and contain internal state and context information.
The mechanisms necessary to guarantee the consistence and coherence of the relo-
cated and/or preempted tasks is known as a context management [Dondo et al. 2010].
Therefore, in recent years, many works have pointed towards the specification of hard-
ware components as tasks, from an object-oriented perspective: RMs need to be de-
signed in such a way that they can be safely stopped via checkpoints and a task man-
agement unit (i.e. context retrieval and reinjection, relocation) must be implemented
both at the component and RecOS level.
Therefore, abstraction mechanisms must be provided so that the low-level imple-
mentation details associated with the hardware components are transparent from the
application level perspective. Some examples of such wrappers have been presented
in the last few years [Kalte and Porrmann 2005], with varying levels of complexity
[Hsiung et al. 2009]. However, the majority of approaches share many commonalities,
regarding the manner in which these components interact with the RecOS as a bridge
to the modules to be executed in the PRR [Dondo et al. 2010]. An example of such a
wrapper [Wattebled et al. 2012] (proposed by the authors), and the associated process
state diagram (PSD) for a task are shown on Figure 23 a) and b), respectively.
The rationale behind this wrapping is that the task management services can be
implemented in hardware, discharging the processor of these time-consuming duties.
Thus, the wrappers serve as a bridge between the complex bus protocol signaling and
Fig. 23. a) A typical wrapper for context management b) Internal FSM for interacting with the PR executive
ACM Computing Surveys, Vol. -, No. -, Article –, Publication date: September 201-.

–:34 G. Ochoa-Ruiz
the actual sub-module functionalities (i.e., I/Os, hardware accelerators). In this sense,
it is very akin to the resource implementation of the IEC 61499 standard, enabling the
modification and relocation of functions (function blocks) onto resources (PRRs).
However, the most important feature of these modules is that they exploit object-
oriented strategies to achieve higher degrees of HW virtualization. In this manner, the
wrapper enables to cater for the management the state and context of the associated
RM, in a portable and data efficient manner. This is typically attained through the
implementation of a set of services at the RecOS level, which translate into specific
actions at the hardware level, for carrying out actions such as creating a thread (i.e.,
create task, set context) or removing it from the PRR (stop, disabling and killing a
task), which entail the manipulation and relocation of the task bitstream.
These activities are typically coordinated by an internal control unit (a command
decoder in Figure 23 a)) which serves as the interface between the RC management
and the wrapper, while federating the life-cycle of the allocated task through an FSM
(the PSD in Figure 23 b)). The FSM take into the account the state of the task before
inserting or removing it from the PRR (effectively enabling the required checkpoints for
the application) and informing a context controller that data is to be temporally stored,
either internally in the wrapper or in external memory [Ochoa-Ruiz et al. 2017].
As can be inferred from this brief introduction to the reconfiguration management
of DRSoCs, many of the endeavors carried out by the reconfigurable computing com-
munity in partially reconfigurable systems are not very far from the ongoing research
on the IEC 61499 standard.
Specifically, the device management specification aspects of the IEC 61499 standard,
discussed in Section 3.3 have been practically implemented in DRSoC platforms, with
the distribution and reconfiguration capabilities already in place thanks to the pro-
gresses made in partial reconfiguration technology and tools.
The manner in which the resource and function block models have been imple-
mented in some of the works discussed in Section 4.3 point at many commonalities
as well [Gawali and Sharma 2009], with the FB implementation of Figure 12 being
strikingly similar to the wrapper implementations introduced above. The same ap-
plies for the process state diagram (PSD) used to model the behavior of a task in many
current DRSoC implementations, which practically implements the PSD described in
the IEC 61499 (Figure 6), albeit in a massively parallel architecture setting.
However, despite of the increased sophistication and versatility in system concep-
tion which can be attained by using DRSoCs, a more holistic approach is needed in
order to exploit such kind of platforms for implementing heterogeneous IEC 61499 ap-
plications. Specifically, the code generation approaches discussed in Section 4.3 need
to be accompanied by interface synthesis and automatic integration in pre-defined
and widely accepted bus-wrappers, either as dynamic objects with internal context or
simple hardware threads that can be relocated onto various resources, either as soft-
ware and hardware implementations. In this manner, the design process becomes more
transparent from the application development perspective [Ochoa-Ruiz et al. 2015].
The platform description and the behavior of the DRSoC-based applications also
needs to be fully accessible by these code generation tools, in order to incorporate
the context management and relocation capabilities when necessary. A great deal of
research in this regard has been carried out by the model-driven engineering commu-
nity, through the introduction of several design tools for describing and implementing
Systems-On-Chip and subsequently, DRSoCs [Ochoa-Ruiz et al. 2017].
In the next section, we will provide some hints on how these efforts, and those de-
scribed in this section could coalesce into an holistic approach for implementing IEC-
61499 FPGA-based platforms, as well as the challenges that need to be addressed to
make this possible.
ACM Computing Surveys, Vol. -, No. -, Article –, Publication date: September 201-.

Enabling adaptable IEC 61499-based cyber-physical systems –:35
6.4. Summary and other avenues of research
In the previous sections, we have delved into an in-depth survey of the strides made
by the reconfigurable computing (RC) community to advance the partial reconfigura-
tion technology. These progresses have enabled system designers to move from rela-
tively simple, static partitioning strategies (in which independent task could simpy be
swapped in an out of the reconfigurable fabric), to more malleable platforms, which
we have dubbed Dynamically Reconfigurable Systems-on-Chip. The main goal of this
article was to highlight the many resemblances between many of the efforts carried
out by the RC community in recent years, and the previsions of the IEC 61499 norm,
in terms of how the devices based on the norm are expected to work.
Furthermore, in Section 4.4 we have provided some convincing arguments about
what we believe is currently lacking in both software and hardware implementations
of the IEC norms (i.e. MCU and FPGA-based implementations, respectively) and how
many of those shortcomings could be circumvented through the use of advance partial
reconfiguration tools and techniques, thoroughly discussed in this section. We have
focused our discussion mainly on the architectural aspects of the norm, and drawn
the many parallels that exist between the device manager and resource models in the
IEC 61499 norm, and many of the implementations currently being realized by the
academia in RC.
Nonetheless, the research in reconfigurable computing has not been limited to the
architectural aspects discussed in the previous sections. These developments have just
enabled the realization of full-fledged dynamic hardware objects or swappable (and
preemptable) logic units [Brebner 1997] (the context-aware wrappers discussed in Sec-
tion 6.3), which have permitted to implement many of the features currently lacking
in the FPGA-based implementations discussed in Section 4.3, namely: improving the
configurability of FPGA-based applications, enabling fine-grained reconfiguration of
HW tasks in many applications and finally, the distribution (i.e., relocation) of hard-
ware threads within resources (i.e., reconfigurable regions) in DRSoCs, which have
been exploited in a large number of applications.
Other features related to partial reconfiguration not addressed in this article pertain
to aspects such as HW/SW co-design, the partitioning of applications into software and
hardware functions for design space exploration purposes and finally, the best schedul-
ing strategies to be deployed within a particular application [Noguera and Badia 2004].
These are important issues, since the partial reconfiguration process incurs in latency
penalties that need to be taken into consideration during profiling of the application
for a given DRSoC platform [Papadimitriou et al. 2011], in order to obtain the best
compromise between performance and power consumption.
A great deal of research has been carried out using static scheduling strategies [Guil-
let et al. 2014] (the behavior of the DRSoC and reconfigurable regions is predefined of-
fline), but with the introduction of context-aware and preemptable hardware threads,
as well as come of the RecOSes briefly discussed in Section 6.3, the possibilities for
full-fledged dynamic scheduling, as those required by the IEC 61499 are not that far
ahead. However, we consider that a discussion on such topics is out of the scope of this
article and could be better served if addressed in a separate comparative survey, but
excellent sources already exist [Resano et al. 2008].
In the following section we will discuss how the efforts made by the reconfigurable
computing community, both in the implementation of the IEC norms and in the partial
reconfiguration domain could be brought together to implement full-fledged IEC 61499
platforms. As we will see, these efforts need to be harmonized through an approach
based on MDE and ESL practices, which have been gaining traction in recent years
for dealing with complex engineering problems [Sangiovanni-Vincentelli 2007].
ACM Computing Surveys, Vol. -, No. -, Article –, Publication date: September 201-.

–:36 G. Ochoa-Ruiz
7. TOWARDS AN INTEGRATED MDE IEC 61499 MODELING FRONT-END FOR SOC FPGAS
Since its inception in 2005, the IEC 61499 has attracted a great deal of research; many
different tools have been proposed to model applications based on the standard, but
many shortcomings and open problems remain [Thramboulidis 2012]. The majority of
these issues stem from the open-ended provisions of the specification, in terms of the
actual implementation of the several underlying models (i.e., function blocks, resources,
devices, and management executives), the execution semantics, and the interfacing
with the required run-time environments. More importantly, there is lack of widely
accepted hardware platforms to underpin the various ongoing efforts, which we believe
is instrumental for the convergence of the developments carried out by the academia
and the needs of the automation industry.
Moreover, the IEC 61499 standard represents not only a technological shift, but a
methodological paradigm, which imposes new challenges in the manner in which con-
trol systems are conceptualized, implemented, and validated [Patil et al. 2013]. Thor-
ough this article, we have analyzed some of the features that IEC 61499 platforms
are expected to include, as well as the shortcomings of current implementations. We
posited the DRSoCs represent and excellent choice for implementing such systems,
and here well discuss some of the challenges that need to be addressed to make this
convergence possible.
In particular, in order to provide a truly usable framework for IEC 61499 heteroge-
neous based on the reconfigurable architectures described in the last section, a holis-
tic approach combining elements from the automation and SoC domains is necessary,
united by a Model-Driven Engineering approach. In the following pages, we delve into
some of the current trends in both areas, and in the last sub-section, we discuss some
possible solutions and the associated challenges, concluding the article.
7.1. State of the adoption of MDE in the automation domain and open problems
In industrial automation, the well-established programming standards (i.e., IEC
61131-3) are often used to program parts of the system, such as the PLCs and other
IEDs. Despite many standardization efforts, every automation manufacturer provides
vendor-specific software tools for configuring and programming their hardware. In ad-
dition, communication among automation equipment is typically rather difficult due
to the plethora of communication standards and data exchange formalisms. In order to
overcome these limitations, a great deal of effort has been carried out by research and
industrial organizations to promote the introduction of new standards in the automa-
tion domain, specifically for enabling interoperability of previous efforts, based around
IEC 61131-3 standard [Thramboulidis 2005].
The most remarkable and active projects in this regard are represented by PLCopen
[Van der Wal 1999] initiative, and in a second degree, by recent research efforts, such
as AutomationML [Drath et al. 2008]. However, such efforts have fallen short in many
aspects, since the number of different development tools, models of computation and in
general, programming languages, make it practically impossible to achieve convergence
using a single framework. The same can be said the IEC 61499 standard, for which a
lot of disparate target implementation technologies and not always compatible run-
time environments exist.
Many works have sought to improve the specification of Distributed Control Systems
(DCS) through the use of UML [Bonfe and Fantuzzi 2003], in tandem with component-
based approaches [Thramboulidis 2005]. Following this logic, control algorithms are
encapsulated as Intelligent Mechatronic Component blocks with several design views,
covering various aspects of the component characteristics. Such blocks can then be
used for hierarchically composing complex systems, and using model transformations,
to obtain executable PLC code and various configuration models [Luder et al. 2011].
ACM Computing Surveys, Vol. -, No. -, Article –, Publication date: September 201-.

Enabling adaptable IEC 61499-based cyber-physical systems –:37
Moreover, the collaboration among different design tools involved in the develop-
ment cycle can be achieved by automatic model transformations between the inter-
nally employed formalisms. Models are internally represented (and stored) using meta-
languages, usually based on the eXtensible Markup Language (XML), which is ex-
ploited by design tools for a variety of design activities. Examples of such formalisms in
the automation domain are the Computer Aided Engineering eXchange format (CAEX,
for storing the system topology) [Schleipen and Okon 2010], and the aforementioned
PLCopen XML (logical information).
However, these formalisms are mostly used for configuration and storing variables
meta-data, and thus are not directly exploitable for hardware generation purposes in
FPGA-based design frameworks. However, they are widely accepted standards and
thus, many MDE-based endeavors have sought to incorporate as the backbone for the
development of new development tools, specifically in SCADA systems, such as the
O3NEIDA framework [Vyatkin et al. 2003] (briefly discussed in Section 2). Similar
efforts have been carried out within the SoC and reconfigurable computing community,
in which the introduction of the IP-XACT standard [IEEE 2009], which in tandem with
UML profiles for SoC design has spurred a great deal of research avenues, in particular
for partially reconfigurable systems [Ochoa-Ruiz et al. 2015].
The great variety of implementation choices fostered by the new standards such as
the IEC 61499 make the overall design of automation solutions for plants very com-
plex, especially when different technologies have to work in unison (i.e. IEDs, PLCs,
embedded systems, FPGA-based controllers, among others). It has been widely rec-
ognized that this ever increased complexity requires new methodologies, frameworks
and common, language independent models for representing, saving and reusing au-
tomation and control algorithms (i.e. automation components) [Yang et al. 2014], as
thoroughly discussed in Section 2.
Therefore, new MDE-based approaches in this context could offer various benefits: (i)
they could provide an incremental design approach enabling the specification of com-
plex systems, enabling a more holistic design view, as the possibility to concentrate in
various aspects of the design process through domain-specific languages, making the
system generation and verification more tractable [Vyatkin 2013], (ii) the cost of devel-
oping, maintaining and evolving such systems is reduced, as models can be exchanged
across different tools, thus promoting aspects such as configurability and interoper-
ability [Ochoa-Ruiz et al. 2012a] and (iii) these latter aspects could be enforced by
automatic code generation techniques for software control algorithms, if coupled with
appropriate HLS techniques, as discussed in Section 4.
Some incipient efforts have been done within the automation community, first with
some initial endeavors uniting the modeling of control systems [Bonfe and Fantuzzi
2003] and later with the introduction of the concept of the Intelligent Mechatronic
Component (IMC) for evaluating, integrating and exchanging automation control soft-
ware [Thramboulidis 2005]. Subsequent endeavors have sought to extend the reach of
MDE in the automation domain; two efforts standout for their breadth, the MEDEIA
[Strasser et al. 2009] and AUKOTON [Peltola et al. 2011] research projects. Such
projects have aimed at providing mechanisms for integrating automation plants en-
compassed by heterogeneous components, as well as for the generation of code for such
components from language independent models.
It is not the goal of this article to provide an extensive account of the efforts in
this domain, but the reader is directed to excellent sources to delve further in the
essential requirements for successfully implementing DCS [Dai et al. 2013]. Other
exhaustive surveys tackle ongoing efforts and open problems in this field, and how
they can be addressed by exploiting lessons learned from the software engineering
domain [Vyatkin 2013].
ACM Computing Surveys, Vol. -, No. -, Article –, Publication date: September 201-.

–:38 G. Ochoa-Ruiz
Fig. 24. Requirements for a metamodeling-driven framework for IEC 61499 DCS
Nonetheless, several works in the domain have pointed at the need of further refin-
ing the design process [Pang et al. 2014], by adding an extra layer in which techno-
logical details are introduced. This phase is instrumental as design methodologies for
IPMCS platforms incorporate more heterogeneous embedded devices, such as FPGAs
and DRSoCs. Moreover, such approaches need to integrate code generation techniques
targeting the synthesis on HDLs, in order to harmonize the efforts done in the au-
tomation and reconfigurable computing communities. Some of these aspects will be
delineated in the following sub-section, pointing at some of the research avenues that
need to be explored to make this convergence possible.
7.2. Discussion: MDE and DRSoCs: Opportunities and Challenges
DCS platforms are currently engineered as an assembly of heterogeneous components,
which can be seen as independent and heterogeneous units of control, typically known
as Automation Components. It has been recognized that in order to help the differ-
ent endeavors in the automation domain to coalesce into a more holistic approach for
distributed systems, MDE techniques need to be thoroughly applied during the entire
design process so that various concerns can be addressed within single framework.
Such an approach should allow as well let the different actors in the design pro-
cess to concentrate on what they want the overall system to achieve, regardless of
the low-level system implementation or target technology, using an adequate level of
abstraction, as well as domain specific concepts.
The IEC 61499 embodies such requirements, but several provisions need to be ad-
dressed before it can be successfully deployed in heterogeneous embedded platforms,
as depicted in Figure 24. First and foremost, several low-level and technology-specific
algorithmic implementations need to be abstracted (encapsulated) so they can be asso-
ciated with IEC 61499 FBs [Patel and Shukla 2012]. Moreover, code for various target
technologies should be automatically generated, in order to shield the control engineer
from the technology-specific details. Some of these aspects will be discussed as follows.
—(a) Automated generation of multi-platform FB libraries: To be effective, CAD
tools need to make extensive use of IP reuse for tasks such as system integra-
tion. In general, MDE-based approaches deploy component-based strategies in which
low-level meta-data is extracted and stored in data-books (via meta-data reflection)
[Mathaikutty and Shukla 2009]. Such strategies have been widely used in SoC de-
sign, and recently, in reconfigurable computing [Arnesen et al. 2010], based upon
standard formalisms such as IP-XACT. However, in order to be deployed by automa-
tion tools, various legacy FB implementations need to be abstracted (a) using the
adequate formalisms (i.e. CAEX, AutomationML, IP-XACT) so the high-level tem-
plates can be linked with their low-level counterparts [Ochoa-Ruiz et al. 2012a]. The
creation of these libraries can be performed automatically via model transformations.
ACM Computing Surveys, Vol. -, No. -, Article –, Publication date: September 201-.

Enabling adaptable IEC 61499-based cyber-physical systems –:39
—(b) Adequate high-level views for separation of concerns: Once the IP libraries
for various target technologies have been created, a designer can compose complex
DCS platforms using a modeling front-end (b). Of course, the IEC 61499 applications
described in Section 3.1 will be only one of the various models (views) of a distributed
system; other models for the execution semantics (model of computation), as well
as behavioral specification (i.e., reconfiguration semantics and constraints) would be
required, as they are not yet defined in the standard. Nonetheless, some research in
partial reconfiguration for DRSoCs, in conjunction with MDE techniques has been
conducted ([Guillet et al. 2014]) and can be used in the context of the IEC 61499.
—(c) Platform Specific Models for resource allocation: The most important as-
pect for transparently implementing algorithms in heterogeneous platforms is to at-
tain a high-degree of virtualization of the underlying hardware resources. In the
context of fixed architectures, such virtualization can be easily achieved through the
HW/SW interface, since the I/Os are usually fixed and abstracted as simple access
methods. However, intermediate hardware descriptions for heterogeneous embedded
platforms are not currently used in most automation methodologies and thus, a com-
bination of IP-XACT and the CAEX formalisms could prove useful. In the particular
context of DRSoCs, platform specific models, based on slot or grid DRSoC could pro-
vide effective means for allocating/mapping IEC 61499 FBs to FPGA resources.
—(d) Support of heterogeneous meta-models and automatic synthesis: In order
to produce concrete results, an effective MDE-based design framework uses model
transformation as the heart of the conception and implementation process. For this
purpose, a Model Transformation Engine is needed to federate the entire design pro-
cess (c). Low-level implementation details are retrieved from the meta-data IP li-
braries to produce executable code or back-end models (d), through a process known
as refinement. For instance, the high-level models to be mapped to reconfigurable
devices can be transformed into HDL code or direct synthesized into netlists [Ochoa-
Ruiz et al. 2012a]. Another possibility could involve transformations among models,
which can be exploited for legacy code reuse: IEC 61131-3 code can be transformed
into HDL code and encapsulated into FB hardware implementations, as the works
described in Section 4.3.
—(e) Models of computation and execution for IEC 61499 applications: As thor-
oughly discussed in Section 3.4, there are currently many gaps in the IEC 61499
specification regarding the model of computation. The vast majority of current tools
and RTEs make use of sequential hypotheses for implementing the event-based ap-
proach promoted by the standard, betraying its advantages and benefits. However,
the use of SoC FPGA devices, with truly concurrent and parallel execution of tasks,
could have significant benefits in the creation of full-fledged IEC 61499 devices. As
discussed in Section 5, the definition of a novel architecture model is very much re-
quired [Doukas and Thramboulidis 2011], along appropriate models of computation
(MoCs), which should unequivocally describe the interaction between the different
actors (i.e., RTE, device management services, etc) [Hofmann et al. 2011].
—(f) Models of execution for reconfiguration-capable systems: A similar claim
can be made for the reconfiguration provisions of the IEC 61499 standard: models of
execution need to be integrated into the modeling framework in order to take into
account the costs of the reconfiguration process [Papadimitriou et al. 2011], but also
communication delays between the different actors during the execution of DCS ap-
plication. In the context of DRSoC, several works have already addressed these as-
pects within MDE-based approaches. However, in order to provide such mechanisms
in IEC 61499 applications, more research needs to be done [Yan and Vyatkin 2013],
based on the concepts discussed in Section 6.3.
ACM Computing Surveys, Vol. -, No. -, Article –, Publication date: September 201-.

–:40 G. Ochoa-Ruiz
In summary, these various requirements pertain the device and resources modeling,
the execution and scheduling specifications, as well as the reconfiguration and distri-
bution of applications. However, several other concerns are particularly pressing, such
as the modeling of the system behavior, reliability and availability under several con-
ditions (i.e., cyber-attacks) [Serpanos and Voyiatzis 2013]. This might entail the inclu-
sion of security aspects in the device and execution models of the IEC 61499 standard.
In this regard, provisions described in the IEC 62443 [IEC 2013] standard (by the ISA
Security Compliance Institute) could prove useful, adding an additional arguments for
the use of FPGA in the prototyping and compliance of such systems, especially regard-
ing real-time analytics and intrusion detection mechanisms and strategies [Mitchell
and Chen 2014].
Reconfigurable devices represent an excellent choice not only for rapid system proto-
typing anymore, but for implementing full-fledged production systems, especially with
the advent of extended processing platforms by various FPGA vendors, incorporating
powerful processing capabilities via ARM processors, in which the previously RecOSes
can be easily ported. Recent strides in high-level synthesis are as well making it in-
creasingly easy to close the gap between the software and hardware communities, and
this could be as well the same for the automation domain, if some of the research
avenues outlined in this paper are explored.
8. CONCLUSIONS AND FINAL REMARKS
In this paper, we have discussed the current state of the IEC 61499 standard, which
was introduced as a means to architect multi-platform DCS from a common applica-
tion model. The provisions of the IEC for this one and other standards have proven
insufficient to attain the much desired features of agile systems. The first two require-
ments (portability and configurability) have been partially solved via the standardiza-
tion and programming languages, while the third (interoperability) still necessitates
the successful incorporation of other standards, such as the IEC 64424.
Nonetheless, the main of issues hampering the adoption of the IEC 61499 are not
only methodological, but stem in no small part from the lack of common and well-
accepted reference hardware models. We have briefly discussed how SoC FPGAs could
be used for successfully implementing IEC 61499-based systems, with several advan-
tages such the capability to explore various device management strategies and re-
source allocation of HW or SW tasks and the possibility to implement full-fledged re-
configuration and distribution.
In particular, we have discussed several progresses made by the reconfigurable com-
puting community, which are strikingly close to those sought by the IEC 61499 stan-
dard and which have not been addressed by the ongoing efforts in the implementation
of the standard in reconfigurable devices.
We believe that such progresses, pertaining new capabilities in the creation of DR-
SoCs (such as task management and relocation in tile- and slot-based platforms) could
have a positive impact in overcoming the limitations currently associated with IEC
61499 hardware implementations. The virtualization capabilities provided by dynam-
ically reconfigurable SoC-FPGAs could foster research in the automation community
and enable capabilities such as distribution and reconfiguration, currently lacking in
mostly static implementations of the standard.
Moreover, they could enable to seamlessly integrate and explore various schedul-
ing and device management policies using a common architectural framework and
potentially further promote IP exchange among the various actors in the automation
community. Furthermore, several interesting developments in the High-level synthe-
sis could provide the additional boost required to bridge the gap that has traditionally
hampered the use of reconfigurable devices beyond specialized application areas.
ACM Computing Surveys, Vol. -, No. -, Article –, Publication date: September 201-.

Enabling adaptable IEC 61499-based cyber-physical systems –:41
However, as discussed in the second portion of the article, the challenges for the con-
vergence of these various disparate concerns demand innovative modeling paradigms.
A lot of recent research suggests that one of the most promising routes is to make
extensive use of Model-driven Engineering techniques, accompanied by the encapsu-
lation of the various control algorithms (i.e., Function Blocks) into multi-language and
multi-platform libraries. More importantly, the incorporation of adequate architecture
models for several target technologies, in order to foster interoperability is a necessity,
but adequate models of execution and computation are also required in order to tame
the complexity of the DCS in which such devices are to be integrated.
Furthermore, a major challenge in the adoption of new technological paradigms
comes from the engineering perspective: in order to be used by the industry, the per-
ceived migration cost associated with new tools and technologies should be signifi-
cantly smaller than the perceived benefit. In order to overcome the much maligned
learning curves and migration costs, the entire endeavor needs to be underpinned as
well by appropriate tools, so the various experts can concentrate in describing their
respective concerns, letting the tools to cater for the implementation details, though
automated procedures.
REFERENCES
S.Z. Ahmed, G. Sassatelli, L. Torres, and L. Rouge. 2010. Survey of New Trends in Industry for Pro-
grammable Hardware: FPGAs, MPPAs, MPSoCs, Structured ASICs, eFPGAs and New Wave of Inno-
vation in FPGAs. In Field Programmable Logic and Applications (FPL), 2010 International Conference
on. 291–297.
F. Andren, T. Strasser, A. Zoitl, and I. Hegny. 2012. A reconfigurable communication gateway for distributed
embedded control systems. In 38th Annual Conference on IEEE Industrial Electronics Society.
A. Arnesen, K. Ellsworth, D. Gibelyou, T. Haroldsen, J. Havican, M. Padilla, B. Nelson, M. Rice, and M.
Wirthlin. 2010. Increasing Design Productivity through Core Reuse, Meta-data Encapsulation, and Syn-
thesis. In Field Programmable Logic and Applications (FPL),International Conference on. 538 –543.
A. Astarloa. 2016. Intelligent Gateways Make a Factory Smarter. In Xilinx Xcell Journal Vol. 94. 14–21.
D. Bacon, R. Rabbah, and S. Shukla. 2013. FPGA Programming for the Masses. Queue 11, 2 (2013).
C. Beckhoff, D. Koch, and J. Torresen. 2014. Design Tools for Implementing Self-Aware and Fault-Tolerant
Systems on FPGAs. ACM Trans. Reconfigurable Technol. Syst. 7, 2, Article 14 (2014), 23 pages.
D. Blouin, G. Ochoa-Ruiz, Y. Eustache, and J. P. Diguet. 2015. Kaolin: A system-level AADL tool for FPGA
design reuse, upgrade and migration. In Adaptive Hardware and Systems (AHS), 2015 NASA/ESA
Conference on. 1–8.
M. Bonfe and C. Fantuzzi. 2003. Design and verification of mechatronic object-oriented models for industrial
control systems. In Emerging Technologies and Factory Automation, 2003. Proceedings. ETFA ’03. IEEE
Conference, Vol. 2. 253–260 vol.2. DOI:http://dx.doi.org/10.1109/ETFA.2003.1248708
G. Brebner. 1997. The swappable logic unit: a paradigm for virtual hardware. In Field-Programmable Cus-
tom Computing Machines, 1997. Proceedings., The 5th Annual IEEE Symposium on. 77–86.
A. Chang. 2015. Innovative Platform-based Design for the Industrial Internet of Things. In Xilinx Xcell
Journal Vol. 92. 32–37.
Miroslaw Chmiel, Jan Mocha, and Edward Hrynkiewicz. 2010. A FPGA-Based Bit-Word {PLC} {CPUs}
Development Platform. {IFAC}Proceedings Volumes 43, 24 (2010), 132 – 137. 10th {IFAC}Workshop
on Programmable Devices and Embedded Systems.
K. Compton and A. DeHon. 2007. Chapter 11: Operating System Support for Reconfigurable Computing,
Reconfigurable Comnputing: The Theory and Pactice of FPGA-based Computation. Morgan Kaufmann.
S. Corbetta, M. Morandi, M. Novati, M.D. Santambrogio, D. Sciuto, and P. Spoletini. 2009. Internal and Ex-
ternal Bitstream Relocation for Partial Dynamic Reconfiguration. Very Large Scale Integration (VLSI)
Systems, IEEE Transactions on 17, 11 (Nov 2009), 1650–1654.
P. Coussy. 2008. High-Level Synthesis: From Algorithm to Digital Circuit. Springer.
P. Coussy, D. D. Gajski, M. Meredith, and A. Takach. 2009. An Introduction to High-Level Synthesis. IEEE
Design Test of Computers 26, 4 (July 2009), 8–17. DOI:http://dx.doi.org/10.1109/MDT.2009.69
Philippe Coussy, Dominique Heller, and Cyrille Chavet. 2011. High-Level Synthesis: On the path to ESL
design. In 2011 IEEE 9th International Conference on ASIC, ASICON 2011, Xiamen, China, October
25-28, 2011. 1098–1101.
ACM Computing Surveys, Vol. -, No. -, Article –, Publication date: September 201-.

–:42 G. Ochoa-Ruiz
Wenbin Dai, V. Vyatkin, and J.H. Christensen. 2013. Essential elements for programming of distributed
automation and control systems. In Emerging Technologies Factory Automation (ETFA), 2013 IEEE
18th Conference on. 1–8.
J. P. Delahaye, J. Palicot, C. Moy, and P. Leray. 2007. Partial Reconfiguration of FPGAs for Dynamical
Reconfiguration of a Software Radio Platform. In 2007 16th IST Mobile and Wireless Communications
Summit. 1–5. DOI:http://dx.doi.org/10.1109/ISTMWC.2007.4299250
D. Densmore and R. Passerone. 2006. A Platform-Based Taxonomy for ESL Design. IEEE Design Test of
Computers 23, 5 (May 2006), 359–374. DOI:http://dx.doi.org/10.1109/MDT.2006.112
J. Dondo, F. Rincon, J. Barba, F. Moya, F. Sanchez, and J.C. Lopez. 2010. Persistence Management Model
for Dynamically Reconfigurable Hardware. In Digital System Design: Architectures, Methods and Tools
(DSD), 2010 13th Euromicro Conference on. 482–489.
G. Doukas and K. Thramboulidis. 2011. A Real-Time-Linux-Based Framework for Model-Driven Engineer-
ing in Control and Automation. Industrial Electronics, IEEE Transactions on 58, 3 (2011), 914–924.
R. Drath, A. Luder, J. Peschke, and L. Hundt. 2008. AutomationML - the glue for seamless automation
engineering. In Emerging Technologies and Factory Automation. IEEE International Conference on.
D. Du, X. Xu, and K. Yamazaki. 2010. A study on the generation of silicon-based hardware Plc by means
of the direct conversion of the ladder diagram to circuit design language. The International Journal of
Advanced Manufacturing Technology 49, 5-8 (2010), 615–626.
R. Dubey. 2009. Embedded System Design Using Field Programmable Gate Arrays (1st ed.). Springer.
V. Dubinin and V. Vyatkin. 2008. On Definition of a Formal Model for IEC 61499 Function Blocks. EURASIP
Journal on Embedded Systems 2008, 1 (2008), 426713.
L. Ferrarini and C. Veber. 2004. Implementation approaches for the execution model of IEC 61499 applica-
tions. In Industrial Informatics, 2004. INDIN ’04. 2004 2nd IEEE International Conference on. 612–617.
P. Garcia, K. Compton, M. Schulte, E. Blem, and W. Fu. 2006. An Overview of Reconfigurable Hardware in
Embedded Systems. EURASIP Journal on Embedded Systems (2006).
D. Gawali and V. K. Sharma. 2009. FPGA Based Micro-PLC Design Approach. In Advances in Computing,
Control, Telecommunication Technologies, 2009. ACT ’09. International Conference on. 660–663.
C. Gerber, H.-M. Hanisch, and S. Ebbinghaus. 2008. From IEC 61131 to IEC 61499 for Distributed Systems:
A Case Study. EURASIP J. Embedded Syst. 2008, Article 4 (April 2008), 8 pages.
A. Gerstlauer, C. Haubelt, A. D. Pimentel, T. P. Stefanov, D. D. Gajski, and J. Teich. 2009. Electronic System-
Level Synthesis Methodologies. IEEE Transactions on Computer-Aided Design of Integrated Circuits
and Systems 28, 10 (Oct 2009), 1517–1530. DOI:http://dx.doi.org/10.1109/TCAD.2009.2026356
J.F. Goeders, G.M Holland, L. Shannon, and S.J.E. Wilton. 2015. Chapter 14: Systems-on-Chip on FPGAs.
In FPGAs for Software Programmers, D. Koch, F. Hannig, and D. Ziener (Eds.). Springer Netherlands,
461–283.
Diana G¨
ohringer, Stephan Werner, Michael H¨
ubner, and J¨
urgen Becker. 2011. RAMPSoCVM: Runtime
Support and Hardware Virtualization for a Runtime Adaptive MPSoC. In International Conference on
Field Programmable Logic and Applications, FPL 2011, September 5-7, Chania, Crete, Greece.
L. Gomes, E. Monmasson, M. Cirstea, and J.J. Rodriguez-Andina. 2013. Industrial electronic control: FP-
GAs and embedded systems solutions. In Industrial Electronics Society, IECON 2013 - 39th Annual
Conference of the IEEE. 60–65.
S. Guillet, F. de Lamotte, N. Le Griguer, E. Rutten, G. Gogniat, and J.-P. Diguet. 2014. Extending
UML/MARTE to Support Discrete Controller Synthesis, Application to Reconfigurable Systems-on-Chip
Modeling. ACM Trans. Reconfigurable Technol. Syst. 7, 3, Article 27 (Sept. 2014), 17 pages.
A. Gupte and P. Jones. 2009. Hotspot Mitigation Using Dynamic Partial Reconfiguration for Improved Per-
formance. In Reconfigurable Computing and FPGAs, 2009. International Conference on. 89–94.
Z. Hajduk, B. Trybus, and J. Sadolewski. 2015. Architecture of FPGA Embedded Multiprocessor Pro-
grammable Controller. Industrial Electronics, IEEE Transactions on 62, 5 (May 2015), 2952–2961.
Mohamed Ben Hammouda, Philippe Coussy, and Lo¨
ıc Lagadec. 2014. A design approach to automatically
generate on-chip monitors during high-level synthesis of hardware accelerator. In Great Lakes Sympo-
sium on VLSI 2014, GLSVLSI ’14, Houston, TX, USA - May 21 - 23, 2014. 273–278.
R. Hartenstein. 2007. Chapter 20: Basics of Reconfigurable Computing. 451 –501 pages.
R. Hartenstein and T. Kaiserslautern. 2007. Chapter 22: Applications, design tools and low power issues
in fpga reconfiguration. In Designing Embedded Processors, Jrg Henkel and Sri Parameswaran (Eds.).
Springer Netherlands, 451–501. DOI:http://dx.doi.org/10.1007/978-1-4020-5869-1 20
Mark D. Hill and Michael R. Marty. 2008. Amdahl’s Law in the Multicore Era. Computer 41, 7 (July 2008).
M. Hofmann, M. Rooker, and A. Zoitl. 2011. Improved communication model for an IEC 61499 runtime
environment. In Emerging Technologies Factory Automation, 2011 IEEE 16th Conference on. 1–7.
ACM Computing Surveys, Vol. -, No. -, Article –, Publication date: September 201-.

Enabling adaptable IEC 61499-based cyber-physical systems –:43
P.-A. Hsiung, CC.-H. Huang, and Y.-H. Chen. 2009. Hardware Task Scheduling and Placement in Operating
Systems for Dynamically Reconfigurable SoC. J. Embedded Comput. 3, 1 (Jan. 2009), 53–62.
S. Ichikawa, M. Akinaka, H. Hata, R. Ikeda, and H. Yamamoto. 2011. An FPGA implementation of hard-
wired sequence control system based on PLC software. IEEJ Transactions on Electrical and Electronic
Engineering 6, 4 (2011), 367–375.
IEC. 1993. International Standard IEC 6113-3: Part 3: Programming Languages. IEC.
IEC. 2005. International Standard IEC 61499-1: Function Blocks - Part 1: Architecture. IEC.
IEC. 2013. International Standard IEC 62443: Industrial Network and System Security. IEC.
IEEE. 2009. IEEE 1685, IEEE Standard for IP-XACT, Standard Structure for Packaging, Integrating, and
Reusing IP within Tools Flows. http://standards.ieee.org/getieee/1685/download/1685-2009.pdf. (2009).
X. Iturbe, K. Benkrid, Chuan Hong, A. Ebrahim, R. Torrego, I. Martinez, T. Arslan, and J. Perez. 2013.
R3TOS: A Novel Reliable Reconfigurable Real-Time Operating System for Highly Adaptive, Efficient,
and Dependable Computing on FPGAs. Computers, IEEE Transactions on 62, 8 (Aug 2013), 1542–1556.
Abhishek Kumar Jain, Khoa Dang Pham, Jin Cui, Suhaib A. Fahmy, and Douglas L. Maskell. 2014. Vir-
tualized Execution and Management of Hardware Tasks on a Hybrid ARM-FPGA Platform. J. Signal
Process. Syst. 77, 1-2 (Oct. 2014), 61–76. DOI:http://dx.doi.org/10.1007/s11265-014-0884- 1
B. Janssen, F. Schwiegelshohn, M. Koedam, F. Duhem, L. Masing, S. Werner, C. Huriaux, A. Courtay, E.
Wheatley, K. Goossens, F. Lemonnier, P. Millet, O. Becker, J.and Sentieys, and M. Hubner. 2015. Design-
ing applications for heterogeneous many-core architectures with the FlexTiles Platform. In Embedded
Comp. Syst.: Architectures, Modeling, and Simulation, 2015 International Conference on. 254–261.
H. Kalte and M. Porrmann. 2005. Context saving and restoring for multitasking in reconfigurable systems.
In Field Programmable Logic and Applications, 2005. International Conference on. 223–228.
D. Kirschberger, H. Flatt, and J. Jasperneite. 2014. An architectural approach for reconfigurable industrial
I/O devices. In ReConFigurable Computing and FPGAs, 2014 International Conference on. 1–6.
D. Koch, C. Beckhoff, and J. Teich. 2008. ReCoBus-Builder: A novel tool and technique to build statically and
dynamically reconfigurable systems for FPGAS. In Field Programmable Logic and Applications, 2008.
FPL 2008. International Conference on. 119–124. DOI:http://dx.doi.org/10.1109/FPL.2008.4629918
D. Koch, J. Torresen, C. Beckhoff, D. Ziener, C. Dennl, V. Breuer, J. Teich, M. Feilen, and W. Stechele. 2012.
Partial Reconfiguration on FPGAs in Practice - Tools and Applications. In ARCS Workshops. 297–319.
I. Kuon and R.J Rose. 2010. Quantifying and Exploring the Gap Between FPGAs and ASICs. Springer.
C. Lavin, M. Padilla, J. Lamprecht, P. Lundrigan, B. Nelson, and B. Hutchings. 2011. RapidSmith: Do-
It-Yourself CAD Tools for Xilinx FPGAs. In Field Programmable Logic and Applications (FPL), 2011
International Conference on. 349–355.
R.W Lewis. 2001. Modeling Control Systems using IEC 61499. IEE.
Enno L ¨
ubbers and Marco Platzner. 2009. ReconOS: Multithreaded Programming for Reconfigurable Com-
puters. ACM Trans. Embed. Comput. Syst. 9, 1, Article 8 (Oct. 2009), 8:1–8:33 pages.
A. Luder, E. Estevez, L. Hundt, and M. Marcos. 2011. Automatic transformation of logic models within
engineering of embedded mechatronical units. The International Journal of Advanced Manufacturing
Technology 54 (2011), 1077–1089.
P. Manet, D. Maufroid, L. Tosi, O. Gailliard, G.and Mulertt, M. Di Ciano, J.-D. Legat, D. Aulagnier, C.
Gamrat, R. Liberati, V. La Barba, P. Cuvelier, and P. Rousseau, B.and Gelineau. 2008. An evaluation of
dynamic partial reconfiguration for signal and image processing in professional electronics applications.
EURASIP J. Embedded Syst. 2008, Article 1 (Jan. 2008), 11 pages.
N. Marques, H. Rabah, E. Dabellani, and S. Weber. 2014. A Novel Framework for the Design of Adapt-
able Reconfigurable Partitions for the Placement of Variable-sized IP Cores. Embedded Systems Letters,
IEEE 6, 3 (Sept 2014), 45–48. DOI:http://dx.doi.org/10.1109/LES.2014.2317254
D.A. Mathaikutty and S.K. Shukla. 2009. Metamodeling-Driven IP Reuse for SoC Integration and Micropro-
cessor Design (1st ed.). Artech House, Inc., Norwood, MA, USA.
C. Maxfield. 2009. FPGA:s World Class Designs (1st ed.). Newnes.
E. J. McDonald. 2008. Runtime FPGA Partial Reconfiguration. In Aerospace Conference, 2008 IEEE. 1–7.
J-Y. Mignolet, V. Nollet, P. Coene, D. Verkest, S. Vernalde, and R. Lauwereins. 2003. Infrastructure for
Design and Management of Relocatable Tasks in a Heterogeneous Reconfigurable System-on-Chip. In
Proceedings of the Conference on Design, Automation and Test in Europe, DATE.
Adam Milik. 2016. On hardware synthesis and implementation of {PLC}programs in {FPGAs}.Micropro-
cessors and Microsystems 44 (2016), 2 – 16. Modern Techniques of Design and Implementation of Highly
Flexible Controllers.
ACM Computing Surveys, Vol. -, No. -, Article –, Publication date: September 201-.

–:44 G. Ochoa-Ruiz
Robert Mitchell and Ing-Ray Chen. 2014. A Survey of Intrusion Detection Techniques for Cyber-physical
Systems. ACM Comput. Surv. 46, 4, Article 55 (March 2014), 29 pages.
E. Monmasson, L. Idkhajine, and M. W Naouar. 2011. FPGA-based Controllers. Industrial Electronics Mag-
azine, IEEE 5, 1 (March 2011), 14–26.
D.P. Montminy, R.O. Baldwin, P.D. Williams, and B.E. Mullins. 2007. Using Relocatable Bitstreams for Fault
Tolerance. In Adaptive Hardware and Systems, 2007. Second NASA/ESA Conference on. 701–708.
B. Navas, J. Oberg, and I. Sander. 2013a. Towards the generic reconfigurable accelerator: Algorithm devel-
opment, core design, and performance analysis. In Int. Conf. on Reconfigurable Computing and FPGAs.
B. Navas, I. Sander, and J. berg. 2013b. The RecoBlock SoC platform: A flexible array of reusable Run-Time-
Reconfigurable IP-blocks. In Design, Automation Test in Europe Conference (DATE), 2013. 833–838.
C. Neely, G. Brebner, and W. Shang. 2013. ReShape: Towards a High-Level Approach to Design and Opera-
tion of Modular Reconfigurable Systems. ACM Trans. Reconf. Technol. Syst. 6, 1, Article 5 (2013).
S. Neuendorffer. 2010. Chapter 12: FPGA Platforms for Embedded Systems, Model-Based Design for Embed-
ded Systems. Morgan Kaufmann.
Juanjo Noguera and Rosa M. Badia. 2004. Multitasking on Reconfigurable Architectures: Microarchitecture
Support and Dynamic Scheduling. ACM Trans. Embed. Comput. Syst. 3, 2 (May 2004), 385–406.
G. Ochoa-Ruiz, S. Guillet, F. de Lamotte, E. Rutten, E.-B. Bourennane, J.-P. Diguet, and G. Gogniat. 2015. An
MDE approach for Rapid Prototyping and implementation of Dynamic Reconfigurable Systems. ACM
Trans. Des. Autom. Electron. Syst. 21, 1, Article 8 (Oct. 2015), 25 pages.
G. Ochoa-Ruiz, O. Labbani, E. Bourennane, P. Soulard, and S. Cherif. 2012a. A high-level methodology
for automatically generating dynamic partially reconfigurable systems using IP-XACT and the UML
MARTE profile. Design Automation for Embedded Systems (2012), 1–36.
G. Ochoa-Ruiz, O. Labbani-Narsis, E. Bourennane, S. Cherif, S. Meftali, and J. Dekeyser. 2012b. Facilitating
IP deployment in a MARTE-based MDE methodology using IP-XACT: A Xilinx EDK case study. In
Reconfigurable Computing and FPGAs (ReConFig), 2012 International Conference on. 1–8.
G. Ochoa-Ruiz, M. Touiza, E. Bourennane, A. Guessoum, K. Messaoudi, and M.A. Hajjaji. 2013. A Novel
approach for accelerating bitstream relocation in many-core partially reconfigurable applications. In
Control, Decision and Information Technologies (CoDIT), 2013 International Conference on. 271–276.
G. Ochoa-Ruiz, P. Wattebled, T. Maamar, F. de Lamotte, S. Meftali, J.-P. Diguet, E.-B. Bourennane, and J.-L.
Dekeyser. 2017. A modeling front-end for seamless design and generation of context-aware Dynamically
Reconfigurable Systems-on-Chip. In Journal on Parallel and Distributed Computing, Special Issue on
Reconfigurable Computing and FPGA Technology.
OMG. 2014. Model-driven Engineering. http://www.ogm/org/mda. (2014).
D. O’Sullivan and D. Heffernan. 2010. VHDL architecture for IEC 61499 function blocks. Computers Digital
Techniques, IET 4, 6 (November 2010), 515–524.
A. Otero, E. de la Torre, and T. Riesgo. 2012. Dreams: A tool for the design of dynamically reconfigurable
embedded and modular systems. In 2012 International Conference on Reconfigurable Computing and
FPGAs, ReConFig 2012, Cancun, Mexico, December 5-7, 2012. 1–8.
Cheng Pang, V. Vyatkin, and Wenbin Dai. 2014. IEC 61499 based model-driven process control engineering.
In Emerging Technology and Factory Automation (ETFA), 2014 IEEE. 1–8.
K. Papadimitriou, A. Dollas, and S. Hauck. 2011. Performance of Partial Reconfiguration in FPGA Systems:
A Survey and a Cost Model. ACM Trans. Reconfigurable Technol. Syst. 4, 4, Article 36 (Dec. 2011).
H.D. Patel and S.K. Shukla. 2012. Ingredients for Successful System Level Design Methodology. Springer.
S. Patil, J. Yan, V. Vyatkin, and Cheng Pang. 2013. On composition of mechatronic components enabled by
interoperability and portability provisions of IEC 61499: A case study. In Emerging Technologies Factory
Automation (ETFA), 2013 IEEE 18th Conference on. 1–4.
J. Peltola, S. Sierla, T. Vepslinen, and K. Koskinen. 2011. Challenges in industrial adoption of model-driven
technologies in process control application design. In 9th IEEE Int. Conf. on Ind. Informatics.
J. Resano, J.A. Clemente, C. Gonzalez, D. Mozos, and F. Catthoor. 2008. Efficiently Scheduling Runtime
Reconfigurations. ACM Trans. Des. Autom. Electron. Syst. 13, 4, Article 58 (Oct. 2008), 12 pages.
A. Sangiovanni-Vincentelli. 2007. Quo Vadis, SLD? Reasoning About the Trends and Challenges of System
Level Design. Proc. IEEE 95, 3 (march 2007), 467 –506.
M. Santarini. 2010. Xilinx FPGAs: Creating a Greener Future for Industrial Motor Control. In Xilinx Xcell
Journal Vol. 73, Fourh Quqrter. 8–11.
M. Schleipen and M. Okon. 2010. The CAEX tool suite - User assistance for the use of standardized plant
engineering data exchange. In Emerging Technologies and Factory Automation, IEEE Conference on.
ACM Computing Surveys, Vol. -, No. -, Article –, Publication date: September 201-.

Enabling adaptable IEC 61499-based cyber-physical systems –:45
Dimitrios N. Serpanos and Artemios G. Voyiatzis. 2013. Security Challenges in Embedded Systems. ACM
Trans. Embed. Comput. Syst. 12, 1s, Article 66 (March 2013), 10 pages.
A.A. Sohanghpurwala, P. Athanas, T. Frangieh, and A. Wood. 2011. OpenPR: An Open-Source Partial-
Reconfiguration Toolkit for Xilinx FPGAs. In Parallel and Distributed Processing Workshops and Phd
Forum (IPDPSW), 2011 IEEE International Symposium on. 228–235.
T. Strasser, M. Rooker, I. Hegny, M. Wenger, A. Zoitl, L. Ferrarini, A. Dede, and M. Colla. 2009. A research
roadmap for model-driven design of embedded systems for automation components. In Industrial Infor-
matics, 2009. INDIN 2009. 7th IEEE International Conference on. 564–569.
T. Strasser, A. Zoitl, J.H. Christensen, and C. Sunder. 2011. Design and Execution Issues in IEC 61499
Distributed Automation and Control Systems. Systems, Man, and Cybernetics, Part C: Applications and
Reviews, IEEE Transactions on 41, 1 (Jan 2011), 41–51.
C. Sunder, A. Zoitl, J.H. Christensen, H. Steininger, and J. Rritsche. 2008. Considering IEC 61131-3 and IEC
61499 in the context of component frameworks. In Ind. Informatics, 6th IEEE Int. Conf. on. 277–282.
K. Thramboulidis. 2005. Model-integrated mechatronics - toward a new paradigm in the development of
manufacturing systems. Industrial Informatics, IEEE Transactions on 1, 1 (Feb 2005), 54–61.
K. Thramboulidis. 2008. Challenges in the development of Mechatronic systems: The Mechatronic Compo-
nent. In Emerging Technologies and Factory Automation. IEEE International Conference on. 624–631.
K. Thramboulidis. 2012. IEC 61499: Back to the well proven practice of IEC 61131?. In Emerging Technolo-
gies Factory Automation (ETFA), 2012 IEEE 17th Conference on. 1–8.
M. Touiza, G. Ochoa-Ruiz, E. Bourennane, A. Guessoum, and K. Messaoudi. 2013. A novel methodology for
accelerating bitstream relocation in partially reconfigurable systems. Microprocessors and Microsystems
37, 3 (2013), 358 – 372.
E. Van der Wal. 1999. Introduction into IEC 1131-3 and PLCopen. In The Application of IEC 61131 to
Industrial Control: Improve Your Bottom Line Through High Value Industrial Control Systems (Ref. No.
1999/076), IEE Colloquium on. 2/1–2/8.
V. Vyatkin. 2009. The IEC 61499 standard and its semantics. Industrial Electronics Magazine, IEEE 3, 4
(Dec 2009), 40–48.
V. Vyatkin. 2013. Software Engineering in Industrial Automation: State-of-the-Art Review. Industrial Infor-
matics, IEEE Transactions on 9, 3 (Aug 2013), 1234–1249.
V. Vyatkin, J. Christensen, J.L.M. Lastra, and F. Auinger. 2003. OOONEIDA: an open, object-oriented
knowledge economy for intelligent distributed automation. In Industrial Informatics, 2003. INDIN
2003. Proceedings. IEEE International Conference on. 79–88.
P. Wattebled, J.-P. Diguet, and J. Dekeyser. 2012. Membrane-based design and management methodology
for parallel dynamically reconfigurable embedded systems. In ReCoSoC. 1–8.
D. Wenbin and V. Vyatkin. 2012. Redesign Distributed PLC Control Systems Using IEC 61499 Function
Blocks. Automation Science and Engineering, IEEE Transactions on 9, 2 (April 2012), 390–401.
A. Wold, A. Agne, and J. Torresen. 2014. Relocatable Hardware Threads in Run-Time Reconfigurable Sys-
tems. In Reconfigurable Computing: Architectures, Tools, and Applications - 10th International Sympo-
sium, ARC 2014, Vilamoura, Portugal, April 14-16, 2014. Proceedings. 61–72.
R. Woods, J. McAllister, G. Lightbody, and Y. Yi. 2008. FPGA-based Implementation of Signal Processing
Systems (1st ed.). Wiley.
Xilinx. 2012. Partial Reconfiguration Overview, WP374. http://www.xilinx.com. (2012).
J. Yan and V. Vyatkin. 2013. Distributed Software Architecture Enabling Peer-to-Peer Communicating Con-
trollers. Industrial Informatics, IEEE Transactions on 9, 4 (Nov 2013), 2200–2209.
C. Yang, V. Vyatkin, and C. Pang. 2014. Model-Driven Development of Control Software for Distributed
Automation: A Survey and an Approach. Systems, Man, and Cybernetics: Systems, IEEE Transactions
on 44, 3 (March 2014), 292–305.
S. Yousuf and A. Gordon-Ross. 2010. DAPR: Design Automation for PR FPGAs.. In ERSA. 97–103.
N. Zilberman, Y. Audzevich, G.A. Covington, and A.W. Moore. 2014. NetFPGA SUME: Toward 100 Gbps as
Research Commodity. Micro, IEEE 34, 5 (Sept 2014), 32–41.
A. Zoitl. 2009. Real-time execution for IEC 61499. ISA.
A. Zoitl, T. Strasser, and G. Ebenhofer. 2013. Developing modular reusable IEC 61499 control applications
with 4DIAC. In Industrial Informatics (INDIN), 2013 11th IEEE International Conference on. 358–363.
A. Zoitl, T. Strasser, C. Sunder, and T. Baier. 2009. Is IEC 61499 in harmony with IEC 61131-3? Industrial
Electronics Magazine, IEEE 3, 4 (Dec 2009), 49–55.
Received February 20–; revised March 20–; accepted June 20–
ACM Computing Surveys, Vol. -, No. -, Article –, Publication date: September 201-.