A Dynamic Current Mode D-Flipflop for High Speed Application

Abstract

—With the continuous growth of semiconductor
technologies, the design of high-speed circuits is a need of the
hour. Current Mode Logic (CML), a derivation from Emitter
Coupled Logic (ECL) is such an approach with concerns
present to be improvised. Targeting that, we have come up
with a new design of dynamic CML to structure a power
efficient D-Flipflop. The simulations are carried out for 90nm
CMOS using Synopsys H-Spice platform at a supply voltage
and operating frequency of 1.2V and 10GHz respectively. The
device footprint reads an area requirement of 108.624 µm2
(16.045µm × 6.77µm). This design is noted to dissipate a very
low power of 219.05uW and delay of as small as 31.30ps when
driven with aperiodic data of 2.5GHz.

Full text

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A Dynamic Current Mode D-Flipflop for High
Speed Application
Madhusudan Maiti, Anupama Paul, Suraj Kumar Saw, Alak Majumder
Integrated Circuit and System (i-CAS) Lab, Department of Electronics and Communication Engineering,
National Institute of Technology, Arunachal Pradesh, Yupia- 791112, India.
Email: {madhusudan.maiti, anupamapaul10, srjsaw98 , majumder.alak} @gmail.com
Abstract—
With the continuous growth of semiconductor
technologies, the design of high-speed circuits is a need of the
hour. Current Mode Logic (CML), a derivation from Emitter
Coupled Logic (ECL) is such an approach with concerns
present to be improvised. Targeting that, we have come up
with a new design of dynamic CML to structure a power
efficient D-Flipflop. The simulations are carried out for 90nm
CMOS using Synopsys H-Spice platform at a supply voltage
and operating frequency of 1.2V and 10GHz respectively. The
device footprint reads an area requirement of 108.624 µm
2
(16.045µm × 6.77µm). This design is noted to dissipate a very
low power of 219.05uW and delay of as small as 31.30ps when
driven with aperiodic data of 2.5GHz.
Keywords— Low power, Current mode logic, D-latch, High
speed, D-flip flop.
I. I
NTRODUCTION
The increase in the demand of high-speed wireline
communication systems has facilitated the rapid
advancement of high-performance logic circuits which can
burn low power along with managing high rate data. The D
Latch or delay flip flop (D-FF) logic circuit is considered as
one of the sub-sets of such communication transceivers.
Over the last few decades, there have been many different
structures of latch and flip-flop circuit including static,
dynamic, transmission gate, clocked CMOS etc. However,
those structures have their limitations when it comes to steer
high speed data. So, we noted a shift of focus towards CML
due to its superior performance in terms of speed compared
to other logic styles. This is because, the constant tail bias
current makes the transistors in saturation mode unlike
CMOS logic where transistors are forced back and forth
between saturation and linear region. The MOS current mode
logic (MCML) style of D-latch has not only satisfied the
stringent speed requirements [1, 2]; but also reduces the
switching noise and supply fluctuations due to constant
current source, which has led to have high noise immunity
due to differential nature [2 - 4]. However, conventional
MCML has its own limitations such as static power
dissipation due to constant current source and that guides to
read higher power/Hz at low frequency. Secondly, it requires
complex fabrication process to manage the large load
resistors and reference voltage distribution tree thereby
leading to complex routing and larger chip area [1, 5]. To
eliminate the said shortcomings, we designed a new dynamic
CML based D-Flipflop, which runs easily at higher
switching frequencies and still burns lower power compared
to other existing designs.
II. MCML
L
ATCH
A. Conventional MCML Latch:
A current mode logic latch is shown in figure 1, which
consists of a sample and hold state at either logic levels of
clock signal. In the tracking mode, transistor pair N1 and N2
is used to sense information and transistor pair N3 and N4 is
used to store the data. When clock is high at the Gate of N5,
the circuit is operated in tracking mode; but when clock is
low, N6 turns on to activate hold pair transistor. But this
design suffers from functional failure due to smaller gain in
latch section when switching at higher frequencies [6]. Also,
the tracking operation guides to an increase in capacitance of
N1 and N2 thereby curbing down the small signal gain of
tracking.
B. Proposed MCML D-Latch Circuits:
The proposed current mode D-FF intending to achieve
higher speed and dissipate low power is shown in figure 2,
which eliminates the requirement of reference voltage for
constant current, rather employs a dynamic current source
guided by Clock signal. The MOS transistor pair M4 and M5
is driven by the differential input ‘D’; while the cross
coupled PMOS pair M1 and M2 preserve the value after
evaluation thereby holding the data. The MOS transistor M6
and (M0 and M3) are serving dynamically as tail transistor
and pull-up resistors thereby controlling the current flow.
During the low phase of clock, the transistor M0, M3 and
M6 turn ON and therefore one of the output nodes drops the
voltage than other node depending on the differential input.
During this phase (evaluation), when one of output nodes
drops lesser than (V
DD
-V
tp
), either of M1 and M2 turns ON
thereby making the other OFF and this speed up the
evaluation process. When the clock is set high, the transistors
M0, M3 and M6 are steered to OFF state and then the cross-
couple transistor pair work to hold state.
Fig. 1. Conventional CML Latch
Fig. 2. Proposed D-latch circuit

C. Performance of the new Dynamic CML Latch:
Figure 3 shows the clock to output delay and data to
output delay as a function of data to clock delay for both
conventional and proposed D-latches. It is to note that clock
to output delay of the proposed design increasing linearly
with data to clock delay and the value is lesser than that of
conventional one. However, the data to output delay is found
to be almost independent of data to clock distance and way
lesser in magnitude than the conventional latch. This
concludes our design to achieve higher data rate. Also, this
design reads a small power 87.43µW thereby proving its
worth for low power application.
Fig. 3. Delay analysis against Data-Clock delay.
III. D
YNAMIC
C
URRENT
M
ODE
D-FF
In order to achieve good performance, the newly
developed dynamic current mode D-Latch is employed to
structure a Master-Slave D-FF as displayed in figure 4(a),
which is formed by cascading a positive level triggered D-
Latch to one negative level triggered D-Latch. In this case, it
is a negative edge triggered flip-flop. The physical design is
carried out (refer figure 4(b)) and the layout estimates an
area of 108.624µm
2
(16.045µm × 6.77µm). The transient
analysis of post-layout simulation is shown in figure 4(c),
which justifies the working of the design.
IV. S
IMULATION
R
ESULT OF
P
ROPOSED
DFF
The simulation of the new design is performed using
Synopsys H-Spice under the following environments:
CMOS Technology = 90 nm
Supply Voltage (V
DD
) = 1.2 V
Clock Frequency (F
CLK
) = 10 GHz
Differential Input (Periodic) = 2.5 GHz
Temperature = 25
0
C
A. Performance Metrics at Different Process Corners:
The performance parameters such as delay, power
dissipation (P
avg
), and power-delay-product (PDP) of the
proposed circuit are evaluated at different corners for ‘no
skew’ condition and is summarized in table I for both
schematic and post-layout simulation. The metrics computed
for post-layout case are observed as a deviation of 71.98%,
17.93% and 102.66% from pre-layout result in nominal (TT)
corner. However, the alteration of each metric as a function
of corner is relatively small, thereby proving the design to be
a resilient one.
T
ABLE
I.
ANALYSIS OF PERFORMANCE METRICS
Corners Delay (ps) P
avg
(µW) PDP (fJ)
SCHEMATIC
TT 18.20 185.74 3.38
FF 17.40 192.50 3.34
FS 18.60 183.04 3.40
SF 18.00 188.39 3.39
SS 19.30 179.40 3.46
LAYOUT
TT 31.30 219.05 6.85
FF 29.20 226.50 6.61
FS 31.80 216.88 6.89
SF 30.70 220.52 6.77
SS 33.60 211.53 7.10
B. Metrics as a Function of Temperature:
The temperature dependency of the circuit performance
parameters such as delay, average power and PDP are
evaluated at nominal corner and their values at three different
temperatures (0
0
C, 25
0
C & 90
0
C) are shown in figure 5. The
(a) (b)
(c)
Fig. 4. New Dynamic Current Mode MS-DFF (a) basic block (b) layout @ 90nm and (c) transient analysis

circuit metrics are noted to be almost unaltered against
temperature variation in both pre-layout and post-layout
case. It’s a known fact that higher the temperature, slower
the circuit is going to run, which implies the decrease in
mobility with the rise in temperature, thereby reducing
current and hence the power. This is validated from figure 5.
Fig. 5. Delay, average power and PDP analysis at different temperature
V. C
ONCLUSIONS
:
In this paper, a new dynamic current mode power
efficient MS-DFF is unveiled to achieve higher data rate.
The D-Latch circuit is countered against the conventional
design and proved to be a better candidate to build MS-DFF
for high speed application. Analyses are carried out as a
function of process corners and temperature to prove the
reliability of new design. The new D-FF could prove its
worth to be a potential candidate for designing a decision
circuit present in clock and data recovery module of high-
speed serial link.
A
CKNOWLEDGMENT
The authors acknowledge Ministry of Electronics and
Information Technology (MEITY), Govt. of India for
financial support under SMDP C2SD project.
R
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