Scaling Challenges of Floating Gate Non-Volatile Memory and Graphene as the Future Flash Memory Device: A Review

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REVIEW
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Journal of
Nanoelectronics and Optoelectronics
Vol. 14, pp. 1195–1214,
2019 www.aspbs.com/jno
Scaling Challenges of Floating Gate Non-Volatile
Memory and Graphene as the Future Flash
Memory Device: A Review
Afiq Hamzah∗, Hilman Ahmad, Michael Loong Peng Tan, N. Ezaila Alias,
Zaharah Johari, and Razali Ismail
With the increasing number of electronic consumer and information technology, demands for non-volatile
memory rapidly grow. This study comprehensively reviewed the challenges related to the floating gate tran-
sistor for each component of the gate stack that consists of the tunnel oxide layer, inter-poly dielectric (IPD)
oxide layer and poly-Si floating gate until reaching its bottleneck as the floating gate thickness scale to 7 nm.
By going through the development of flash memory from its early year, the issues of the floating gate structure
are identified. In resolving these issues, several approaches and upcoming flash memory devices are pro-
posed. The prospect of carbon-based floating gate devices covering the graphene flash memory (GFM) and
the vertical CNTFET floating gate are thoroughly discussed; reviewing its device performance and transient
characteristics, which were extracted from experimental works and compared with recent upcoming technolo-
gies such as the HFG and the three-dimensional (3D) vertical flash memory. Reports indicate that graphene
flash memory (GFM) capable of rivaling with the upcoming hybrid floating gate (HFG) device. It is found that
the carrier concentration, transient characteristics and memory window of GFM are very much comparable to
the HFG. Attributes to the high density of states (DOS) of graphene, GFM managed to lower its operating volt-
age while achieving comparable memory window as HFG. In the case of CNTFET with nanocrystal floating
gate, the device performance is lesser than the 3D vertical flash memories in terms of its short channel effect
and gate capacitance ratio. But considering its nanometer structure that has ballistic properties, better device
performance with a proper definition of metal contact and synthesis can be achieved. Finally, the advantages
of using graphene as floating gate are concluded and future work to improve the CNTFET floating gate is
proposed.
Keywords: Floating Gate MOS (FG-MOS), Floating Gate, Tunneling Oxide, Inter-Poly Dielectric (IPD), Gate Stack,
Graphene Flash Memory (GFM), Hybrid Floating Gate (HFG), Gate-All-Around (GAA), Vertical 3D Flash Memory.
CONTENTS
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2.FlashMemory ............................... 3
3. Floating Gate Non-Volatile Memory Technologies . . . . . . . . . 4
4. FG-NVMBasicConcepts ......... ............... 7
5. Related Issues in Conventional FG-MOS . . . . . . . . . . . . . . 10
6.GrapheneFlashMemory......................... 13
7.3DVerticalFlashMemory ....................... 15
8.DiscussionandConclusion ....................... 17
School of Electrical Engineering, Faculty of Engineering, Universiti
Teknologi Malaysia, 81310 Johor, Malaysia
∗Author to whom correspondence should be addressed.
Acknowledgments ............................. 18
ReferencesandNotes........................... 18
1. INTRODUCTION
Moore’s law has led to the advancement of high-speed
logic computing, increasing number of electronic con-
sumer and information technology that urge for higher data
storage capability. It is expected that each and every person
in this world to have approximately 1 billion transistors
as compared in 1968, where only one transistor per per-
son [1]. Memory as one of the constituents of electronic
devices has been constantly developed in conjunction to
massive and high-speed applications. It is used in many
consumers’ electronic appliances where encoded data is to
Email: mafiq@fke.utm.my
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Scaling Challenges of Floating Gate Non-Volatile Memory and Graphene as the Future Flash Memory Device: A Review Hamzah et al.
Memory
Non
Volatile
ROM
PROM EPROM
EEPROM
FLASH
NOR NAND
Volatile
RAM
Static Dynamic
Fig. 1. Memory devices based on complementary metal-oxide-
semiconductor (CMOS) technology.
be stored and retained as digital information inside mem-
ory devices. Generally, memory devices are divided into
two categories, which are volatile and non-volatile mem-
ory. Volatile memory is a form of memory that loses data
when the power is off. It is also known as Random-Access-
Memory (RAM) with very fast read and erase time.
Dynamic-RAM (DRAM) and Static-RAM (SRAM) are
the most commonly known volatile memory. Non-volatile
memory (NVM) is a form of memory that preserves data
even when the power is off. It is also known as Read-
Only-Memory (ROM). NVM can retain a massive amount
of data but at low write and read speed. Mask ROM,
Programmable ROM (PROM), Erasable PROM (EPROM),
Electrically Erasable-Programmable ROM (EEPROM) and
Flash Memory are the types of non-volatile memory. These
are based on metal-oxide-semiconductor (MOS) technol-
ogy. There are also other technologies being used to store
data. Optical devices such as compact-disk ROM (CD-
ROM), digital-versatile-disc RAM (DVD-RAM) and fer-
roelectric technology such as the well-known hard-disk
drive (HDD) are employed as dominant secondary mem-
ory, in which these are commonly used to store digital
information.
An ideal memory device is to have high capacity and
speed, low power consumption, being non-volatile, ran-
dom access, and can be acquired with a cheap price. How-
ever, it is seemingly impossible due to the limitation within
CMOS technology itself. Each memory has its own capa-
bility. Volatile memories such as SRAM and DRAM have
the random-access capability and high Write/Erase (W/E)
speed. On the contrary, they have low storage and need
to be frequently refreshed to maintain their actual state
that led to high power consumption due to its volatility.
NVMs offer different opportunity and capable of cover-
ing a wide range of applications, from consumer electronic
products, communication and also in the automotive indus-
try. It can be qualitatively compared in terms of usage and
cost. The early mask ROM is physically programmed by
the manufacturer and cannot be re-written as the main pur-
pose stand by its name, which is read-only. Then, with the
advancement in semiconductor industry through floating-
gate MOS, there is EEPROM. EEPROM provides with a
practical usage of memory that conducts W/E operation
by applying an electric field. Furthermore, it also provides
with byte-wise random access capability that made EEP-
ROM a key figure in the memory industry. Nevertheless,
since EEPROM consists of two transistors (2T) per cell, it
has made the device becoming highly expensive for mas-
sive storage application [2]. Flash memory is another type
of NVM that was developed from EEPROM. There are
two types of flash memory, NOR flash and NAND flash.
Instead of having 2T per cell, flash only has 1 transis-
tor (1T) per cell. This has been a major revolution that
steered the course of memory industry for high capacity
storage. Because of its 1T per cell, the price has been
greatly reduced with while having high storage capacity.
NOR flash has very much similar performance as the pre-
vious EEPROM except for its cheaper price. It is suitable
to be used as a code storage device due to the execute-
in-place (XiP) capability. Meanwhile, NAND flash serves
a difference purpose by storing a massive chunk of data.
It has slow read and W/E speed that executes by page.
Table I below summarizes the performance for each of
these devices and its application.
The major success of the memory device goes down to
the evolution of a CMOS technology memory cell namely
the floating gate MOS (FG-MOS). It has been the back-
bone for the development of memory devices, especially
in flash memory. Incongruent with MOS Field-Effect-
Transistor (MOSFET) miniaturization, it is impossible for
the FG-MOS to escape from fundamental issues that haunt
the device performance when scaled below 10 nm node.
One of the major issues is because the tunneling oxide
and the Inter-Poly Dielectric (IPD) oxide thickness barely
scaled between technology nodes. Therefore, it is diffi-
cult to scale the conventional wrap-around planar device
structure when the bit line spacing having a half-pitch
size of 19–20 nm [3]. From 28 nm to 24 nm half-pitch
contact, the IPD thickness scaled from 11 nm to 10 nm
respectively, while the tunneling oxide maintains its thick-
ness in the range of 6 nm–7 nm to maintain the wrap
around FG structure. International Technology Roadmap
for Semiconductor (ITRS) 2014, on their report on Process
Integration, Devices and Structure predicted that further
scaling of IPD layer thickness will saturate at 9 nm with
22 nm DRAM half-pitch. Referring to ITRS table, two-
dimensional (2D) planar NAND flash scaling is expected
to saturate at 10 nm node with IPD thickness stops at 9 nm
and tunneling oxide stops at 5–6 nm [3]. This prediction
is supported by memory manufacturers such as Sandisk,
Samsung, Micron and SK Hynix. Figure 2 shows the gen-
eral guidelines from companies that converged at 10 nm
node. Decreasing the half-pitch size below this value will
degrade the gate capacitance ratio (GCR) below 0.6 that
speed up the charge retention time and increase the cell-
to-cell interference effects.
Nevertheless, the usages of FG structure and charge
trapping memory cells are still relevance due to the mass
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Hamzah et al. Scaling Challenges of Floating Gate Non-Volatile Memory and Graphene as the Future Flash Memory Device: A Review
Tab l e I . Shows the performances between memories.
FLASH
SRAM DRAM Mask ROM EEPROM NOR NAND
Non-volatility N N Y Y Y Y
Erasable Y Y N Y Y Y
Programmable Y Y (factory) Y Y Y
Smallest write Byte Byte N/A Byte Byte Page
Smallest read Byte Page Byte Byte Byte Page
Read speed Very fast Fast Fast Fast Fast Slow
Write speed Very fast Fast N/A Slow Slow Slow
Active power High Med Med Med Med Med
Sleep power Very low High 0 0 0 0
Price/GB High Low Very low High Low Very low
Applications Small storage and fast. Main memory Stable code volume Serial number Code Data storage
production of the CMOS technology. However, the limi-
tation in Si-based technology has opened the opportunity
for new material to step up as a successor. The emerging
carbon-based materials namely graphene, carbon nanotube
(CNT), graphene nanoribbon (GNR) and graphene nano-
scroll (GNS) have gained momentum across various fields
of research. Graphene is a zigzag chain with 120angle
through sp2hybridization to form a single layer honey-
comb lattice structure. It is materially light, low dimension
and its electronic properties that depend on their geom-
etry variations are unique to solid state physics. Their
band gap can be varied from 0 eV to 1 eV to exhibit
either metallic or semiconducting behavior by changing
its helical geometries. In addition, they also show high
mobility transport. Suspended graphene demonstrates up
to around 1,000,000 cm2V−1s−1while intrinsic CNT is
around 200,000 cm2V−1s−1, prompting to be suited apply
for high-speed logic operation. Interestingly, carbon-based
devices show hysteretic behavior by sweeping the gate
voltage [4, 5]. CNT has been used as channel material with
SiO2is utilized as the charge trapping layer. This indicates
that CNT is very promising to be utilized as a memory cell
in continuing the CMOS technology below 10 nm node.
If this is possible, 1D material such as CNT is capable to
achieve memory density of up to Terabits/cm2[6]. Subse-
quently, the W/E voltage can be downscaled and reduce
the power consumption [7]. Moreover, graphene and mul-
tilayer graphene (MLG) have been used to replace the
poly-Si floating gate [4]. Researches showed that MLG
with a high-density of states (DOS) is capable of storing
a great number of charge, which results in large memory
window of more than 6 V [8–11].
Although most experts believe that silicon will maintain
their domination in the semiconductor industry for the sub-
10 nm node, there have been severe fundamental issues
arose beyond this node that prevents the establishment of
silicon for flash memory applications. Limitations encoun-
tered by flash memory in achieving high capacity and low
cost prompting for an alternative memory device. There-
fore, the aim of this review is to present various issues
related to the current floating gate structure highlighting
each segment of the memory cells from the oxide layer,
channel and floating gate material. In conjunction with the
emergence of carbon-based materials and the 3D vertical
floating gate structure, related issues and potential candi-
dates for replacing the conventional floating gate memory
cell are discussed.
2. FLASH MEMORY
Flash memory has been vastly used in today’s electronic
consumer devices. Figure 3 shows the memory storage
capacity exponentially increased throughout the years,
which is consistent with Moore’s law of doubly increase
the number of transistor in every 18 months. More than
70% of flash memory architecture based devices such as
Fig. 3. A number of storage capacity exponentially increase throughout
the years with storage application devices is the highest.
Fig. 2. Shows the general guidelines of NAND flash from manufactur-
ers. 2D planar NAND flash s caling s tops at 10 nm node.
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Scaling Challenges of Floating Gate Non-Volatile Memory and Graphene as the Future Flash Memory Device: A Review Hamzah et al.
solid states drive (SSD), mobile phone, Universal Serial
Bus (USB) flash and flash memory cards are being dom-
inantly used by electronic consumers, justified the expec-
tation of flash memory usage exceeding 50% of device
application [12]. Basically, there are two main usages of
flash memory. One is to integrate NVM to digital systems
such as cache in the central processing unit (CPU). Sec-
ondly, is to be used as storing elements such as SSD, flash
memory cards and USB flash drives.
3. FL OATIN G G AT E NO N- VOL AT IL E
MEMORY TECHNOLOGIES
The concept of having a bi-stable state in Field-Effect-
Transistor (FET) that was initially originated by Professor
W. B. Shockley and Pearson has inspired Sze and Kahng
to the idea of a charge storing transistor in 1967 [13]. This
has been the foundation to the non-volatile MOS memory
devices. They introduced the concept of memory transis-
tor started from a basic MOSFET structure by tweaking
the gate stack that consists of a semiconductor channel
layer, thin-film oxide layer I1, a floating embedded metal
gate layer M1, a thick oxide layer I2and an external metal
gate M2as shown in Figure 4 [13]. It is known as MIMIS
(metal-insulator-metal-insulator-semiconductor). I1needs
to be thin enough to maintain high electric field during the
positive voltage pulse in allowing electron tunneling to M1
and into its conduction band while I2is thick enough pre-
venting the electrons tunneling through it. When the gate
voltage is removed, I1must be small enough to prevent
from backtunneling. A negative voltage pulse is applied to
discharge electrons from M1.
Both charging and discharging of the floating gate M1
is by direct tunneling mechanism. It required a very thin
oxide layer (<10 nm) with fewer defects, which is difficult
to achieve during the time. The presence of defects during
the fabrication causing the charge-stored in M1to tunnel
back into the substrate and therefore, could not be realized.
Nevertheless, the duo contributed with the basic concept of
Fig. 4. Shows the structure of MIMIS. Program and erase operation
is performed by direct tunneling mechanism through I1(adapted with
permission from [13], Kahng, D. and Sze, S.M., 1967. A floating gate
and its application to memory devices. Bell Syst. Tech. J., 46, pp.1288—
1295. Copyright@Nokia Bell Labs).
NVM that still holds until today, which led to the develop-
ment of the floating gate and the charge-trapping devices.
To solve the technological constraint in MIMIS cell, two
possible improvements were taken. First is by replacing
the floating gate M1with a dielectric layer, which has
been the foundation of charge-trapping devices and sec-
ondly, by increasing the tunneling oxide thickness I1,so
that other tunneling mechanisms instead of direct tunnel-
ing is inevitable.
The metal-nitride-oxide-semiconductor (MNOS) cell
was introduced by Wegener et al., in the same year as
MIMIS [14]. With respect to the first approach, MNOS
employed a nitride layer in replaced of I2and M1in
MIMIS cell (refer Fig. 5). The nitride layer of Si3N4is
used as the “storage compartment” that can capture holes
and electrons. The device will not suffer from a com-
plete discharge of carriers since it is being individually
isolated from one another by the nitride layer. MNOS is
programmed by applying a high positive voltage to the
gate so that the electrons from the channel can tunnel to
the nitride conduction band and trapped by nitride traps,
resulting in a positive threshold voltage shift. While the
erase operation is performed by applying a high negative
voltage in allowing holes from the channel valence band
to tunnel into the nitride layer and neutralizes the nitride
traps, resulting in negative threshold voltage.
Increasing the tunneling oxide thickness, I1has been
widely used in NVM devices. This approach has led to
the realization of the first operating floating gate device
in 1971, introduced by Frohman-Benthckowsky as Float-
ing Gate Avalanche Injection MOS (FAMOS) [15]. Instead
of using metal layer M1in MIMIS, FAMOS embeds a
poly-Si as its floating gate covered by a thick 100 nm
oxide layer. It is originally a p-channel device without
the control gate M2(refer Fig. 6). FAMOS cell injection
mechanism is based on energetic electrons in the chan-
nel by applying avalanche plasma in drain region below
the floating gate causing electron drift from the drain into
the floating gate. This is due to the positive oxide field
Fig. 5. The structure of MNOS cell. The Si3N4layer is employed
instead of a floating gate as the “storage compartment” (adapted with per-
mission from [14], Wegener, H.A.R., et al., 1967. The Variable Thresh-
old Transistor, a New Electrically-Alterable, Non-Destructive Read-Only
Storage Device. 1967 International Electron Devices Meeting, Vol. 13,
1198
p.70. Copyright@IEEE).
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Hamzah et al. Scaling Challenges of Floating Gate Non-Volatile Memory and Graphene as the Future Flash Memory Device: A Review
Fig. 6. FAMOS cell consists of poly-Si floating gate covered by a
~1000 Å thick oxide layer without the control gate. A high negative volt-
age is applied at the drain during programming and it can only be erased
by UV or X-ray exposure (adapted with permission from [15], Frohman-
Bentchkowsky, D., 1974. FAMOS—A new semiconductor charge storage
device. Solid State Electronics,17, pp.517–529. Copyright@Elsevier).
induced by capacitive-coupling between the floating gate
and the drain. The avalanche plasma is induced by apply-
ing such high negative voltage to the drain causing hot
electrons emission through the thick tunneling oxide layer
into the floating gate. This mechanism is known as a hot-
carrier injection (HCI) [15]. FAMOS is the first memory
cell to be commercially used and manufactured as EPROM
that earned the inventor Frohman with a Nobel prize in
physics [16]. Unlike PROM, EPROM is erasable by expo-
sure to ultra-violet (UV) or X-ray irradiation. However,
this has been its major drawback, possibly due to the lack
of an external gate causing no field emission to electrically
discharge the electrons in the floating gate. Moreover, the
programming process is not efficient.
In order to alleviate the drawback in FAMOS, an exter-
nal gate is added. Stacked Gate Avalanche Injection MOS
(SAMOS), proposed by the father of flash memory Fujio
Masuoka [17], is a memory cell that mimics the form of
FAMOS but with the addition of an external electrode as
a control gate, shown in Figure 7 [17, 18]. The addition
of the control gate has effectively improved FAMOS pro-
gramming speed and efficiency due to the increase of
drift velocity of electrons in the oxide layer, combining
with an energy barrier lowering at the Si–SiO2interface
and a decrease of avalanche breakdown voltage. Electrical
erasure of the floating gate is achieved through Fowler-
Nordheim tunneling effects [18]. Subsequently, follow-
ing the advancement in thin-film technology by Harari
et al. [19], has led to the invention of EEPROM in 1976,
having thin tunneling oxide of 20 to 100 Å [20]. EEPROM
has been commercially manufactured and widely used to
store small data, calibration or parameter information that
needs to be retained during power loss.
Later in 1984, transitions from EEPROM to flash EEP-
ROM take place. Flash EEPROM resembles the combina-
tion of EPROM and EEPROM. It inherits the W/E speed
and 1T per-bit of EPROM and the endurance of EEPROM
as compared in Table II. By having one transistor per bit,
flash memory has a larger amount of storage and cheaper
price than EEPROM. Moreover, it also provides random
access capability in order to change the memory state of
a single bit or page. Unlike EEPROM, the erase operation
needs to be executed to the whole chip.
Flash memory was originally invented by Toshiba’s
F. Masuoka in 1984. It has 256 Kbit storage, which was
fabricated using 2.0 m conservative design rule. The
name “flash” was suggested to Dr. Masuoka by his col-
league, Mr. Shoji Ariizumi because of the erase operation
that imitates the flash of a camera. The memory struc-
ture is based on triple poly-Si technology that consists of
the erase gate, floating gate and control gate as shown in
Figure 8 [24].
The injection mechanism is based on hot-carrier injec-
tion by applying a high gate voltage to the metal contact.
While erasure is based on Fowler-Nordheim tunneling to
induce field emission at the floating gate by applying a
high voltage at erase gate. However, due to the incon-
sistent treatment of thin-film oxide and Fowler-Nordheim
tunneling, the product failed to be commercialized. Never-
theless, the concept and the architecture of flash EEPROM
is proven to be the pivot point for NVM industry.
In transpiring the concept of flash memory, in 1987,
Toshiba has invented the NAND flash memory, fabricated
using the conventional double poly-Si gate technology [25]
that comprises floating gate and control gate separated by
a thick interpoly dielectric layer (IPD) layer of 200 Å [26].
Original NAND flash architectureisanarrayoffloating
gate transistors connected in series without a select tran-
sistor, as shown in Figure 9, which has 4 cells per bit line
string using 1.0 m process node to form 4 M bit storage.
It is programmed using HCI and erased by Fowler-
Nordheim Tunneling. Stand by its name, NAND architec-
ture flash memory behaves like a NAND logic gate. The
bit line output is pulled low (no current flow) when all
the memory cells across the bit line string are pulled high
Fig. 7. Stacked avalanche-injection MOS (SAMOS) structure with
the addition of 2nd poly-Si as a control gate while maintaining the
form of FAMOS such as thick tunneling oxide layer (∼1600 Å)
(adapted with permission from [18], Iizuka, H., et al., 1976. Electri-
cally alterable avalanche-injection-type MOS read-only memory with
stacked-gate structure. IEEE Trans. Electron Devices, 23, pp.379–387.
Copyright@IEEE).
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Scaling Challenges of Floating Gate Non-Volatile Memory and Graphene as the Future Flash Memory Device: A Review Hamzah et al.
Table II. Performance comparison between EEPROM and NOR flash EEPROM.
EPROM [21] EEPROM [22] NOR Flash EEPROM [23]
Number of transistor per bit 1T 2T 1T
Memory size 2 M×8 b (0.6 um technology) 128 K ×8 b (0.8 um technology) 2 M ×8 b (0.6 um technology)
Chip size 7.18 mm×17.39 mm 11.83 mm ×7.73 mm 6.3 mm ×18.5 mm
Cell size 2.2 um×1.75 um 3.8 um ×8um 1.7um×2.0 um
Access time 63 ns 120 ns 58 ns
Programming time/word 5 us 8 ms 5 us
Erase/write cycles (Endurance) 100 105103to 105
(current flow). The string is programmed by biasing the
drain with 9 V voltage bias and the selected bit is supplied
with 10 V gate voltage while the unselected bit is supplied
with 21 V gate voltage. No threshold shift is observed for
a long period of time of ∼104.
Seeing the potential of NAND flash memory, in 1988,
Intel started to develop a NOR architecture flash memory
based on simpler cell structure by the name of EPROM
tunnel oxide (ETOX) which has been the standard for the
cells scalability [27]. It uses similar double poly-Si gate
technology as in Ref. [26] but with thinner tunnel oxide
layer of ∼100 Å. The thin tunnel oxide layer provides fast
program and erase operations, which adequately prevents
charge loss from the floating gate. The injection mecha-
nism is also based on HCI for programming and Fowler-
Nordheim tunneling for erasure. The output bit line of
NOR flash is pulled high when all the memory cells is
pulled low. In contrast to NAND flash, NOR flash memory
cell is individually grounded at its graded source junction,
as shown in Figure 10, to facilitate high voltage to the
junction for erase operation.
Common ground NAND and NOR memory array archi-
tectures have been commercially used in the mid-1980s
in many applications. Both devices have their own advan-
tages and disadvantages, depending on its usage. NAND
flash array is assembled in a block that consists of a
Fig. 8. Triple poly-Si gate stack of erase gate, floating gate and control
gate with aluminum word line contact. The erase gate voltage of 30 V is
applied to discharge the electrons at the floating gate and grounded dur-
ing program and read operations (reproduced with permission from [24],
Masuoka, F., et al., 1984. A New Flash E2PROM Cell Using Triple
Polysilicon Technology. 1984 International Electron Devices Meeting,
Vol. 30, pp.464–467. Copyright@IEEE).
Fig. 9. Depicts the architecture of NAND flash memory invented
in 1987 that consists of 4 bit per string (adapted with permission
from [25], Samachisa, G., et al., 1987. A 128 K Flash EEPROM
Using Double Polysilicon Technology. In Solid-State Circuits Confer-
ence. Digest of Technical Papers. 1987 IEEE International, pp.76–77.
Copyright@IEEE).
number of pages (word lines). Erasing a single block will
set all bits to state 1, making NAND flash has fast W/E
operation since it is performed block-wise. It is suitably
used as a mass storage device in regard to its small cell
size of 4 F2(‘F’ is the half-pitch size between uncontacted
poly-Si), which is the smallest amongst silicon-based
memory technologies. Therefore, it can be densely packed
into a single chip of memory array to form high-density
Fig. 10. Depicts the architecture of NOR flash memory invented in
1988 by Intel. Notice that source junction in each cell is grounded
(adapted with permission from [27], Verma, G. and Mielke, N., 1988.
Reliability Performance of ETOX Based Flash Memories. 26th Annu.
Proc. Reliab. Phys. Symp., Vol. 1988, pp.158–166. Copyright@IEEE).
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Hamzah et al. Scaling Challenges of Floating Gate Non-Volatile Memory and Graphene as the Future Flash Memory Device: A Review
memory devices such as Solid-State Drive (SSD), flash
drive and micro SD card. On the other hand, NOR flash is
a byte-wise device, which made it capable of fast READ
and W/E operation can be executed by bit. In addition, it
can also perform WRITE and READ operation simulta-
neously. This proves to be very useful for microcontroller
unit (MCU) that frequently undergoes many bit changes.
However, the device suffers from W/E operation speed,
especially for a large storage device. NOR flash is used
to store program codes due to its fast random-access and
W/E operation. In regards to the XiP operation, early NOR
flash has been implemented in computer’s BIOS and as a
firmware. However, in order to have fast random access
and W/E operation, each source junction of NOR flash’s
cell needs to be individually connected to ground causing
the cell size of about 10 F2. The device comparisons of
NAND and NOR flash are shown in Table III below.
With the ever-increasing electronic consumers and
demands, FG structure continues to be further downscaled
and multi-level cells (MLCs) have been adapted to increase
the memory density. In 1995, Bauer et al., from Intel Co.
managed to develop the 32 Mb NAND flash memory using
16 Mb memory cells [28]. Further scaling of the conven-
tional FG structure reached its bottleneck when scaling
below 20-nm node with cell-to-cell interference affecting
the memory reliability. This is due to the limitation of
the IPD layer to wrap around the floating gate, which has
reduced the coupling capacitance and caused a severe drop
to its GCR. Fortunately, the advancement in high-K dielec-
tric technology implemented by Intel for its 45-nm node
Table III. Comparisons between NAND flash and NOR flash.
NAND NOR
Cell array
Layout
Cross section
Cell size 4 F210 F2
Advantages Fast W/E •Fast random access
•Capable bytes program
•XiP
Disadvantages Slow random access Slow W/E
Applications Capable of storing large sequential data (data, video, voice). Store program code.
manages to crack the issue. Intel Micron Flash Technolo-
gies (IMFT) has implemented the high-K stack instead of
IPD layer. Metal control gate was also implemented, but
with a cost of narrowing the floating gate. By using this,
they have managed to scale the flash memory into 16-nm
half-pitch. FG structure is still a sensible choice for NAND
flash future application due to its CMOS compatibility in
making high-density storage device.
4. FG-NVM BASIC CONCEPTS
Consider the conventional FG-NVM with p-substrate as
shown in Figure 11. This structure has been widely used
to electrically program and erase information via carrier
tunneling through the tunnel oxide layer into the FG. Since
the FG is isolated by the wrap-around oxide layer, the
charges are trapped and remained even when the power
is off, which makes it non-volatile. The upper gate is
the control gate (CG) where the voltage pulse is applied.
Below the control gate is another gate that is being embed-
ded within the oxide layer, called the floating gate (FG).
Both gates are conventionally doped poly-Si. The tun-
nel oxide layer is a thin-film insulator of approximately
10 nm. It needs to be thick enough to resist the charge
from flowing to the substrate during retention period and
for the charge to tunnel into the FG during write opera-
tion. Another oxide layer situated in between the CG and
the FG is the inter-poly dielectric (IPD) layer that consists
of oxide-nitride-oxide (ONO). It is much thicker than the
tunnel oxide layer in order to withstand the high voltage
pulse applied to the gate and also to avoid the carrier from
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Scaling Challenges of Floating Gate Non-Volatile Memory and Graphene as the Future Flash Memory Device: A Review Hamzah et al.
N+ source N+ drain
P-Substrate
Floating Gate
Control Gate
CFG-CG
CTOX CFD
CFS
VCG
VD
VS
Vsub
Fig. 11. Shows the basic floating gate transistor architecture. CFG-CG ,
CTOX,CFD ,CFS represent the floating gate to control gate, tunneling oxide,
floating gate to drain and floating gate to source for each capacitance
respectively. VCG,VS,VDand Vsub represent the voltage terminal for con-
trol gate, source, drain and substrate respectively.
tunneling into the gate terminal during program operation.
Besides, it is essential in maintaining the GCR to be ≥0.6,
which heavily influences the W/E and read operation speed
of a FG device. CFG,CFS,CFSub ,andCFD are the termi-
nal capacitive coupling between the terminal (gate, source,
drain, and substrate) and the FG respectively.
Basically, FG device consists of three operations;
(1) write, (2) erase and (3) read. It can be signified by the
current flowing inside its channel. When the applied gate
voltage, VCG is much higher than its threshold, VT, current
will flow through the channel denoting bit ‘1’. At the same
time, high energy carriers will tunnel through the tunnel
oxide barrier and into the FG creating voltage drop across
the gate stack that increases the threshold voltage. When
VT≥VCG, the current will stop to denote bit ‘0’. These
operations can be understood by considering the capaci-
tive coupling of the device and its tunneling mechanisms
in finding the FG potential. The capacitive coupling of the
device is based on the charge equation of
Q=CV (1)
Then the charge in the floating gate node can be approxi-
mated as
QFG =VFG −VCG·CFG−CG +VFG −VD·CFD
+VFG −VS·CFS +VFG −VSub·CTOX (2)
VFG is the floating gate potential and VD,VS,andVSub are
the potential at each terminal drain, source and substrate
respectively. Given the total capacitance as CT=CFG−CG +
CFD +CFS +CTOX, the capacitance coefficient or coupling
ratio for each terminal can be denoted as i=CFi/CT
where the subscript iis the symbol of the terminal. Thus,
the VFG can be deduced as
VFG =GVCG +DVD+SVS+SubVSub +QFG (3)
Rearranging (3) to become
VFG =GVCG +DVD=CFG−CG
CT
VCG +fVD+QFG
CT
(4)
Consider that at initial condition there is no charge is
stored in the FG so QFG =0 with the source and substrate
terminal is grounded, VS=VSub =0.
VFG =G·VCG +D·VD=CFG
CT
VCG +f·VD(5)
where
f=CFD
CFG
(6)
Based from (5), the FG-MOS current–voltage (I–V)char-
acteristics can be obtained by using the conventional
MOSFET equations. It can be done by replacing the gate-
to-source voltage, VGS with (5) and modification is made
to the threshold voltage and the conduction parameter, k
n
with respect to VCG.GivenVTof FG-MOS as
VTfloating gate=G·VTcontrol gate(7)
and Kn
k
nfloating gate=1
G
·k
ncontrol gate(8)
The MOSFET I–Vcharacteristic equations in ohmic
region (OR) and saturation region (SR) are given as
ORVDS≤VGS −VT
IDS =k
n·VGS −VT·VDS −V2
DS/2(9)
SRVDS≥VGS −VT
IDS =k
nVGS −VT2(10)
By replacing (5), (7) and (8) into (9) and (10), the FG
device characteristics are obtained as
ORVDS≤G·VCG +f·VDS −VT
IDS =k
n·VCG −VT·VDS +f−1
2GV2
DS(11)
SRVDS≥G·VCG +f·VDS −VT
IDS =G·k
n/2VCG +fVDS −VT2(12)
It can be seen from (11) and (12), the I–Vcharacteristics
of FG device correspond to its control gate voltage; and
the boundary between ohmic and saturation is changed.
Comparison between both MOSFET and FG-MOS can be
made by plotting the I–Vcurve. Figure 12 below shows
the I–Vcurve for each devices [29].
It is observed that for conventional MOSFET, the drain
current saturates in negligence to the drain voltage incre-
ment. Unlike FG-MOS, saturation does not occur when
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Hamzah et al. Scaling Challenges of Floating Gate Non-Volatile Memory and Graphene as the Future Flash Memory Device: A Review
(a) (b)
Fig. 12. (a) I–Vcurve of the conventional MOSFET transistor shows saturation and the IDS independent of drain voltage when VDS ≥VGS −VT
(b) I–Vcurve of the FG-MOS transistor indicates no saturation as VGS is increased from 0 to 5 V with 0.5 V step and VT=05 V while the dotted
lines represent the model. The graph indicate strong dependencies of IDS on drain voltage due to the strong coupling between FG to the drain terminal.
Adapted with permission from [29], Wang, S.T., 1979.OntheI–Vcharacteristics of floating-gate MOS transistors. IEEE Transactions on Electron
Devices, 26, pp.1292–1294. Copyright@IEEE.
further exert to the VDS (refer Fig. 12). This is mainly due
to the capacitive coupling between the FG and the drain.
The device is fabricated with W/L =03 mm/0.3 mm, indi-
cates a strong coupling between the drain terminal to the
FG (CFD/CFG =0.35) while the source is weakly coupled
to the FG (CFS/CFG =0.05). Therefore, the I–Vcurve
obtained from FG-MOS deviates from the conventional
MOSFET which has weak gate-drain coupling. More
effects of FG-MOS have been highlighted by Ref. [29] in
contrast to the conventional MOSFET such as
(1) The channel may conduct current by drain voltage
during cut-off (VGS <V
Tand operate as depletion-mode
MOSFET. This effect is known as drain turn-on.
(2) The drain current does not saturate in the saturation
region and continue to rise as drain voltage increases as
shown in Figure 12(b).
(3) The boundary between ohmic and saturation region is
expressed as VDS=G·VCG +f·VDS −VT.
(4) The transconductance, gmin saturation region
increases with VDS, which is in contrast with the conven-
tional MOSFET transistor where the transconductance is
constant in the saturation region and relatively independent
of VDS.
gm=IDS
VGSVDS=constant
=G·KnVCG +f·VDS −VT(13)
(5) The capacitive coupling ratio, fin saturation region
only depends on CFD and CFG. It can be verified by
f=D/G=− VGS
VDS IDS=constant
(14)
by the existence of charges in the gate oxide layer which
depends on the device parameters. On the other hand, not
only that the FG-MOS threshold voltage depends on the
device parameter, but it is also affected by the surround-
ing terminal potential and the number of charges stored
in the FG. Consider the charge is to be stored in the FG
(QFG = 0). Biasing the CG will induce FG potential, VFG
which inverts the semiconductor channel. Subsequently,
the charge stored in the FG causes a voltage drop across
the gate stack and alter the threshold voltage. Given the
expression of the threshold voltage of MOSFET
VT=VFB +2fp +Q
trap
Cox
(15)
where VFB is the flat-band voltage, fp is the Fermi poten-
tial, Qtrap is the trap charge at the oxide-semiconductor
interface and Cox is the gate oxide capacitance. By insert-
ing the floating gate charge and its capacitance of the FG-
MOS to replace Qtrap and Cox respectively, the threshold
voltage is obtained as
VT=VFB +2fp +Q
FG
CFG
(16)
Then the threshold voltage shift VTis derived as
VT=VT−VT0 =−QFG
CFG
(17)
where VT0 is the threshold voltage at initial condition with
respect to its floating gate charge. It must be emphasized
that the number of charges per threshold voltage shift is
not primarily due to neither the physical size of the float-
ing gate nor from the overall floating gate capacitance, CT.
It is mainly due to the coupling capacitance at the control
gate, CFG which influences the number of electrons. To
achieve high number of stored charges, the CFG must be
increased as much as possible. This is done by increasing
One of the most important features of a memory cell is the
threshold voltage shifts, VT. It is an indication of charge
being stored in the FG. Conceptually, it is relatively simi-
lar to the trap charges, Qss that exists in the gate oxide of
a MOSFET transistor. The threshold voltage is increased
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the floating gate height and by decreasing the thickness of
the IPD layer. Increasing the floating gate height enhances
CFG and subsequently increases the gate capacitive cou-
pling ratio which needs to be more than 0.6. Decreasing
the IPD layer thickness can be implemented by employ-
ing high-Kdielectric constant which compensates the thin-
ner dielectric from causing charge loss and degrades the
retention time of the FG-MOS. In the next section, related
issues in conventional FG-MOS are described.
5. RELATED ISSUES IN
CONVENTIONAL FG-MOS
The flash memory capability in storing charge is compre-
hended by understanding the essence of a memory cell
structure and its mechanism. FG-MOS structure is the
common memory cell being implemented for 2D flash
memory architecture. Device miniaturization has led to
certain physical limiting factors and failure mechanisms
that degrade the device performances, endurance, and reli-
ability. Such failure mechanisms are the wearing effect,
floating gate thinning and gate leakage caused by the thin-
ning of IPD layer and tunneling oxide layer. There are
few issues on the gate stack that will be discussed in this
section based on each component of the FG-MOS, which
are the IPD oxide layer, tunneling oxide layer and its poly-
Si floating gate.
The IPD oxide layer is one of the important compo-
nents that influence FG-MOS reliability during program
operation. Basically, it is a layer consisting of oxide-
nitride-oxide (ONO) layer which isolates the floating gate
poly-Si from having direct contact to the control gate.
Due to certain physical limitation, ITRS has reported that
the thickness of the IPD oxide layer to be saturated at
9 nm [3]. The key feature of an IPD oxide layer is to
have good coupling between the control gate and the float-
ing gate (GCR ≥0.6) and to minimize the gate leakage
during program operation. Apparently, it does not scale
constantly with the half-pitch scaling, resulting in an incre-
ment of the electric field between neighboring cells due
to high wordline voltage. The equivalent oxide thickness
(EOT) of IPD oxide and tunnel oxide layers are barely
scaled between process technologies [3], in which the IPD
layer is expected to saturate at 9 nm thick while tunnel
oxide in the range 5–6 nm. In these contexts, with high
field stress and frequent W/E operation, poly-Si control
gate suffers from poly-gate depletion that increases the
gate capacitance series and subsequently reduces the cou-
pling capacitance [30]. In addition, with the poly-Si float-
ing gate distance closing each other has prompted in a
severe increase of parasitic capacitances between neigh-
boring cells, conjuring an abnormal cell-to-cell interfer-
ence as shown in Figure 13 [3]. These effects consequently
degrade the GCR and cause unstable bit state of the mem-
ory cell prior to threshold voltage variations. Furthermore,
thinning the IPD oxide will increase the charge leakage
Fig. 13. Shows the neighboring parasitic capacitance of a victim cell
due to half-pitch scaling causing unstable cell states and threshold voltage
variation. Adapted with permission from [31], Kim, Y.J., et al., 2014.
Effects of abnormal cell-to-cell interference on p-type floating gate and
control gate NAND flash memory. Japanese Journal of Applied Physics,
53, p.04ED12. Copyright@Institute of Physics.
during W/E operation causing the threshold voltage to sat-
urate at a certain limit due to charge tunneling through the
IPD layer and into the outer circuit or commonly known
as program saturation [32].
Several approaches have been taken to enhance the IPD
layer efficiency. Reducing the poly-Si surface roughness
to reduce trap charges is one of the approaches. Another
approach is by implementing high-kdielectric technology
in replaced of ONO layer for less than 19–20 nm half-
pitch technology.It was first adopted by Intel Micron Flash
Technology (IMFT) who insist on continuing using the
planar structure for its 20 nm technology NAND flash.
Deploying high-k/metal onto the gate stack has success-
fully scaled the memory cell by narrowing the poly-Si
floating gate width for below 20 nm process technology.
Moreover, instead of using the conventional wraparound
floating gate structure in maintaining the GCR level, good
combination of high-k/metal can also improve the GCR
without having to wrap-around the thin poly-Si floating
gate. It also offers voltage reduction that lowers the electric
field of the floating gate, subsequently reduces the para-
sitic capacitances in minimizing the cell-to-cell interfer-
ence. The addition of air gap between cells also performed
the same task in countering the effect of cell-to-cell inter-
ference to maintain the stability of the bit state. However,
with today’s aggressive NAND cell scaling, high-k/metal
technology will soon reach its limits. Even though the fully
planar high-k/metal technology has overcome several criti-
cal issues of the wraparound floating gate, the W/E voltage
scaling will soon reach its limit and increases the elec-
tric field between cell nodes that led to serious wordlines
breakdown.
The tunnel oxide layer is responsible for the electron
tunneling in and out of the floating gate. The key fea-
tures of a good tunneling oxide are to be able to have fast
charge transfer in/out the floating gate during W/E opera-
tion and thick enough in withholding the charge from leak-
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Hamzah et al. Scaling Challenges of Floating Gate Non-Volatile Memory and Graphene as the Future Flash Memory Device: A Review
ing back to the substrate body during retention. For fast
W/E operation, a high control gate voltage (i.e., ∼20 V) is
applied to yield high-field distribution in the oxide layer.
After a large number of W/E cycles took place, the quality
of the tunnel oxide layer will degrade. Scaling the tun-
nel oxide of a conventional wraparound floating gate has
reached its bottleneck. Similar case in IPD’s layer, the tun-
nel oxide thickness is barely scaled between technology
nodes [3]. Therefore, a high-stress electric field will cause
severe wearing effect due to electron tunneling. Frequent
W/E cycles using Fowler-Nordheim tunneling mechanism
in NAND flash has seriously deteriorated the insulator sur-
face and introduced the trap charges. This will steadily
increase the threshold voltage of a memory cell that led
to unstable bit-state condition and also increases the sub-
threshold swing (SS) and lower its transconductance [33].
Moreover, the presence of trapped charges has also yielded
stress-induced leakage current (SILC) effect that results
in poor data retention (refer Fig. 14(a)). It is based on
trap-assisted tunneling mechanism causing the electrons
to tunnel from the floating gate into the channel even at
low potential of insulator layer [2, 34]. Furthermore, the
wearing effect also contributes to the charge loss from the
floating gate. These signify that thinning the tunnel oxide
layer or scaling the conventional wraparound feature size
per se will severely reduce its effective oxide thickness
(EOT) due to the wearing effect and thus, increasing the
leakage current during retention as shown in Figure 14(b).
Report on the limitation of the SiO2tunnel layer sug-
gested that single trap charge for less than 8 nm thick with
high field stress will suffer a complete charge loss [34].
Other reports indicate 7 nm as a typical value for the
tunnel oxide thickness [35], whereas ITRS and Intel indi-
cate 6 nm as its limit [3, 30]. Extensive researches on the
limitation of tunnel oxide layer have been discussed. Bar-
rier engineering (BE) is the obvious solutions in replac-
ing the SiO2layer. There are two BE approaches. The
first approach is to form a triangular tunnel barrier. Tri-
angular or crested barrier approach accommodates lower
(a) (b)
Tunnel Oxide Field
Log Current
Retention Program/Erase
Retention goal
SILC
degrades
retention
Fig. 14. (a) The SILC phenomenon occurs due to trap-assisted tunneling mechanism resulted by the trapped charges at the tunnel oxide layer that
causes by W/E cycling. (b) Shows the gate current across the gate stack against the tunnel oxide field. SILC increases the leakage current during the
retention period.
barrier during charging and higher barrier during reten-
tion [30, 36]. It is formed by a configuration of dielectric
layers of high-k/low-k/high-k. This combination of dielec-
tric layers provides a low barrier for W/E operation and
high barrier during retention. The second approach is the
VARIable Oxide Thickness (VARIOT) [37]. Conceptually,
it is similar to the crested barrier but with an opposite
configuration of low-k/high-k/low-k(symmetric) or low-
k/high-k(asymmetric) [37]. VARIOT offers scalable W/E
voltage and faster W/E operation than the single SiO2
layer.
The main component of the FG-MOS is the floating
gate itself. Its highly-doped poly-Si floating gate works
as a storage compartment for storing charges. Unfortu-
nately, the limitation of IPD oxide thickness that led to
poly-Si floating gate narrowing has reduced the number of
stored charges as (refer Fig. 15). The number of charges
at the floating gate determined the width of the mem-
ory window/threshold voltage shift, Vth . With the decre-
ment amount of charges, the reliability during retention,
especially for a memory cell that exhibits narrow Vth
has been affected. One charge loss during retention will
severely reduce the memory window. In addition, a report
indicates that the poly-Si floating gate does not support
vertical scaling below 7 nm [38]. This is due to the ballis-
tic transport in highly doped poly-Si floating gate during
programming. As the floating gate size is being narrowed,
some electrons went ballistic through the IPD oxide layer.
In addition, its low work function has worsened the issues
causing severe charge loss during retention.
In order to further squeeze the feature size of the FG-
MOS is to have a fully planar floating gate structure as
shown in Figure 16. By using high-k/metal gate stack to
the expense of thin floating gate layer, IMFT has pushed
to 16 nm half-pitch scaling. Hybrid floating gate (HFG) is
another form of planar memory cell. It is a combination
of poly-Si/metal stack in replace of poly-Si only [39, 40].
Reports indicate that HFG is capable in suppressing the
ballistic current through the gate stack during program and
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Scaling Challenges of Floating Gate Non-Volatile Memory and Graphene as the Future Flash Memory Device: A Review Hamzah et al.
Fig. 15. Number of electrons decreases with feature size scaling.
reduce the cell-to-cell interference. It can be scaled to 4 nm
thickness, which is much thinner than conventional poly-
SI of 7 nm while suppressed the ballistic transport dur-
ing program [39–41]. A low-dimensional material has also
been prompted to be a stand-in replacement for the poly-
Si floating gate. It has been reported that graphene-based
(a) (b) (c)
Fig. 16. (a) The planarized poly-Si floating gate with metal control gate fabricated by IMFT for its 16 nm technology node. (b) Shows the ultra-thin
HFB structure consisting of in-situ steam generated (ISSG) oxide layer, 7 nm layer combination of n+poly-Si and TiN metal, a high-kAl2O3IPD
layer and n-type control gate. Adapted with permission from [40], Kar, G.S., et al., 2012. Ultra Thin Hybrid Floating Gate and High-kDielectric
as IGD Enabler of Highly Scaled Planar NAND Flash Technology. Technical Digest—International Electron Devices Meeting, IEDM, pp.2.2.1–2.2.4.
Copyright@IEEE. (c) A floating gate consisting 6–7 layers of graphene which consume 2–3 nm thick that further vertical scaling and reduce the cell-to-
cell interference. Reprinted with permission from [10], Bertolazzi, S., et al., 2013. Nonvolatile memory cells based on MoS2/graphene heterostructures.
ACS Nano,7, pp.3246–3252. Copyright@American Chemical Society Publisher.
N+ source N+ drain
P-Substrate
Poly-Si Floating
Gate
Poly-Si Control
Gate
IPD oxide layer
Tunnel oxide
1) Barely scale between technology
nodes.
2) Half-pitch scaling increases
coupling between floating gate
neighbors.
3) Increasing gate series
capacitance due to poly-Si depletion
effects.
4) Very thin IPD layer promotes
charge transfer during W/E
operation.
1) Barely scale between technology nodes.
2) Severe wearing effects for thickness <8nm with
high-field stress is applied increasing trapped charges.
3) Stress-induced leakage current (SILC).
4) Degrades device performances (SS and
transconductance)
1) Does not support vertical scaling below 7nm.
2) Further scaling increases ballistic leakage current at the gate
stack during programming.
3) Further scaling also reduces its density of states (DOS)
4) Narrowing of poly-Si FG, reducing its coupling capacitance
with drain/source reduce its GCR.
5) Low work function of poly-Si worsening the retention time.
Fig. 17. Summarized the issues related to the gate stack of the conventional wraparound FG-MOS divided into each component from IPD oxide
layer, poly-Si floating gate and tunneling oxide.
material such as 2D graphene [9, 10, 42, 43], and carbon
nanotube (CNT) [5, 44–46] able to yield wide memory
window.
Many issues have been highlighted for each component
of the floating gate transistor in giving brief indication and
idea to further improve the floating gate structure. All these
issues are summarized as in Figure 17.
Generally, the performance of a memory cell is divided
into two main categories, which are dc-(stationary) and
transient performances. The device performance of a mem-
ory cell can be characterized as in MOSFET device.
Parameters such as transfer and output characteristics,
subthreshold swing (SS), on-off ratio (Ion/Ioff ,gate
capacitance ratio (GCR), transconductance (gm, and con-
ductance (gdare analyzed. The transient performances
are accessed based on its W/E speed and voltage, and
its reliability (i.e., retention and endurance). The number
of charges injected to the floating gate will influence the
threshold voltage shift, in which depends on W/E voltage
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Hamzah et al. Scaling Challenges of Floating Gate Non-Volatile Memory and Graphene as the Future Flash Memory Device: A Review
and its charging time. Low W/E voltage and fast charging
time in obtaining large memory window are what defined
a good memory cell. The industrial standard of an FG-
MOS required ±20 V W/E voltages to obtain a mini-
mum of 1.5 V memory windows [8]. Such high voltage is
required to allow Fowler-Nordheim tunneling for fast W/E
operation. Therefore, it is important to optimize the speed
and the W/E voltage of the memory. The endurance is
assessed by observing its memory window variations after
numbers of W/E cycle. This is due to the introduction of
trap charges during W/E operations causing threshold volt-
age variation after each number of cycling that increases
the gate leakage current. The conventional FG-MOS can
endure approximately 104W/E cycles and it is predicted
to be further decreased to 50×103for sub-20 nm tech-
nology before the tunnel oxide breakdown [3]. Finally, the
retention of the memory cell in retaining the charges after
being programmed is assessed over time. Most NAND
flash devices are expected to retain the data for approxi-
mately 10 years after being programmed. These parame-
ters are very important in characterizing a newly developed
NVM cell for future application.
Next section discusses on the prospect of carbon-based
devices compared to the HFB and the 3D vertical float-
ing gate flash memories; in reviewing their device perfor-
mances and transient characteristics.
6. GRAPHENE FLASH MEMORY
With vast emerging low-dimensional materials in the semi-
conductor industry, carbon-based materials appear as one
of the prospects for resolving the physical limitation in
floating gate transistor. Several reports on carbon-based
materials especially graphene and CNT indicate an early
sign of hysteresis using back-gated device structure mainly
due to the existence of water molecules [47, 48]. Nonethe-
less, this phenomena has prompt carbon-based materials
for memory device application [7, 48–51]. Fuhrer et al.,
has shown, not only that Catalytically Vapor Deposition
(CVD) synthesized CNT to exhibit high hole mobility of
∼9000 cm2V−1s−1, but it also demonstrated wide hys-
teresis of 6 V when the gate voltage is sweep between
±10 V [5]. Early observation indicates that Graphene
Nanoribbon (GNR) exhibits hysteresis when subject to the
voltage pulse of ±10 V yielding stable pulse test out-
put at various clock rates below 10 kHz, which is an
indication for long endurance cycles of >107[51]. Further-
more, there are other characteristics and parametric per-
formances that highlight the performance of carbon-based
FET for floating gate non-volatile memory such as high
on-off ratio, high density of states (DOS), low dimension-
ality, low power consumption, and high mobility.
as graphene FET (GFET) is renowned for its ballistic
transport due to the high mobility that could reach up to
1,000,000 cm2/Vs [59]. Stützel et al., is among the earli-
est to work on GFET for flash memory application [51].
Graphene was mechanically exfoliated and characterized
as in conventional FET configuration by using doped sili-
con substrate act as the back gate. Threshold voltage shift
is observed when the back-gate voltage is swept between
±10 V. Pulse test conducted below 10 kHz shows stable
switching between the on/off states without any sign of
degradation, suggesting high endurance of >107cycles.
Zhan et al., also reported on GFET but with the addition
of nickel nanocrystal as the floating gate [52]. A large
memory window of >10 V is observed by sweeping the
back-gate voltage between ±40 V until it starts to show
saturation at 23.1 V. The large threshold shift is due
to the low dimensional structure of multilayer graphene
(MLG) that allows fringing electric fields from the back-
gate affecting the channel and the Ni-nanocrystal.
Graphene Flash Memory (GFM) is a floating gate transis-
tor with graphene as its memory element. Hong et al., was
the first to use graphene as a floating gate [8]. He adopted
the MOS-capacitor structure consisting Si–SiO2-graphene-
Al2O3–Ti/Al/Au. Both single-layer graphene (SLG) and
multilayer graphene (MLG) are synthesized using CVD
method where both materials are distinguished by their
Raman shift; then, transferred onto a Si/SiO2layer in which
the silicon is used as device channel and 5 nm thick SiO2
is used as the tunneling oxide layer. A 35 nm thick high-
kAl2O3is used as the IPD oxide layer to provide with
better control gate capacitance and improved reliability.
Ti/Al/Au stacking is used as the gate electrode. A con-
trol device which excludes the graphene layer is also fabri-
cated for comparison purpose. The performances for both
SLG and MLG are assessed by measuring its memory win-
dow, charge density in the floating gate and its reliability is
approximated based on the extracted data.
The capacitance–voltage (C–V) characteristics for these
three devices (i.e., SLG, MLG and control device) are
measured. Early clarification is made where the control
device shows a negligible threshold voltage shift to indi-
cate the process is almost free from dangling charges.
While the other two devices are being subject to ±7V
gate voltage and show threshold shifting. The memory
window for MLG is observed to be approximately 6 V
while for SLG is approximately 2 V. This shows that the
employment of MLG has immensely improved the charge
storage capability for floating gate device while the indus-
try standard is set at 1.5 V [8]. Early intuitive reason for
this exceptional improvement is due to the higher num-
ber of DOS in MLG compared to SLG. This has been
affirmed by computing the number of charge density trap
inside both floating gates by using Eq. (17). Assuming that
initially before charging the device number of charge is
zero, Q=0. After the device is on the number of charges,
Several reports on graphene discussed on its capability
to be employed either as the floating gate transistor chan-
nel [49, 51–54] or as the floating gate itself [8–11, 55–58].
Graphene as a transistor channel or commonly known
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Scaling Challenges of Floating Gate Non-Volatile Memory and Graphene as the Future Flash Memory Device: A Review Hamzah et al.
Q=qn,wherenis the carrier density and qis the elec-
tron charge in which the charge density is deduced as
n=CFG ·VT/q. MLG floating gate has 1 ×1013 cm−2
whereas SLG has 333×1012 cm−2. This shows that MLG
has higher number of trap charge of approximately multi-
ple of 3 which also triples the memory window to ∼6V.
Moreover, MLG has high workfunction (∼4.6 eV) which
offers high electronic barrier at graphene/SiO2interface for
the trapped charge from tunneling back to the substrate.
With the wide memory window, MLG could exhibit long
retention capability. It is expected that only 8% charge loss
for over 10 years [8]. Hong et al., has also conducted a
simulation to observe the cell-to-cell interference crossing
the wordline for GFM compared to the conventional float-
ing gate structure. The result shows that the thinness of
MLG manages to reduce cell-to-cell interference of poly-
Si floating gate by minimizing the resulting field of nearest
neighbors upon charging.
In 2012, Mishra et al., have also conducted similar work
to Hong et al., in which comparison between SLG and
MLG is reported [9]. He adopted the flash MOS-capacitor
structure consisting of Si–SiO2-MLG-Al2O3-TiN. 6–7 lay-
ers of MLG are obtained by reducing the graphene oxide
layer and the thickness is measured to be approximately
2–3 nm thick. The effective oxide thickness for both tun-
neling and IPD layers are measured to be 13.5 nm and
15 nm respectively. Pulse test is conducted for 1 s using
±18 V W/E voltage and the memory window is extracted.
The large W/E voltage compared to Hong’s structure could
be due to the thicker tunnel oxide layer used in Mishra
et al., work. The results show that the MLG has a wider
memory window of 6.8 V and higher carrier density in the
floating gate of 91×1012 cm−2compared to SLG. This is
mainly due to the high DOS number as calculated in this
paper
Molybdenum Disulfide (MoS2is also one of the
promising low-dimensional material. The fully 2D NVM
has been introduced by Bertolazzi based on MoS2and
graphene by forming a heterojunction structure [10]. The
structure adopted MLG as the floating gate and SLG is
used as the electrode connected to another 2D structure
channel of MoS2. This has been the state-of-art of a new
revolutionize floating gate device due to the combination
of 2D materials. The usage of MoS2as channel seems
obvious due to its semiconducting properties and with the
combination of highly conductive graphene layer would
make it very promising for the future molecular device.
Direct contacts between MoS2and graphene are sepa-
rated by an interlayer distance of 0.34 nm does prove to
have charge transfer despite the large interlayer separation.
Graphene is synthesized by CVD method and placed onto
a Si/SiO2structure and MoS2is exfoliated to a separate sil-
icon substrate before being placed onto the graphene layer.
A high-kdielectric oxide layer of combination Al2O3-
HfO2is used for both tunneling and an IPD oxide layer
with thickness (1:6 nm) and (1:30 nm) respectively where
the MLG of 2–3 nm thick is being held in between these
oxide layers.
The newly device characteristics and performances are
assessed to distinguish its capability as a flash memory.
A memory window of approximately 8 V is observed when
the device is biased between ±15 V back to back. The
carrier density is then computed in the order of 1017 m−2
which is similar to the previous reports on MLG floating
gate [8, 9]. The gate leakage through the control gate is
also measured during programming to be 10 pA which
is much lower than the poly-Si floating gate reported in
Ref. [38]. This proves MLG floating gate to have similar
features as HFG in suppressing the ballistic transport dur-
ing programming. This is due to its zero bandgap nature
that has metallic properties. Since the MLG floating gate
is thermally stable at a very high temperature of 1500 C,
thus it is more favorable to be used as the floating gate
compared to HFG. The on-off ratio exceeding 104is mea-
sured. The high ratio is important for a fast read operation
of the device. The endurance test is performed by supply-
ing voltage pulse of 10 Hz. The test indicated slow decay
after each W/E operation for 120 cycles. This is due to the
wearing effects that most floating gate transistor suffers.
Finally, the retention of the device shows 70% charge loss
after 10 years. However, room of improvement could be
made by implementing better high-koxide to improve the
endurance and the reliability of GFM. Some parameters
pertaining to the performance of these flash memories are
extracted. The capacitance between the control gate and
the floating gate is computed as CCOX =0·r/tCOX,where
0is the vacuum permittivity, rand tCOX are the dielectric
constant and thickness of the IPD oxide layer respectively.
Then the GCR can be approximated as [57]
GCR ≈CCOX
CCOX +CTOX
=11+tCOX
tTOX
·TOX
COX (18)
The metric performances are summarized as in Table IV.
Since graphene has semi-metallic properties and high
workfunction as metal, a comparison is made between
GFM and HFB. The GCR is calculated using Eq. (18). It
seems like HFG has outclassed the GFM given its high
GCR and memory window. GFM in Refs. [8, 10] shows
very low GCR of 0.2–0.3 except in Ref. [9] where the
GCR is maintained above 0.6 due to the thicker tun-
nel oxide layer of 13.5 nm. Basically, low GCR led to
poor gate control and required higher operating voltage to
compensate the low gate capacitance. In addition, the cell-
to-cell interference and the GCR are suppressed by the
thinning of the floating gate while reducing the number of
charge being stored due to the decrease in DOS, resulting
in small memory window. But for the case of GFM, even
though the GCR is considered low, the device has lower
W/E operating voltage and wider memory window than the
HFG. This led to a whole new understanding of memory
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Hamzah et al. Scaling Challenges of Floating Gate Non-Volatile Memory and Graphene as the Future Flash Memory Device: A Review
Tab l e I V. GFM device performances compared to HFG.
Type of memory Ref. CFG (F ·m−2)n(m−2) GCR Memory window Retention time Endurance
GFM [10] 5.6 ×10−32.8 ×1017 0.2 ∼8V(Vcg =15 V) ∼10 years >104
[9] 5.3 ×10−32.26 ×1017 0.68 ∼6.8 V (Vcg =18 V) N/A N/A
[8] 2.3 ×10−31.0 ×1017 0.25 ∼6V(Vcg =7V) ∼10 years N/A
[8] 2.7 ×10−33.33 ×1016 0.25 ∼2V(Vcg =7V) ∼10 years N/A
HFG [62] 8.4 ×10−33.89×1017 0.67 ∼7.4 V (Vcg =18 V) N/A N/A
[39] 5.3 ×10−33.65 ×1017 0.57 ∼11 V (Vcg =22 V) ∼10 years >104
cell where thinner floating gate is essential in minimizing
the cell-to-cell interference while obtaining a wider mem-
ory window. Graphene has a remarkable intrinsic prop-
erty of high DOS. This is proved by all three reports that
computed carrier density in GFM within the magnitude
of ∼1017 m−2which is approximately similar to the HFG
(refer Table IV). The high DOS has led to a large memory
window while the thin physical thickness of MLG accom-
modated in scaling the W/E voltage [8]. Since the poly-Si
floating gate consists of low work function and suffers
from severe ballistic transport during programming limit-
ing it thickness to only 7 nm, HFG has step-up the chase of
replacing the conventional poly-Si as floating gate within
hope that it could facilitate scaling of W/E voltage and
device geometry. However, the implementation of metal is
highly unstable under high temperature. In addition, it also
contaminates the tunnel oxide layer that could cause severe
SILC and leakage increased during the retention period. In
contrast, the inert covalently bonded graphene structure is
thermally stable material of up to 1500 C and circumvent
from any contamination to the tunnel oxide layer making
it a better contender than metal [60]. With respect to its
high work function (∼4.6 eV), MLG suppressed the bal-
listic leakage current from going through the control gate
during programming. With a good combination of high-k
IPD oxide layer should provide faster set/reset time and
provide with better leakage suppression [61]. As shown in
Table IV, previous reports indicate that MLG can hold the
data for >10 years.
Additionally, graphene exhibit a thinner layer than the
HFG. 6 to 7 graphene layer could sum up to about 2–3 nm
thickness. In order to maintain the GCR level while
Advantages of MLG as Floating gate device:-
1) Provide large memory window.
2) Provide large barrier for electron during
retention.
3) Suppressed ballistic leakage current.
4) Thermally stable at high temperature of
up to 1500˚C.
5) Reduced cell-to-cell interference.
Fig. 18. Shows the fully planar of 2D structure MLG flash memory transistor in combination with 2D channel material to further miniaturize the
floating gate device. The advantages of MLG floating gate are highlighted.
minimizing its cell-to-cell interference, sensible parame-
ter characterization needs to be done in choosing suitable
oxide thickness when employing MLG as the memory ele-
ment. Utilizing the barrier engineering IPD oxide could
be one of the methods in achieving good retention and
gate control for GFM [37]. Further understanding in scal-
ing the oxide layers is required in order to utilized MLG
floating gate. This has been thoroughly discussed by Cao
et al., where the fully planar 2D heterostructure-based
floating gate transistor is benchmarked with conventional
FG-MOS [57]. Finally, the advantages of GFM can be
summarized as in Figure 18.
7. 3D VERTICAL FLASH MEMORY
The 3D NAND architecture provides another alternative
for having high-density memory storage. But given the
stacking of 2D planar device prove to be technically
challenging because of many process steps; furthermore,
the prerequisite layers experienced an additional thermal
process that rose the cost per bit after several numbers of
layers (refer Fig. 19). In addition to the mounting number
of cell in 3D stacking leading to the increase of cell-to-cell
interference between adjacent layers, has cast doubt over
its efficiency.
The introduction of “punch and plug” approach in 2007
has simplified the fabrication process dramatically [63].
The so-called ‘Bit-cost scalable (BiCS) technology is a
process that forms vertical bit line channels that are “plug”
through the arrays of the control gate to form high-density
multi-layer flash memory. Fewer fabrication steps taken
in forming the 3D stacking proved to be very econom-
ical and somehow predicted to be saturated at a certain
J. Nanoelectron. Optoelectron. 2019, Vol. 14, No. 9 1209

Scaling Challenges of Floating Gate Non-Volatile Memory and Graphene as the Future Flash Memory Device: A Review Hamzah et al.
Fig. 19. Shows the relative bit cost for 3D stacked NAND architecture
and Bit-Cost scalable when the number of layer increases. Adapted with
permission from [63], Tanaka, H., et al., 2007. Bit Cost Scalable Technol-
ogy with Punch and Plug Process for Ultra High Density Flash Memory.
2007 IEEE Symposium on VLSI Technology, pp.14–15. Copyright@IEEE.
number of layers. Since then, other approaches have been
proposed for low-cost 3D flash memory architectures by
implying few processing steps. In 2013, ITRS has cat-
egorized the 3D NAND flash into three groups namely
the vertical channel, the vertical gate and the floating gate
(refer Table V).
Most 3D flash memory architectures have adopted the
gate-all-around (GAA) cell transistor due to the conve-
nience of “punch and plug” fabrication approach. The
main advantage of implementing GAA is because of
its ultimate gate electrostatic control on the channel to
Tab l e V. 3D vertical NAND flash categories as highlighted in ITRS 2013.
Vertical channel Vertical gate Floating gate
Approach p-BiCS TCAT VSAT VG-NAND DC-SF S-SCG
Cell transistor SONOS GAA TANOS GAA SONOS planar SONOS DG FG GAA FG GAA
Cell size 6 F2/n 6 F2/n 6 F2/n 4 F2/n 10 F2/n 13 F2/n
Ref. [63] [64] [65] [66] [67] [68]
Tab l e V I . The metric performance between silicon-based GAA and CNT-based GAA flash memory devices.
Memory type Silicon-based GAA CNT-based GAA
Device structure [73] [74] [67, 75] [76] [7] [72]
Diameter (nm) 5.0 7.0 40 15 2.0 1.5
Tunnel layer thickness (nm) 4.5 (SiO23.0 (SiO28.0 (SiO211 (TEOS) 3.0 (SiNX3.0 (Al2O3
Storage layer thickness (nm) 4.5 (Si3N4with Si-NC) 7.8 (Si3N440 (n+poly-Si) 25 (n+poly-Si) Au-dots Si-dots
IPD layer thickness (nm) 8.0 (SiO25.8 (SiO212 (SiO220 (TEOS) 10 (Al2O310 (Al2O3
Device performance
W/E voltage (V) 11/−10 14/−14 15/−11 10/−8−5/5 −5/5
SS (mV/dec) 84 77 60.5 112 98.6 100
DIBL (mV/V) 26 43 – 38.8 – –
On/Off ratio ∼105∼105∼104∼103∼104∼103
Vth (V) 6.25 5.2 9.2 6.0 4.5 3.0
GCR – – 0.7 0.7 0.6 0.5
Transient characteristics
Endurance >104>104>104>104––
Retention ∼10 years ∼10 years ∼10 years ∼10 years – ∼600 s
increase the device performance for high-speed applica-
tion and better control of short channel effect [3]. Table VI
below shows the metric performance for the upcoming
prospect of GAA 3D flash memory devices in achieving
high-density storage as well as to further downscaling.
The GAA structure can be simply divided into two cat-
egories which are the silicon-based and the CNT-based.
The CNT-based flash memory indicates p-type device.
Within a glimpse, silicon-based GAA architectures are
much superior to CNT-based all in all. With SS nearing
the theoretical limit, low DIBL and high on/off ratio sug-
gest high-speed W/E operation within s can be achieved.
The wide memory window also prompts for MLC applica-
tion, especially for DC-SF architecture where the threshold
shift could be as wide as 9.2 V when longer or higher gate
pulse is applied. The high GCR of >0.6 could compensate
the cell-to-cell interference that degraded the floating gate
device stability.
The cylindrical tubular CNT topology allowed the for-
mation of GAA structure for transistor application and
showed remarkable device performance [69–71]. This has
led to the possibility of CNT field-effect-transistor (CNT-
FET) to be used as a GAA flash memory device. Yusuke
et al., fabricated the CNTFET floating gate device by
embedding Au-dot as the floating gate and study its
memory effect using high-kdielectrics insulator namely
Al2O3[7]. Most importantly the device is annealed with
270 C in a chamber to remove the water molecules from
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Hamzah et al. Scaling Challenges of Floating Gate Non-Volatile Memory and Graphene as the Future Flash Memory Device: A Review
MLG as the storage element. Firstly, the combination of
low dimensional material promoted scaling of the floating
gate device below the sub-20 nm technology. The utiliza-
tion of MLG as a floating gate has increased the width of
memory window, provides high work function that forms
high barrier for electron tunneling during retention, sup-
pressed the ballistic leakage current during programming,
thermally stable at a very high temperature, and severely
reduces the cell-to-cell interference and most importantly
to accommodate downscaling of floating gate device. GCR
≥0.6 has been the benchmark for suppressing FG-MOS
cell-to-cell interference and longer retention time limit.
Although GFM has low GCR, it can still minimize the
floating gate crosstalk and its high workfunction provides
a higher barrier than poly-Si from electrons tunneling dur-
ing the charge retention period. A comprehensive study
has been performed by Cao et al., in theoretically realizing
the potential of a fully planar 2D heterostructures GFM
with the combination of transition metal dichalcogenides
(TMD) channel. The physical structure of GFM is bench-
marked as in Table V [77].
Nevertheless, there are still rooms for improvement that
can be done to further understand the performance of
GFM. One of the major issues has been the ballistic cur-
rent due to floating gate thickness limitation. Mathematical
modeling and simulation effort could be done in giv-
ing thorough understanding on MLG floating gate. It is
predicted that MLG metallic behavior could suppress the
ballistic current during programming and therefore, under-
standing the tunneling mechanism of MLG floating gate
and modeling could help in reviewing this issue. Further-
more, the device and transient performances could also be
assessed.
In the case of vertical 3D NAND flash device, despite
the GAA architecture has the capability of reducing the
short channel effect and to improve the gate control,
the prospect of CNT as flash memory is yet to unfold.
The most important component in a flash device is the
memory element; either it is the floating gate or the
charge trapping. This paper only present nanocrystal as
the floating gate and p-type device as it is so far, the
Table VII. Scaling projection limitation comparison between FG-MOS
and GFM (adapted with permission from [77], Cao, W., et al., 2014.
A compact current–voltage model for 2D semiconductor based field-
effect transistors considering interface traps, mobility degradation, and
inefficient doping effect. IEEE Trans. Electron Devices,61, pp.4282–
4290. Copyright@IEEE).
Ratio between
Gate Cell-to-cell W/E current
TOX COX length distance and leakage
EOT (nm) EOT (nm) (nm) (nm) current
Si/poly-Si 5 (SiO25 (high-K) 15–16 15–16 1017–1027
TMD/MLG 1.5 (HfO22(HfO
25–10 5–10 1019–1034
Fig. 20. Retention characteristics of CNTFET floating gate device using
Si-dots floating gate (red), Au-dots floating gate (blue) and HfO2 (red).
Adapted with permission from [7], Yusuke, F., et al., 2012 Carbon
nanotube-based floating gate memories with high-k dielectrics. Japanese
Journal of Applied Physics, 51, p.06FD11. Copyright@Institute of
Physics.
influencing the memory effect. The deposition of Al2O3
as the IPD oxide layer has resulted in an increase of the
memory window to 4.6 V compared to the SiO2 layer with
3.2 V. This is because the high-k IPD layer provides better
gate control, which subsequently reduces the barrier thick-
ness of the SiNx in allowing more holes to penetrate into
the Au-dot. Recently, in accordance with Yusuke et al.,
work, Kohei et al., have fabricated the CNTFET floating
gate device but uses Si-dot as the floating gate. Figure 20
shows the retention characteristics of a CNTFET floating
gate with different floating gate elements. Si-dots float-
ing gate managed to uphold the on/off ratio much longer
than the Au-dots. The on/off ratio of Au-dots floating gate
decrease within 600 s while Si-dots and HfO2 still retain
its memory window. It is said that the negligible band off-
set between Au-dots and Al2O3 contributed to the severe
electron tunneling during retention [72]. The memory win-
dow for the Si-dots is only 4.5 V with ±5 V operating
voltage; but more than enough to operate as an SLC. Wider
memory window can possibly be achieved by applying a
larger operating pulse. Moreover, their GCRs are much
lower than the silicon-based GAA flash memory due to
the thin floating-dot.
8. DISCUSSION AND CONCLUSION
We have thoroughly discussed the scalability issues related
to conventional floating gate transistor based on each com-
ponent of the device that consists of both tunneling and
IPD oxide layers, and its floating gate followed by propos-
ing possible approaches in solving these issues for each
component of the device where these issues are then con-
cluded in the form of figure (refer Fig. 17). In accor-
dance to these issues, GFM is prompted as a possible
solution due to superior graphene intrinsic characteristics
such as low dimensionality, high DOS, high current den-
sity, and thermally stable at high temperature. The dis-
cussion f ocuses on i ts floating gate component t hat uses
J. Nanoelectron. Optoelectron. 2019, Vol. 14, No. 9 1211

Scaling Challenges of Floating Gate Non-Volatile Memory and Graphene as the Future Flash Memory Device: A Review Hamzah et al.
most updated for charge-based flash memory using CNT-
FET. Other potential floating gate components such as the
n+poly-Si and the HFG can also be utilized in order to
observe the performance of CNTFET as flash memory.
Both simulation and experimental efforts are essential in
comprehending this matter. Simulation basis could realize
the physic behind CNTFET for flash memory application.
Considering the robust ballistic transport model [78, 79]
and by incorporating the capacitive coupling coefficient
method [80, 81] could be a starting point in understand-
ing the upper limit of the CNTFET flash memory device
application. Umoh and Kazmierski are those of a very few
researches to come out with the floating gate device model
using GNR [82]. Experimental work is very essential in
realizing the real potential of one device. Researchers
have reported the possibility of fabricating GAA CNTFET
by obtaining suspended CNT [71, 83, 84]. Then, Atomic
Layer Deposition (ALD) is used to deposit dielectric layer
and metal gate. A similar process could be utilized to
form floating gate CNTFET on Si substrates with ther-
mally grown 300 nm thick SiO2. The thick Si substrates
layer could accommodate the thickness of the gate stack.
Finally, the self-aligned floating gate CNTFET that has
scalable source/drain contacts with the gate length down
to 20 nm length could be realized [71], which is consistent
with ITRS2013 projection on 3D vertical flash memory
where the half-pitch size is scaled down to 22 nm [3].
Acknowledgments: Authors would like to acknowl-
edge the financial support from the Ministry of
Higher Education (MOHE), Malaysia under Project
R.J130000.7823.4F477. Also thanks to the Research
Management Center (RMC) of Universiti Teknologi
Malaysia (UTM) for providing an excellent research
environment in which to complete this work.
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