No full-text available
To read the full-text of this research,
you can request a copy directly from the authors.
Leakage current reduction in CMOS VLSI circuits by input vector control
Abstract
The first part of this paper describes two runtime mechanisms for reducing the leakage current of a CMOS circuit. In both cases, it is assumed that the system or environment produces a "sleep" signal that can be used to indicate that the circuit is in a standby mode. In the first method, the "sleep" signal is used to shift in a new set of external inputs and pre-selected internal signals into the circuit with the goal of setting the logic values of all of the internal signals so as to minimize the total leakage current in the circuit. This minimization is possible because the leakage current of a CMOS gate is strongly dependent on the input combination applied to its inputs. In the second method, nMOS and pMOS transistors are added to some of the gates in the circuit to increase the controllability of the internal signals of the circuit and decrease the leakage current of the gates using the "stack effect". This is, however, done carefully so that the minimum leakage is achieved subject to a delay constraint for all input-output paths in the circuit. In both cases, Boolean satisfiability is used to formulate the problems, which are subsequently solved by employing a highly efficient SAT solver. Experimental results on the combinational circuits in the MCNC91 benchmark suite demonstrate that it is possible to reduce the leakage current in combinational circuits by an average of 25% with only a 5% delay penalty. The second part of this paper presents a design technique for applying the minimum leakage input to a sequential circuit. The proposed method uses the built-in scan-chains in a VLSI circuit to drive it with the minimum leakage vector when it enters the sleep mode. The use of these scan registers eliminates the area and delay overhead of the additional circuitry that would otherwise be needed to apply the minimum leakage vector to the circuit. Experimental results on the sequential circuits in the MCNC91 benchmark suit show that, by using the proposed method, i t is possible to reduce the leakage by an average of 25% with practically no delay penalty.
... An additional mask layer is required due to VT(Threshold voltage) variation, thereby making fabricationprocess complicated.This technique suffers from latencyperiod i.e. it need some time to get into normal operatingmode after reactivation. The structure for dual VT andMTCMOS technique is shown as: [11] by citing anexample of 2-input NAND gate to illustrate the concept of transistor stacking. The minimum leakage causing input vector isidentified by an automation process and is applied to the circuit under sleep mode. ...
... The minimum leakage causing input vector isidentified by an automation process and is applied to the circuit under sleep mode. An algorithm to obtain the minimum leakagevector (MLV) is given by [11]. ...
The use of Very Large Scale Integration (VLSI) technologies in high performance computing, wireless communication and consumer electronics has been growing at a very fast rate.For the most recent CMOS technologies static power dissipation i.e. leakage power dissipation has become a challenging area for VLSI chip designers.A comprehensive study and analysis of various leakage power minimization techniques have been presented in this paper. The present research study and its corresponding analysis are mainly focusing on circuit performance parameters.
... Leakage current minimization is also a point being addressed in the IC designs and some of the proposed techniques are those suggesting power gating technique, CMOS design technique, RBB technique, Dual-Vt and Dual-Tox, bit line leakage current compensation technique [10]- [12]. In order to use photovoltaic panel for charging small to big electronic devices such as laptop, mobile phone charger for a longer battery lifetime, however the leakage current is the main issue of concern [13]. Recently reported is very useful work on minimizing the power losses and cost of grid-tied solar system [13]- [17]. ...
... In order to use photovoltaic panel for charging small to big electronic devices such as laptop, mobile phone charger for a longer battery lifetime, however the leakage current is the main issue of concern [13]. Recently reported is very useful work on minimizing the power losses and cost of grid-tied solar system [13]- [17]. Although small in magnitude, but the leakage current occurring at different points of the panels have become more (or less) the reason of reducing power efficiency [18]. ...
p>Solar panels used for electricity generation have got inverters as their core components. Such inverters are made from switching devices coupled with additional circuit component configured in a transformer-less topology in recent reported works. A transformer-less topology suffers from the drawbacks of lack of isolation leading to leakage current flow from various points of it down to ground. The leakage in inverters might be troublesome as it may lead to loss in power, and may cause malfunctioning of analog devices normally used in power inverters. In this work, we identify possible leakage currents in a given transformer-less topology using the circuit analysis principles. The conversion of so obtained leakage currents into a useful DC voltage is carried out in this work. This work focuses on converting leakage current into small DC voltage in the range of ~1.1004V using recently reported rectifier circuits, supplying a load of 200Ω in the mW range. Although small in magnitude, such voltage sources could be used for battery charging purposes or driving small loads.</p
... Additionally, the optimization of SRAM memory circuits [10], [11] plays a pivotal role in leakage reduction and overall circuit performance. Among the myriad forms of leakage currents [12], [13], subthreshold leakage [13], [14]emerges as a dominant concern [15], [16]. This paper addresses this issue by exploring modifications to the p-n junction structure to model and mitigate subthreshold leakage current. ...
This paper delves into the convergence of mathematical and computer science principles within the realm of electronics engineering, particularly focusing on device-level transistor restructuring. A pressing challenge confronting the semiconductor sector is the persistent escalation of leakage current alongside technological advancements. At the heart of any chip or semiconductor device lies the transistor, serving as its fundamental building block. Among the various forms of leakage current, subthreshold leakage stands out as a dominant component in transistors. Within this study, a systematic exploration of the numerical association governing the physical configuration of MOSFET and leakage amount specifically the subthreshold one is undertaken. One innovative algorithm is crafted to facilitate the automated tracking of transistor structures, laying the groundwork for subsequent analyses. The simulation framework is meticulously constructed by leveraging mathematical formulations derived from the algorithmic outputs. Remarkably, the results obtained from the simulation conducted through TCAD software exhibit a remarkable proximity to established mathematical models. Given the ubiquity of Complementary Metal Oxide Semiconductor (CMOS) technology in contemporary semiconductor fabrication, it serves as the cornerstone for the simulation endeavours herein.
... Additionally, the optimization of SRAM memory circuits [10], [11] plays a pivotal role in leakage reduction and overall circuit performance. Among the myriad forms of leakage currents [12], [13], subthreshold leakage [13], [14]emerges as a dominant concern [15], [16]. This paper addresses this issue by exploring modifications to the p-n junction structure to model and mitigate subthreshold leakage current. ...
This paper delves into the convergence of mathematical and computer science principles within the realm of electronics engineering, particularly focusing on device-level transistor restructuring. A pressing challenge confronting the semiconductor sector is the persistent escalation of leakage current alongside technological advancements. At the heart of any chip or semiconductor device lies the transistor, serving as its fundamental building block. Among the various forms of leakage current, subthreshold leakage stands out as a dominant component in transistors. Within this study, a systematic exploration of the numerical association governing the physical configuration of MOSFET and leakage amount specifically the subthreshold one is undertaken. One innovative algorithm is crafted to facilitate the automated tracking of transistor structures, laying the groundwork for subsequent analyses. The simulation framework is meticulously constructed by leveraging mathematical formulations derived from the algorithmic outputs. Remarkably, the results obtained from the simulation conducted through TCAD software exhibit a remarkable proximity to established mathematical models. Given the ubiquity of Complementary Metal Oxide Semiconductor (CMOS) technology in contemporary semiconductor fabrication, it serves as the cornerstone for the simulation endeavours herein.
... When logic 0 is given to the inverter. PMOS pull-up transistor will turn ON and NMOS pull-down transistor is switched-OFF and SAPON transistors (Q3 and Q4) remain in the active region, output reads logic 1 (Abdollahi, Fallah, & Pedram, 2004). Similarly, when logic 0 is given as input to the inverter, PMOS transistor will be turned off and NMOS transistor turned on and the output gets pulled down to 0[10'12]. ...
This concise presents a power efficient level shifter using regulated cross-coupled network with split inverter. With the use of regulated cross-coupled network, power dissipation of the pull-up region drastically decreases. Level shifters convert the voltage levels which are below the threshold voltage to the acceptable voltage levels by decreasing the transistor size. A Split inverter is used at the output to decrease the short circuit current. Modified Split inverter along with the load capacitor at the output is used to increase the speed and to decrease the power consumption. This LS can save 31% power compared to other techniques. The proposed level shifter works effectively at high speed and consumes less power. For simulation, LT spice tool of 50 nm technology and 90 nm technology is used.
... Sub threshold leakage I sub= Iso exp (Vgs-Vth/ Vth)(1-exp(-Vds /VT)) (1) Iso=μ0 Cox Weff/LeffV 2 e 1.8 (2) The level of integration of random-access memory cells performance of the circuit is enhanced. [11,12] Standby leakage power is reduced using this technique but the area and delay of the circuit are increased because of the insertion of large MOSFETs. [13] To reduce the area, ...
- Static power dissipation is due to leakage current when the transistor is normally off. The two main sources of power dissipation in CMOS circuits are static and dynamic power dissipation. By scaling down the feature size the dynamic power dissipation has no effect but the static power dissipation has become equal or more than that of Dynamic power dissipation. So, in recent CMOS technologies static power dissipation i.e. power dissipation due to leakage current has become a challenging area for VLSI chip designers. Leakage current occurs in both active and standby modes. Gate leakage, subthreshold leakage cannot be solved by MOS structures nor by introducing new material. One of the feasible solutions is by combinational use of Low- Vt transistors for its high-speed capability and High- Vt transistors for very small leakage current. Multi- Threshold CMOS(MTCMOS) and Variable- Threshold CMOS (VTCMOS) are biasing techniques that uses combinations of different threshold voltage and are suitable for SRAM design. Keywords: leakage power, CMOS, VTCMOS, Feature size, Subthreshold
... Another favorite circuit-level technique is called the input vector control (IVC) that is used for leakage power reduction [9]. It utilizes the transistor stack effect during the standby mode, by applying a vector to the inputs of CMOS logic gates that produce the minimum leakage. ...
To maintain performance increase and reliability, power supply and threshold voltages will have to continually scale, in CMOS technology. With threshold voltage scaling and thinner gate-oxide thickness, sub-threshold and gate tunneling leakage powers are expected to become a significant portion of the total power in CMOS VLSI systems. A self-control leakage-suppression block (SCLSB) for leakage power reduction of static CMOS gates is proposed in this paper. The proposed SCLSB consists of two PMOS and two NMOS transistors that are located between pull-down network (PDN) and pull-up network (PUN). In any combination of input signals, one PMOS and one NMOS transistor of SCLSB turn on and the rest turn off, hence the resistance between the power supply voltage rail to the ground rail increased and leakage currents greatly reduced. The basic static CMOS gates such as inverter, NAND, NOR, and XOR circuits are designed based on SCLSB and their performance is evaluated using SPICE simulations in 22 nm CMOS BSIM4 process. Evaluation outcomes with VDD = 0.9 V depict that power-delay product (PDP) is diminished by 9%, 12.8%, 6%, and 15.25% for inverter, NAND, NOR, and XOR compared to the best counterpart (LECTOR) and by 9%, 35%, 21.5% and 33.8% compared to the conventional CMOS gates. The mentioned features of the proposed static-CMOS circuits are achieved while sustaining the full-swing behavior. To ensure the stability and robustness of the circuits in the presence of the process, voltage, and temperature (PVT) variations, Monte Carlo analysis is also performed.
... And in these areas, recharging of batteries again and again may not possible .SoC [8] for determining power dissipation in chip memories because we can optimise the power here by different methodologies. Hence Low power [5] usage would be very beneficial for SRAM which is particularly practises in chip memories.leakage power is the ruling part of complete power dissipation today, and its commitment has expanded from 18% at 130 nm to 54% at 65 nm innovation [2]. ...
Standby power consumption is a genuine concern in profound nanometer gadgets. Low Power technique approach is frequently embraced in VLSI circuits and frameworks to limit power; in any case, this is accomplished at the expense of degradation in performance. In this article, we examine the pre-existing strategies for controlling leakage power. Sleeper transistor or adding extra transistors in the pathe of supply voltage to the ground proved to be the executable method to recover from leakage of power in hold state. Broad SPICE recreation with 32 nm measure innovation shows a critical decrease in power,PD (power delay)and area.
... Input vector control (IVC) is another favorite circuitlevel method for leakage current/power reduction [10,11]. It uses the stack effect in CMOS modules using adding a minimum leakage vector (MLV) to the primary inputs of combinational circuits and systems during the shut-down mode. ...
A new circuit-level methodology called input controlled leakage restrainer transistor (ICLRT) compatible with single threshold CMOS technology is proposed in this paper, to further discount the leakage and short-circuit powers. To implement this idea a PMOS ICLRT is placed on top of the PUN and an NMOS ICLRT is located at the bottom of the PDN for any path from the supply voltage and the ground to output. The ICLRTs can be deliberately applied to the main sources of leakage and short-circuit currents to reduce total power dissipation. To test the proposed technique, ICLRTs are applied to four 4-2 CMOS compressors. The efficiency of the proposed methodology is evaluated using SPICE simulations in 22-nm BSIM4 (level-54 parameters) CMOS technology. Simulation results with 0.9-V power supply revealed that the power consumption of the 4-2 CMOS compressors based on ICLRT technique is reduced 59.62–74.28% and also power-delay product (PDP) is diminished 32–46.78% relative to corresponding original designs.
... In addition to the well-known power-based attacks that explore the dynamic power consumption, the Static Power Side-channel Analysis (SPSCA) explores the static power dissipation. While in idle, the leakage current is different and strongly dependent on the input as shown in [12]. This attack is especially efficient on sub-100 nm technologies as the static power increases [13]. ...
Modern cryptographic circuits are increasingly demanding security requirements. Since its invention, power analysis attacks are a threat to the security of such circuits. In order to contribute to the design of secure circuits, designers may employ countermeasures in different abstraction levels. This work presents a brief survey of countermeasures to help designers to find good solutions for the design of secure cryptographic systems. A summary is highlighted to compare the pros and cons of the approaches to help designers choose a better solution, or even provide subsidies so that new solutions can be proposed.
... The procedure of turning off the gadgets by removing their supply voltage, leading to leakage power control, is called Power Gating [5]. This methodology uses some more resting transistors that are implanted in the course of action between supplied power and pulled-up framework or might be in between pull-down framework & ground for the reserve spillage currents reduction When the circuit is working in dynamic mode, and the sleeping transistors are whereas they are switched-off when the circuit is available for reserve mode. ...
... Multiple-Vth can be achieved by the methods like Multiple channel doping, Multiple oxide layers, Multiple channel length and multiple body bias [2]. Moreover, design technique like multiple-threshold CMOS was also one of the method used to reduce the propagation delay [12]. LECTOR and INDEP leakage reduction approaches are the CMOS based special configurations of the transistors and explained as below: ...
In the process of continuous miniaturization of devices, it is necessary to look for new devices which overcome the drawbacks of non-scalability and higher static power of metal oxide semiconductor field effect transistor (MOSFET). Fin-shaped field effect transistor (FinFET) is an important device which uses the concept of multi-gates and it is not only scalable but also dissipate lower power at lower technology nodes. This paper designs a low leakage input dependent (INDEP) approach for FinFET devices at 16 nm technology node. Numbers of logic gates are designed and simulated with the help of MOSFET and FinFET devices. Simulation results are compared by calculating the important parameters like leakage power, delay and power delay product (PDP). The designed low leakage INDEP approach is compared with the leakage control transistor (LECTOR) technique. Simulation results for different logic circuits show the large reduction in leakage power in case of FinFET logic gates as compared to MOSFET devices and more leakage saving in case of INDEP approach as compared to conventional as well as LECTOR technique. Reliability in terms of process, voltage and temperature (PVT) variations is checked by running the Monte-Carlo simulations for 1000 samples and observed that INDEP circuits are more reliable.
... Multiple-Vth can be achieved by the methods like Multiple channel doping, Multiple oxide layers, Multiple channel length and multiple body bias [2]. Moreover, design technique like multiple-threshold CMOS was also one of the method used to reduce the propagation delay [12]. LECTOR and INDEP leakage reduction approaches are the CMOS based special configurations of the transistors and explained as below: ...
In the process of continuous miniaturization of devices, it is necessary to look for new devices which overcome the drawbacks of non-scalability and higher static power of metal oxide semiconductor field effect transistor (MOSFET). Fin-shaped field effect transistor (FinFET) is an important device which uses the concept of multi-gates and it is not only scalable but also dissipate lower power at lower technology nodes. This paper designs a low leakage input dependent (INDEP) approach for FinFET devices at 16 nm technology node. Numbers of logic gates are designed and simulated with the help of MOSFET and FinFET devices. Simulation results are compared by calculating the important parameters like leakage power, delay and power delay product (PDP). The designed low leakage INDEP approach is compared with the leakage control transistor (LECTOR) technique. Simulation results for different logic circuits show the large reduction in leakage power in case of FinFET logic gates as compared to MOSFET devices and more leakage saving in case of INDEP approach as compared to conventional as well as LECTOR technique. Reliability in terms of process, voltage and temperature (PVT) variations is checked by running the Monte-Carlo simulations for 1000 samples and observed that INDEP circuits are more reliable.
... The input vector method by Abdollahi et.al. makes use of dependence of leakage current on the input vector to gate [1]. Additional control logic is used to put the circuit in a low-leakage standby state when it is idle and restored to its original state when reactivated. ...
In recent years, with shrinking of device technologies, leakage power (static power) dissipation has become an inevitable proportion of the total power dissipation in an integrated circuit. The leakage power dissipation is projected to grow exponentially during the next decade according to the International Technology Roadmap for Semiconductors (ITRS). This directly affects portable battery operated devices. In this paper a robust method which is equally effectual for static power control for CMOS VLSI circuits in deep submicron technologies has been proposed. It is also referred to as 'sleepy pass gate' uses two complementary sleep transistors connected in parallel forming a pass gate structure. In our leakage reduction technique, the exact output logic state is preserved in both active and standby mode of operation. Thus, experiments conducted with a range of process technologies on combinational logic gates and MCNC'91 benchmark circuits show that the proposed method gives significant savings in leakage power upto 2 orders of magnitude, with lesser area and delay penalty.
... The conditional keeper circuit [15] has been simulated to reduce the delay with lots of transistors that consume more power. With the help of stack [16] and input vector control [17], the leakage current had been improved in the deep submicron devices at the cost of power and area. The stack also improves the load capacitance by cascading of n-channel MOSFET in a pull-up network (PUN), resulting in low voltage swing at the output node. ...
Objective
A new efficient keeper circuit has been proposed in this article for achieving low leakage power consumption and to improve power delay product of the dynamic logic using carbon nanotube MOSFET.
Method
As a benchmark, an one-bit adder has been designed and characterized with both technologies Si-MOSFET and CN-MOSFET using proposed and existing dynamic circuits. Furthermore, a comparison has been made to demonstrate the superiority of CN-MOSFET technology with Synopsys HSPICE tool for multiple bit adders available in the literature.
Result
The simulation results show that the proposed keeper circuit provides lower static and dynamic power consumption up to 57 and 40% respectively, as compared to the domino circuits using 32nm CN-MOSFET technology provided by Stanford University. Moreover, the proposed keeper configuration provides better performance using SiMOSFET and CN-MOSFET technologies.
Conclusion
A comparison of the proposed keeper with previously published designs is also given in terms of power consumption, delay and power delay product with the improvement up to 75, 18 and 50% respectively. The proposed circuit uses only two transistors, so it requires less area and gives high efficiency.
... Among total six components of leakage current , three topmost components of leakage current are subthreshold leakage current, gate leakage current and reverse bias p-n junction leakage current (Abdollahi et al., 2004;Agarwal et al., 2006;Mukhopadhyay et al., 2003Mukhopadhyay et al., , 2005Sanyal et al., 2010). It was observed that modification in gate structure can reduce transistor area (Mukherjee and Reddy, 2018b) and modification in source-drain structure can reduce subthreshold leakage current Reddy, 2016, 2018a). ...
... The components of static power loss are losses below the threshold, junction losses, gate oxide losses, networkinduced drainage losses and breakage losses. [8,9] This applies to directly battery-powered portable devices such as cell phones and PDAs, as they have a long service life. Different techniques used to effectively minimize this power loss. ...
In this thesis proposed a reduction of delay, leakage current, leakage power. First find out the leakage current and leakage power. This thesis uses a gate diffusion input technique. By using this no of transistor is reduced. If number of transistor is reduced, area is also reduced, leakage current also affected. To study all parameter in this thesis uses a 2x1 MUX, 4x1MUX,16x1 MUX and ALU. Applying a GDI technique and also implemented by using a CMOS technique. Then do comparisons on GDI and CMOS technique and do a capacitance calculation. To implement all those things use a microwind 3.1 and DSCH 2.0. It is an Electronic Design Automation (EDA) environment that allows implementing a integrating in a single framework different applications and tools, allowing supporting all the stages of IC design and verification from a single environment. The resulting layout must verify some geometric rules dependent on the technology (design rules). Now checked with a Design Rule Checker (DRC) to find any error in the layout diagram and them simulation is performed. In implementing and do a comparisons of GDI and CMOS technique we get a 75% advantage in 2x1 MUX in counting the number of transistor. In 4x1 MUX we get again a 75% gain in the number of transistor. In 8x1 MUX, give a 78% benefits in the number of transistor. In 16x1 MUX, give a 81% benefits in the number of transistor. In 1 bit ALU give a 54% benefits in the number of transistor. If related power consumption, get a 74% benefits in comparisons of GDI and CMOS technique in 2x1 MUX. In 4x1mux give the advantage of 79% in the power consumption in comparisons of GDI and CMOS technique. In 8x1mux give the advantage of 78% in the power consumption in comparisons of GDI and CMOS technique. In 16x1mux give the advantage of 79% in the power consumption comparisons of GDI and CMOS technique. In bit ALU give the advantage of 64% in the power consumption in comparisons of GDI and CMOS technique.
... Face à l'augmentation des courants de fuite causée par la miniaturisation des transistors, de nouvelles solutions ont été proposées pour réduire significativement I grille . L'ajout d'un sleep mode dans [80] et par contrôle actif de la polarisation du transistor (pour contrôler sa tension de seuil) avec [81] permet une réduction importante du courant I grille . Concernant I seuil et I diode , il a été impératif de repenser la conception des transistors pour limiter ces problèmes de courants de fuite lorsque la finesse devenait inférieure à 25 nm. ...
Les définitions des mots « sentiment », « opinion » et « émotion » sont toujours très vagues comme l’atteste aussi le dictionnaire qui semble expliquer un mot en utilisant le deux autres. Tout le monde est affecté par les opinions : les entreprises pour vendre les produits, les gens pour les acheter et, plus en général, pour prendre des décisions, les chercheurs en intelligence artificielle pour comprendre la nature de l’être humain. Aujourd’hui on a une quantité d’information disponible jamais vue avant, mais qui résulte peu accessible. Les mégadonnées (en anglais « big data ») ne sont pas organisées, surtout pour certaines langues – dont la difficulté à les exploiter. La recherche française souffre d’une manque de ressources « prêt-à-porter » pour conduire des tests. Cette thèse a l’objectif d’explorer la nature des sentiments et des émotions, dans le cadre du Traitement Automatique du Langage et des Corpus. Les contributions de cette thèse sont plusieurs : création de nouvelles ressources pour l’analyse du sentiment et de l’émotion, emploi et comparaison de plusieurs techniques d’apprentissage automatique, et plus important, l’étude du problème sous différents points de vue : classification des commentaires en ligne en polarité (positive et négative), Aspect-Based Sentiment Analysis des caractéristiques du produit recensé. Enfin, un étude psycholinguistique, supporté par des approches lexicales et d’apprentissage automatique, sur le rapport entre qui juge et l’objet jugé.
... Those are source/drain junction leakage current, gate direct tunneling leakage, sub threshold leakage current through the channel of an OFF transistor. Among the above leakage currents in CMOS technologies, the major portion of leakage arise with sub-threshold leakage current [4] Different approaches and techniques are considered to reduce the leakage power. One good technique is "Input vector control", which is not dependent on process technology and it is built on transistor stacking that gives awful reduction in leakage power without compromising to its performance [5] [6]. ...
The power management has become the major constraint while designing VLSI circuits as parameters like Area, Speed, etc. are critical to be optimized. In this work, a low power 16-bit ALU is designed to perform all arithmetic and logic operations. The present day super computers, mobile gadgets, calculators etc. are using low power ALU systems to perform their tasks. Especially, leakage power occupies major portion of power consumption in the CMOS circuits, as the process technology progresses. The objective of the research work is to reduce leakage power in maximum extent to run the ALU with low power. The proposed model has used IVC based leakage power reduction technique in standby mode by using Gravitational Search Algorithm (GSA). Input Vector Control (IVC) technique is found to be a better alternative in achieving low leakage as it is based on the effect of transistor stacking and it is highly preferred because of its independency over other technological parameters without performance overhead. The GSA locates MLV (Minimum Leakage Vector) in vector combinations of input test circuits of ALU. And then IVC forces the other vector combinations into MLV mode of a test circuit to reduce leakage power. The comparison study has been carried out with Genetic Algorithm (GA) and Particle Swarm Optimization (PSO) algorithm with various test circuits. Power analysis is conducted with GSA to ascertain better leakage reduction and also it locates MLV in less number of iterations. GSA takes only 13 iterations to reach its global space, whereas, PSO takes 62 iterations and GA takes 96 iterations to reach their global space. The simulations are carried out using the Xilinx platform with Verilog coding using PSPICE and MATLAB tools.
... Among these components, subthreshold current I sub and gate leakage current I gate are the dominant parts. As a result, we can ignore other parts of leakage and get the leakage current approximation [55], [56], [57] as ...
Leakage power is becoming significant in new generation IC chips. As leakage power is nonlinearly related to temperature, it is challenging to manage the thermal behavior of today’s multi-core systems, since thermal management becomes a nonlinear control problem. In this article, a new predictive dynamic thermal management (DTM) method with neural network thermal model is proposed to naturally consider the inherent nonlinearity between leakage and temperature. We start with analyzing the problems of using recurrent neural network (RNN) to build the nonlinear thermal model, and point out that there is exploding gradient induced long-term dependencies problem, leading to large model prediction errors. Based on this analysis, we further propose to use echo state network (ESN), which is a special type of RNN, as the leakage-aware nonlinear thermal model. We theoretically and experimentally show that ESN achieves much higher accuracy by completely avoiding the long-term dependencies problem. On top of this nonlinear ESN thermal model, we propose a novel model predictive control (MPC) scheme called ESN MPC, which uses iterative steps to find the optimal future power recommendations for thermal management. Being able to consider the leakage-temperature nonlinear effects and equipped with advanced control technique, the new method achieves an overall high quality temperature management with smooth and accurate temperature tracking. Experimental results show the new method outperforms the state-of-the-art leakage-aware multi-core DTM method in both temperature management quality and computing overhead.
... Face à l'augmentation des courants de fuite causée par la miniaturisation des transistors, de nouvelles solutions ont été proposées pour réduire significativement I grille . L'ajout d'un sleep mode dans [80] et par contrôle actif de la polarisation du transistor (pour contrôler sa tension de seuil) avec [81] permet une réduction importante du courant I grille . Concernant I seuil et I diode , il a été impératif de repenser la conception des transistors pour limiter ces problèmes de courants de fuite lorsque la finesse devenait inférieure à 25 nm. ...
Ce texte étudie le groupe quantique Uξ sl(2|1) associé à la superalgèbre de Lie sl(2|1) et une catégorie de ses représentations de dimension finie. L'objectif est de construire des invariants topologiques de 3-variétés en utilisant la notion de trace modifiée. D'abord nous prouvons que la H catégorie CH des modules de poids nilpotents sur Uξ sl(2|1) est enrubannée et qu'il existe une trace modifiée sur son idéal des modules projectifs. De plus CH possède une structure relativement G-prémodulaire ce qui est une condition suffisante pour construire un invariant de 3-variétés à la Costantino-Geer-Patureau. Cet invariant est le cœur d'une 1+1+1-TQFT (Topological Quantum Field Theory). D'autre part Hennings a proposé à partir d'une algèbre de Hopf de dimension finie une construction d’invariants qui dispense de considérer la catégorie de H l l ses représentations. Nous montrons que le groupe quantique déroulé Uξ sl(2|1)/(e1 , f1 ) possède une complétion qui est une algèbre de Hopf enrubannée topologique. Nous construisons un invariant de 3-variétés à la Hennings en utilisant cette structure algébrique, une transformation de Fourier discrète et la notion de G-intégrales. L'intégrale dans une algèbre de Hopf est centrale dans la construction de Hennings. La notion de trace modifiée dans une catégorie s'est récemment révélée être une généralisation des intégrales dans les algèbres de Hopf de dimension finie. Dans un contexte plus général d'algèbre de Hopf de dimension infinie nous prouvons la relation formulée entre la trace modifiée et la G -intégrale.
Leakage current consumes the majority of the active mode energy in the high-performance integrated circuits of today. In particular, in high microprocessor and system-on-chip architectures, the SRAM cell array is the primary source of leakage current. So low-leakage SRAM design is essential. Today’s VLSI designs are all about cutting down on power dissipation, supply voltage, leakage currents, and chip area. However, raising these parameters increases sub-threshold leakage currents and power dissipation, reducing design performance. Increasing the cell area reduces leakage power dissipation in standby mode. To solve these problems, it is best to cut down on effective leakage currents and dynamic power dissipation. For low voltage and energy constraints, the power dissipation, area, and delay performance of the low-power design of the 6T-SRAM cell with the DTMOS technique for a proposed low-power SRAM will be implemented in the Tanner EDA tool in 22 nm technology. The power of both types of SRAM cells will be compared using low-power techniques and a power analysis.Keywords6T SRAMLow powerLeakagesSleep transistorsPower dissipation
Since decades, globally, need for flexible power system with high integration of wind energy has
increased rapidly. Presently, the generation of electricity with conventional methods has led to increase
in carbon emissions, to subdue these emissionshigh integration of wind energy in the power system is
required. Integrating wind energy in the power system caused high level of variability and uncertainty
in the power system. Toaccommodate these features of wind energy development offlexible power
system is required. Such ability of power system which can withstand the imbalance between the power
supply and demand caused due to integration of wind energy is known as power flexibility. Hence
inclusion of flexible power system for generation can reduce the effects of variability and uncertainty
caused due to integration of wind energy.This paper highlights power flexibility, need for assessment
of power flexibility, different evaluation methods developed to assess power flexibility thus providing
directions for future research in this field.
A Planar Inverted Fantenna (PIFA) design is presented at5.03-5.09GHz and 5.725-5.825GHz for
wireless local area network (WLAN) applications. Miniaturization of Patch antennaand reasonable
bandwidth is achieved in this work. The twocomplimentary single split ring resonators (CSSRR) have
been etched in the ground plane to achieved dual band operation. The proposed antenna provides
compact structure because of using PIFA configuration, while capacitive matching has been achieved by
gap coupling.Proposed antenna is simulated using CST V.12 simulator and Particle Swarm optimization
algorithm technique.
With the rapid development of semiconductor technology, chip integration is getting beyond imagination. Aging has become one of the main threats to circuit reliability. In order to develop aging degradation prediction, it is critical to evaluate aging to avoid circuit failures. At present, the research on aging prediction is mainly focused at the transistor and gate levels: at transistor level, the precision is high, but the speed is low; whereas, the gate-level accuracy is not high, but the speed is very fast. In this paper, a path-level aging prediction framework based on the novel critical gate is proposed. The 10-year Negative Bias Temperature Instability (NBTI) aging delay of the critical subcircuit extracted by the novel critical gate is obtained, and the aging delay trend is learnt by using a linear regression model. Then the critical path aging delay can be obtained quickly based on the framework developed by machine learning using the linear regression model. The experimental results of ISCAS’85 and ISCAS’89 benchmark circuits based on 45-nm PTM show that the proposed framework is superior to the existing methods.
The necessity for the development of compact, portable, and reliable electronic devices of enhanced speed and efficiency has prompted the scaling of CMOS devices to be indispensable. However, the benefit of scaling CMOS devices comes at the cost of increased leakage current in circuits. The variance in power consumption by these circuits incites detrimental impacts on the operational characteristics of the entire device. So, in this work, a novel leakage power reduction technique obtained by combining the Leakage Control Transistor (LECTOR) approach and drain gating approach is proposed. Both these subthreshold leakage minimization approaches are prominently used in Complementary Metal Oxide Semiconductor (CMOS) devices for curtailing the leakage power. The effectiveness of the proposed Integrated Drain Gating Lector (IDGL) technique in mitigating the leakage power is ascertained by designing a half adder circuit. Hence the overall leakage power is of 3.16nW & delay 69.12 µs in 180 nm technology, and in low scale technology of 90 nm the same leakage power decline to 2.19nW & delay is 65.45 µs.
This brief represents a low-power push–pull inverter by using dynamic threshold MOSFETs (DTMOSs). The trend in design and manufacturing in semiconductor production units and implementation of million and billion number of transistors in a single chip in very large scale integration is increasing day by day. The demand for Complementary MOSFET (CMOS) integrated circuits (ICs) is continually acceptable due to silent features like low-power consumption, reliable performance, low noise, lesser area, high-speed performance, and outgoing improvement in dealing out technology. However, due to the static circuit standby power and the probability of breakdown in dynamic circuits, a large reduction in the MOS transistor’s threshold voltage (Vt) occurs, resulting in a reduction in gate overdrive and as a result, the entire circuit’s speed of operation. A DTMOS with a low Vt when the MOS turns on and a high Vt when the MOS turns off can be used to overcome this issue. The proposed design is simulated in Cadence tool with 180 nm CMOS technology. It results the average propagation delay of 13.84 ps and average power of 1.39 µW. Therefore, this brief will be an appropriate block for any customized design circuit.
Due to the growing impact of subthreshold and gate leakage, static leakage is contributing more and more towards the power dissipation in deep submicron Nano CMOS technology. There have been many works on subthreshold leakage and techniques to reduce it, such as controlling the input vector to the circuit in standby mode, forcing stack and body bias control. In this tutorial paper we have reviewed the leakage current with change in drain source, gate and bulk voltages for 4 different submicron technologies using the latest PTM models. Simulation result shows the effect of gate leakage and subthreshold leakage in total leakage current for different input vectors for a stack of 3 Nano technology NMOS transistors, further analyzes also the subthreshold and total leakage variation with input vector in a stack of 4 Nano technology NMOS transistors.
The battery-driven portable systems are the lifeline of the modern era. Very large-scale integration (VLSI) designers are continuously working to enhance the performance of the portable systems. The small size, fast response and high battery back-up are the prime factors for the portable systems. Scaling down of the metal oxide semiconductor field effect transistor (MOSFET) dimensions is mandatory to design the low size systems. The power supply and the threshold voltage must be scaled-down with each new technology node in order to maintain the performance of the devices. The scaling down of the threshold voltage of the device produces leakage current. The amount of the leakage current is large at integration level and harms the characteristics of the systems. Therefore, leakage current mitigation is needed especially at lower technology nodes to boost the battery back-up of the portable systems. Number of leakage reduction techniques are available at different abstraction levels. In this review paper, a systematic flow of the low power VLSI field is explored with the target of the different existing circuit level leakage reduction techniques. NAND3 gate is designed and simulated at 16 nm technology node by using the different existing leakage reduction techniques for the comparison purpose.
Tunnel FET is recognized as one of the most promising candidates for ultra-low power applications due to its ultra-low off current and CMOS compatibility. However, some characteristics of TFET caused by asymmetric device structure and special conduction mechanism may make conventional topologies of logic circuits no longer applicable. Our previous work has reported that TFET stacking will result in severe current degradation, which makes traditional logic cells not applicable. In this paper, two solutions are proposed: first, from a logic cell perspective, novel hybrid TFET-MOSFET topologies of standard logic cells are proposed, which achieve more than 2 times lower hardware cost and intrinsic delay, hence up to 4 times lower area-power-delay product (APDP) than that of conventional TFET logic circuits. Compared to MOSFET logic circuits, the designs achieve almost 2 orders of magnitude lower power and up to 34 times lower APDP. Second, from a large-scale circuit perspective, an optimized digital front-end (DFE) is proposed. Taking serial peripheral interface (SPI) as an example, SPI circuit using the optimized DFE achieves 46% lower delay and 4 times lower APDP than that of traditional TFET SPI, and 3 orders of magnitude lower static power and APDP than that of MOSFET SPI.
With technology scaling, subthreshold leakage has dominated the overall power consumption in a design. Input vector control is an effective technique to minimize subthreshold leakage. Low leakage input vector determination is not often possible due to large design space and simulation time. Similarly, applying an appropriate minimum leakage vector (MLV) to each Register Transfer Level (RTL) module instance in a design often results in a low leakage state with significant area overhead. In this work, we propose a top-down and bottom-up approach for propagating the input vector interval to identify low leakage input vector at primary inputs of an RTL datapath. For each module, via Monte Carlo simulation, we identify a set of MLV intervals such that maximum leakage is within (say) 10% of the lowest leakage points. As the module bit width increases, exhaustive simulation to find the low leakage vector is not feasible. Further, we need to uniformly search the entire input space to obtain as many low leakage intervals as possible. Based on empirical observations, we observe self-similarity in the subthreshold leakage distribution of adder/multiplier modules with highly regular bit-slice architectures when input space is partitioned into smaller cells. This property enables the uniform search of low leakage vectors in the entire input space where the time taken for characterization increases linearly with the module size. We further process the reduced interval set with simulated annealing to arrive at the best low-leakage vector at the primary inputs. We also propose to reduce area overhead (in some cases to 0%) by choosing Primary Input (PI) MLVs such that resultant inputs to internal nodes are also MLVs. Compared to existing work, experimental results for DSP filters simulated in 16nm technology demonstrated leakage savings of 93.6% and 89.2% for top-down and bottom-up approaches with no area overhead.
Decreasing the power scattering of Integrated Circuits (IC) through design improvements is a noteworthy test in the design of convenient frameworks, elite processors and recollections. The restricted battery lifetime forces very strict requests on the general power dissemination of a compact framework. Additionally, the expansion in spillage streams with consistent patterns in Very Large Scale Integration (VLSI) innovation scaling is a noteworthy worry for deep submicron (DSM) circuit designers. Moreover, chip dependability and future of chips diminish with lessened supply voltage and expanded spillage. Subsequently, low power design of computerized integrated circuits has risen as a very dynamic and quickly creating field of Complementary Metal Oxide Semiconductor (CMOS) design. The approaches used to accomplish low power utilization in computerized frameworks traverse a wide range from device/process level to calculation level. This examination concentrates on limiting power utilization at circuit level. Efficient circuit level systems that decrease dynamic and spillage power utilization are investigated and broke down. Low power circuits for three classes of CMOS computerized circuits to be specific flip-flops, domino logic circuits (domino logic multiplexer and domino logic convey generator) and Static Random Access Memory (SRAM) cells are proposed, executed and broke down. As testing of information maintenance blames in CMOS SRAM cell is a very critical issue, a low power design for test (DFT) hardware for SRAM cell is additionally proposed and actualized.
The FINFET (Fin field-effect transistors) is projected as a favourable alternative to address challenges faced by continue scaling. Since nanometer procedure schemes are more advanced, the density of chip and frequency of operation have augmented, by making consumption of power in portable devices that are operated by battery could be a significant concern. Though for devices that are non-portable, the consumption of power is significant due to enhanced cooling & packaging costs and possible reliability issues. The metal oxide steady miniaturization semi-conductor field transistor by every novel generation of CMOS(Complementary Metal Oxide Semi-conductor) scheme enhances leakage currents because of minimum channel impacts. The power accounts that are in leakage has been enhancing in a large amount of total consumption of power in deep submicron schemes. Various strategies or schemes are proposes for lessening power leakage. Further, in a system on chip (SOC) designs, caches occupy a significant amount of area in DSP systems, leading to an increase in leakage power. Also, cache memories are used to store filter coefficients. Because of multiple gates, FINFETs structures have better electrostatic control over short channel effects, thus reduces leakage power effectively at the nano regime. In this paper, cache memory and FIR filter are designed by utilizing FINFETs at a 22-nanometer strategy utilizing HSPICE. The experimental outcomes exhibit that structures of FINFET have better leakage control over MOSFET and offers better performance.
Leakage current promises to be a major contributor to power dissipation in future technologies. Bounding the maximum and minimum
leakage current poses an important problem. Determining the maximum leakage ensures that the chip meets power dissipation
constraints. Applying an input pattern that minimizes leakage allows extending battery life when the circuit is in stand-by
mode. Finding such vectors can be expressed as a satisfiability problem. We apply in this paper an incremental SAT solver,
PBS [1], to find the minimum or maximum leakage current. The solver is called as a post-process to a randomvector- generation approach.
Our results indicate that using a such a generic SAT solver can improve on previously proposed random approaches [7].
Low supply voltage requires the device threshold to be reduced in order to maintain performance. As the device threshold voltage is reduced, it results in an exponential increase of leakage current in the subthreshold region. The leakage power is no longer negligible in such low voltage circuits. Estimates of maximum leakage power can be used in the design of the circuit to minimize the leakage power. The leakage power is dependent on the input vector. This input pattern dependence of the leakage power makes the problem of estimating the maximum leakage power a hard problem. In this paper, we present graph based algorithms for estimating the maximum leakage power. These algorithms are pattern-independent and do not require simulation of the circuit. Instead the circuit structure and the logic functionality of the components in the circuit are used to create a constraint graph. The problem of estimating the maximum leakage power is then transformed to an optimization problem on the constraint graph. Efficient algorithms on the graph are used to estimate the maximum leakage power dissipated by a circuit. We also present comparisons with exhaustive/long simulations for MCNC/ISCAS-85 benchmark circuits to verify the accuracy of the method
The state dependence of leakage can be exploited to obtain modest leakage savings in complementary metal-oxide-semiconductor (CMOS) circuits. However, one can modify circuits considering state dependence and achieve larger savings. We identify a low-leakage state and insert leakage-control transistors only where needed. Leakage levels are on the order of 35% to 90% lower than those obtained by state dependence alone. Using a modified standard-cell-design flow, area overhead for combinational logic was found to be on the order of 18%. The proposed technique minimizes performance impact, does not require multiple-threshold voltages, and supports a standard-cell-design flow.
In this paper, we propose a novel operation of a MOSFET that is
suitable for ultra-low voltage (0.6 V and below) VLSI circuits.
Experimental demonstration was carried out in a Silicon-On-Insulator
(SOI) technology. In this device, the threshold voltage of the device is
a function of its gate voltage, i.e., as the gate voltage increases the
threshold voltage (V<sub>t</sub>) drops resulting in a much higher
current drive than standard MOSFET for low-power supply voltages. On the
other hand, V<sub>t</sub> is high at V<sub>gs</sub>=0, therefore the
leakage current is low. We provide extensive experimental results and
two-dimensional (2-D) device and mixed-mode simulations to analyze this
device and compare its performance with a standard MOSFET. These results
verify excellent inverter dc characteristics down to V<sub>dd</sub>=0.2
V, and good ring oscillator performance down to 0.3 V for Dynamic
Threshold-Voltage MOSFET (DTMOS)
Low supply voltage requires the device threshold to be reduced in order to maintain performance. Due to the exponential relationship between leakage current and threshold voltage in the weak inversion region, leakage power can be no longer negligible in such circuits. In this paper we present a technique to accurately estimate leakage power by accurately modeling the leakage current in transistor stacks. The standby leakage current model has been verified by HSPICE. We demonstrate that the dependence of leakage power on primary input combinations can be accounted for by this model. Based on our analysis we can determine good bounds for leakage power in the standby mode. As a by-product of this analysis, we can also determine the set of input vectors which can put the circuits in the low-power standby mode. Results on a large number of benchmarks indicate that proper input selection can reduce the standby leakage power by more than 50% for some circuits. I. Introduction The increasing ...
This paper describes two runtime mechanisms for reducing the leakage current of a CMOS circuit. In both cases, it is assumed that the system or environment produces a "sleep" signal that can be used to indicate that the circuit is in a standby mode. In the first method, the "sleep" signal is used to shift in a new set of external inputs and pre-selected internal signals into the circuit with the goal of setting the logic values of all of the internal signals so as to minimize the total leakage current in the circuit. This minimization is possible because the leakage current of a CMOS gate is a strong function of the input combination applied to its inputs. In the second method, NMOS and PMOS transistors are added to some of the gates in the circuit to increase the controllability of the internal signals of the circuit and decrease the leakage current of the gates the "stack effect". This is, however, done carefully so that the minimum leakage is achieved subject to a delay constraint for all input-output paths in the circuit. In both cases, Boolean satisfiability is used to formulate the problems, which are subsequently solved by employing a highly efficient SAT solver. Experimental results on the circuits in the MCNC91 benchmark suite demonstrate that it is possible to reduce the leakage current by up to 70% in VLSI circuits at the expense of a very small overhead.
Subthreshold leakage current in deep submicron MOS transistors is
becoming a significant contributor to power dissipation in CMOS circuits
as threshold voltages and channel lengths are reduced. Consequently,
estimation of leakage current and identification of minimum and maximum
leakage conditions are becoming important, especially in low power
applications. In this paper we outline methods for estimating leakage at
the circuit level and then propose heuristic and exact algorithms to
accomplish the same task for random combinational logic. In most cases
the heuristic is found to obtain bounds on leakage that are close and
often identical to bounds determined by a complete branch and bound
search. Methods are also demonstrated to show how estimation accuracy
can be traded off against execution time. The proposed algorithms have
potential application in power management applications or quiescent
current (I<sub>D</sub>DQ) testing if one wished to control leakage by
application of appropriate input vectors. For a variety of benchmark
circuits, leakage was found to vary by as much as a factor of six over
the space of possible input vectors
Electrical Engineering Design of High Performance Microprocessor Circuits This book covers the design of next generation microprocessors in deep submicron CMOS technologies. The chapters in Design of High-Performance Microprocessor Circuits were written by some of the world's leading technologists, designers, and researchers. All levels of system abstraction are covered, but the emphasis rests squarely on circuit design. Examples are drawn from processors designed at AMD, Digital/Compaq, IBM, Intel, MIPS, Mitsubishi, Motorola, and Toshiba. Each topic of this invaluable reference stands alone so the chapters can be read in any order. The following topics are covered in depth: * Architectural constraints of CMOS VLSI design * Technology scaling, low-power devices, SOI, and process variations * Contemporary design styles including a survey of logic families, robust dynamic circuits, asynchronous logic, self-timed pipelines, and fast arithmetic units. * Latches, clocks and clock distribution, phase-locked and delay-locked loops * Register file, cache memory, and embedded DRAM design * High-speed signaling techniques and I/O design * ESD, electromigration, and hot-carrier reliability * CAD tools, including timing verification and the analysis of power distribution schemes * Test and testability Design of High-Performance Microprocessor Circuits assumes a basic knowledge of digital circuit design and device operation, and covers a broad range of circuit styles and VLSI design techniques. Packed with practical know-how, it is an indispensable reference for practicing circuit designers, architects, system designers, CAD tool developers, process technologists, and researchers. It is also an essential text for VLSI design courses.
Input vector control is an effective technique for reducing the leakage current of combinational VLSI circuits when these circuits are in the sleep mode. In this paper a design technique for applying the minimum leakage input to a sequential circuit is proposed. Our method uses the built-in scan-chain in a VLSI circuit to drive it with the minimum leakage vector when it enters the sleep mode. Using these scan registers eliminates the area and delay overhead of the additional circuitry that would otherwise be needed to apply the minimum leakage vector to the circuit. We show how the proposed technique can be used for several different scan-chain architectures and present the experimental results on the MCNC91 benchmark circuits.
While some leakage power reduction techniques require modification of process technology achieving savings at the fabrication stage, others are based on circuit-level optimizations and are applied at run-time. We focus our study on the latter kind and compare three techniques: input vector control, body bias control and power supply gating. We determine their limits and benefits, in terms of the potential leakage reduction, performance penalty and area and power overhead. The importance of the 'minimum idle time' parameter, as an additional evaluation tool, is emphasized, as well as the feasibility of achieving power supply gating at low levels of granularity. The obtained data supports the formulation of a comprehensive leakage reduction scheme, in which each technique is targeted for certain types of functional units and a given level of granularity depending on the incurred overhead cost and the obtainable savings
One of the most important features of current state-of-the-art SAT solvers is the use of conflict based backtracking and learning techniques. In this paper, we generalize various conflict driven learning strategies in terms of different partitioning schemes of the implication graph. We re-examine the learning techniques used in various SAT solvers and propose an array of new learning schemes. Extensive experiments with real world examples show that the best performing new learning scheme has at least a 2× speedup compared with learning schemes employed in state-of-the-art SAT solvers
We introduce SATIRE, a new satisfiability solver that is particularly suited to verification and optimization problems in electronic design automation. SATIRE builds on the most recent advances in satisfiability research, and includes two new features to achieve even higher performance: a facility for incrementally solving sets of related problems, and the ability to handle non-CNF constraints. We provide experimental evidence showing the effectiveness of these additions to classical satisfiability solvers.
A model to statistically characterize the leakage power of CMOS
digital circuits is presented. Based on the subthreshold leakage
characterization at transistor and cell level, the leakage power
consumption of a standard cell circuit is obtained. Also, in order to
estimate the leakage power variability for a fixed state, a model of
variations due to process is introduced. Using these models, the
P<sub>LEAK</sub> distribution is found to be asymmetric around the
nominal value showing a long tail for high consuming circuits. The model
has been found effective in evaluating the correlation of leakage power
with other performance specs, in particular delay. We have shown that an
IC with short L, and therefore, with high P<sub>LEAK</sub> will be
faster than nominal ones and an IC with long L, and therefore, with low
P<sub>LEAK</sub> will be slower. Predicted results are consistent with
available experimental data
The state dependence of leakage can be exploited to obtain modest leakage savings in CMOS circuits. However, one can modify circuits considering state dependence and achieve larger savings. We identify a low leakage state and insert leakage control transistors only where needed. Leakage levels are on the order of 35% to 90% lower than those obtained by state dependence alone
Reduction in leakage power has become an important concern in low voltage, low power and high performance applications. In this paper, we use dual threshold technique to reduce leakage power by assigning high threshold voltage to some transistors in non-critical paths, and using low-threshold transistors in critical paths. In order to achieve the best leakage power saving under target performance constraints, an algorithm is presented for selecting and assigning an optimal high threshold voltage. A general standby leakage current model which has been verified by HSPICE is used to estimate standby leakage power. Results show that dual threshold technique is good for power reduction during both standby and active modes. The standby leakage power savings for some ISCAS benchmarks can be more than 50%.
Low supply voltage requires the device threshold to be reduced in order to maintain performance. Due to the exponential relationship between leakage current and threshold voltage in the weak inversion region, leakage power can no longer be ignored. In this paper we present a technique to accurately estimate leakage power by accurately modeling the leakage current in transistor stacks. The standby leakage current model has been verified by HSPICE. We demonstrate that the dependence of leakage power on primary input combinations can be accounted for by this model. Based on our analysis we can determine good bounds for leakage power in the standby mode. As a by-product-of this analysis, we can also determine the set of input vectors which can put the circuits in the low-power standby mode. Results on a large number of benchmarks indicate that proper input selection can reduce the standby leakage power by more than 50% for some circuits.
A new standby leakage control technique, which exploits the
leakage reduction offered by transistor stacks with “more than one
`off' device”, demonstrates 2× reduction in standby leakage
power for a 32-bit static CMOS adder in a low-Vt, sub-1V, 0.1 μm
technology. Leakage reduction is achieved with minimal overheads in
area, power and process technology. The dynamics of leakage reduction
due to transistor stacks, and its influence on the overall leakage power
of large circuits are elucidated for the first time
In order to reduce the power dissipation of CMOS products,
semiconductor manufacturers are reducing the power supply voltage. This
requires that the transistor threshold voltages be reduced as well to
maintain adequate performance and noise margins. However, this increases
the subthreshold leakage current of p and n MOSFETs, which starts to
offset the power savings obtained from power supply reduction. This
problem will worsen in future generations of technology, as threshold
voltages are reduced further. In order to overcome this, we propose a
design technique that can be used during logic design in order to reduce
the leakage current and power. We target designs where parts of the
circuit are put in “standby” mode when not in use, which is
becoming a common approach for low power design. The proposed design
changes consist of minimal overhead circuitry that puts the circuit into
a “low leakage standby state”, whenever it goes into
standby, and allows it to return to its original state when it is
reactivated. We give an efficient algorithm for computing a good low
leakage power state. We demonstrate this method on the ISCAS-89
benchmark suite and show leakage power reductions of up to 54% for some
circuits
The author describes the Boolean satisfiability method for
generating test patterns for single stuck-at faults in combinational
circuits. This new method generates test patterns in two steps: first,
it constructs a formula expressing the Boolean difference between the
unfaulted and faulted circuits, and second, it applies a Boolean
satisfiability algorithm to the resulting formula. This approach differs
from previous methods now in use, which search the circuit structure
directly instead of constructing a formula from it. The new method is
general and effective. It allows for the addition of heuristics used by
structural search methods, and it has produced excellent results on
popular test pattern generation benchmarks
Scaling advanced CMOS technology to the next generation improves
performance, increases transistor density, and reduces power
consumption. Technology scaling typically has three main goals: 1)
reduce gate delay by 30%, resulting in an increase in operating
frequency of about 43%; 2) double transistor density; and 3) reduce
energy per transition by about 65%, saving 50% of power (at a 43%
increase in frequency). These are not ad hoc goals; rather, they follow
scaling theory. This article looks closely at past trends in technology
scaling and how well microprocessor technology and products have met
these goals. It also projects the challenges that lie ahead if these
trends continue. This analysis uses data from various Intel
microprocessors; however, this study is equally applicable to other
types of logic designs. Is process technology meeting the goals
predicted by scaling theory? An analysis of microprocessor performance,
transistor density, and power trends through successive technology
generations helps identify potential limiters of scaling, performance,
and integration
A 4 mm<sup>2</sup>, two-dimensional (2-D) 8×8 discrete
cosine transform (DCT) core processor for HDTV-resolution video
compression/decompression in a 0.3-μm CMOS triple-well, double-metal
technology operates at 150 MHz from a 0.9-V power supply and consumes 10
mW, only 2% power dissipation of a previous 3.3-V design. Circuit
techniques for dynamically varying threshold voltage (VT scheme) are
introduced to reduce active power dissipation with negligible overhead
in speed, standby power dissipation, and chip area. A way to explore V
<sub>DD</sub>-V<sub>th</sub> design space is also studied
1-V power supply high-speed low-power digital circuit technology
with 0.5-μm multithreshold-voltage CMOS (MTCMOS) is proposed. This
technology features both low-threshold voltage and high-threshold
voltage MOSFET's in a single LSI. The low-threshold voltage MOSFET's
enhance speed performance at a low supply voltage of 1 V or less, while
the high-threshold voltage MOSFET's suppress the stand-by leakage
current during the sleep period. This technology has brought about logic
gate characteristics of a 1.7-ns propagation delay time and
0.3-μW/MHz/gate power dissipation with a standard load. In addition,
an MTCMOS standard cell library has been developed so that conventional
CAD tools can be used to lay out low-voltage LSI's. To demonstrate
MTCMOS's effectiveness, a PLL LSI based on standard cells was designed
as a carrying vehicle. 18-MHz operation at 1 V was achieved using a
0.5-μm CMOS process
Design of High Performance Microprocessor Circuits Design Challenges of Technology Scaling Characterization of Leakage Power in CMOS Technologies
- A Chandrakasan
- W Bowhill
- F Fox
- S Borkar
- A Ferre
- J Figueras
[1]
Chandrakasan, A., Bowhill, W. and Fox, F., Design of High Performance Microprocessor Circuits, IEEE Press. 2000.
[2]
Borkar, S., " Design Challenges of Technology Scaling ", IEEE MICRO, July-August 1999.
[3]
Ferre, A. and Figueras, J., " Characterization of Leakage Power in CMOS Technologies ", Proc. of IEEE Int'l
Conference on Electronics, Circuits and Systems, Vol. 2, 1998, pp. 85 –188.
1-V power supply high-speed digital circuit technology with multi-threshold voltage CMOS
- S Mutoh
- T Douskei
- Y Matsuya
- T Aoki
- S Shigematsu
- J Yamada
Mutoh, S., Douskei, T., Matsuya, Y., Aoki, T., Shigematsu, S. and Yamada J., "1-V Power Supply High-Speed Digital
Circuit Technology with Multi-threshold Voltage CMOS," IEEE Journal of Solid-state Circuits, Aug. 1995, pp. 847-854.