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A Wide Tuning Range, Low Phase Noise, and Area Efficient Dual-Band Millimeter-Wave CMOS VCO Based on Switching Cores
Abstract
This paper presents a millimeter-wave wide tuning range voltage-controlled oscillator (VCO) incorporating two switchable decoupled VCO cores. When the first core is switched on producing the low frequency band (LFB) signal and the second core is off, the inductors of the second core are reused to create additional buffers that pass the LFB signal to the output buffers. The generated high frequency band (HFB) signals by the second core when turned on, are directly fed to the output buffers. Producing the outputs of both VCO cores across same terminals without utilizing active/passive combiners and coupled inductors will enhance the phase noise performance of the VCO, increase its output power, and reduce the chip size. Fabricated in a 65-nm CMOS process, the VCO achieves a measured wide tuning range of 26.2% from 54.1 to 70.4 GHz while consuming 7.4-11.2-mA current from 1-V power supply. The peak measured phase noise at 10-MHz offset is -116.3 dBc/Hz and the corresponding FOMT and FOM varies from -180.96 to -191.86 dB and -172.6 to -183.5 dB, respectively. The VCO core area occupies only 0.1 x 0.395 μm².
... Multi-core VCOs using two or more coupled VCOs with overlapping frequency range are used to realize wideband VCOs [11,12,13,14,15,16,17,18,19,20,21,22]. The conventional switching core approach for high FTR is proposed in previous studies [11,12,13,14]. ...
... Multi-core VCOs using two or more coupled VCOs with overlapping frequency range are used to realize wideband VCOs [11,12,13,14,15,16,17,18,19,20,21,22]. The conventional switching core approach for high FTR is proposed in previous studies [11,12,13,14]. The results show that the presence of switching losses and parasitic capacitance leads to degraded PN performance and reduced FTR at mm-wave frequencies. ...
... Under low-Q case, the resonant frequency of tank1 and tank2 can be expressed as shown in Eq. (14) and Eq. (15): ...
A dual-mode wide tuning range voltage-controlled oscillator (VCO) based on switchable weakly coupled cores is presented in this paper. The dual-mode operation is achieved when the two switched VCO cores are under ON and OFF states. A weakly coupled transformer with small coupling coefficient of the two-coupled LC tanks of two VCO cores is used to ensure that the VCO works at desired frequency under both modes. The results show that large coupling coefficient between the LC tank of two VCOs and LC tank of buffer enhances the quality factor of the VCO’s LC tank at lower resonant frequency under both modes. Fabricated in a 55 nm CMOS process, the VCO covers the frequency tuning range from 22.3 to 27.1 GHz and from 31.2 to 36.6 GHz when the switched VCO is under ON or OFF state, respectively. The dual-mode VCO achieves a phase noise of -127.6 dBc/Hz at 10 MHz offset for 22.3 GHz carrier frequency.
... However, the amount of cancellation capacitance is traded off with degradation in PN and power consumption at mm-Wave. Alternatively, a mode-switching architecture, employing two or more switched VCO cores and carefully sharing some of the tank elements among the VCO cores, has been proposed to minimize the size or avoid the use of a C-DAC array [12]- [14]. However, this approach incurs some design complexity, as well as an area and parasitic loading overhead. ...
... As a proof of concept, a robust 5G LC-VCO covering the 24-29-GHz frequency bands with sufficient margin is designed in a digital 45-nm CMOS silicon-on-insulator (SOI) technology using a double folded feedline (DFF) for the C-DAC structure. It is worth noting that no special circuits or architectural enhancement techniques were augmented to further improve the proposed approach [12], [18] since the overall goal of this work is to highlight the significance of the C-DAC design and the efficacy of the proposed structure. ...
... The schematic of the proposed VCO core, implemented in a digital 45-nm CMOS SOI process, is shown in Fig. 14(a). The selection of a standard top-biased LC-VCO topology demonstrates the improved inherent performance of the proposed structure without utilization of architectural enhancement techniques to further improve the performance [12], [16]. For optimum PN [3], the LC tank utilizes a small (∼110 pH) single-turn differential inductor with a Q-factor >30 across the frequency band. ...
This article presents a detailed analysis of the impact of the tank feedline on tuning range (TR) and phase noise (PN) in millimeter-wave
LC
voltage-controlled oscillators (VCOs). A robust extended TR design, with low PN and small die area, is later proposed, analyzed, and experimentally validated. A new interconnect approach for the coarse tuning capacitor bank is used to significantly reduce the
LC
tank routing capacitance and resistance, thus improving the TR and PN of the VCO. As a proof of concept, a 26.8-GHz VCO with a 5-bit digitally switched-capacitor bank [capacitor digital-to-analog converter (C-DAC)] is implemented using a folded feedline routing structure in a digital 45-nm CMOS silicon-on-insulator (SOI) technology. Compared to a conventional layout structure, the proposed interconnect technique yields a wider TR and lower losses while significantly improving the linearity of the C-DAC. The fabricated VCO yields a TR of 33%, covering the extended 5G frequency band with a sufficient margin from 22.4 to 31.2 GHz, with a minimum overlap of 40%. Moreover, it achieves a PN of −105.5 and −97.2 dBc/Hz at a 1-MHz offset at the low and high bands, respectively, while dissipating 6 mW from a 1.0-V supply, corresponding to an average FOM
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of −192.6 dBc/Hz.
... However, the lossy coupled resonators along with the required power combiners at the output of these VCOs considerably add to the power consumption and area while degrading the noise performance of the oscillators. An area-efficient dual-core VCO with small size-varactors and standalone inductors is presented in [1] to increase the FTR along with the high-Q resonator resulting in a better PN performance. There the inductor of high-frequency band core is used as the load for the internal buffer/combiner to pass the signal of low-frequency band to the output buffer. ...
... For a conventional cross-coupled LC-VCO [1], the oscillation frequency is given as ...
... From (2), if Q of the inductor is high (e.g. more than 30), Q of the tank is determined by Q var in low-Q mode. However, as it is discussed in [1], higher Q of the inductor can improve the LC-tank quality factor leading to better PN performance. By expanding (16) to ...
This paper presents a wide-tuning range dual-mode millimeter wave (mm-wave) voltage controlled oscillator (VCO) incorporating high quality-factor (Q) transformer-based variable inductors. A high Q switched inductor with two different values is proposed by constructing the load of a transformer of a high Q fixed capacitor in series with a lossless switch structure that does not add any loss to the LC-tank as implemented by changing the signals mode across the capacitor. By choosing a proper center frequency for each mode and sufficient frequency overlap, a wide frequency tuning range (FTR) mm-wave VCO can be designed. It provides almost twice higher tuning range while keeping phase noise (PN) nearly the same as the two-mode VCO designed with two standalone inductors. Fabricated in a 65 nm CMOS process, the VCO demonstrates the measured FTR of 22.8% from 64.88 to 81.6 GHz range. The measured peak PN at 10 MHz offset is -114.63 dBc/Hz and the maximum and minimum corresponding figures of merit FOM and FOMT are -173.9 to -181.84 dB and -181.07 to -189 dB, respectively. The VCO cores consume 10.2 mA current from 1 V power supply, and the occupied area is 0.146 x0.205 mm².
... Moreover, operation at a high frequency is unstable due to the oscillation frequency being near the self-resonance frequency (SRF), and the absence of fine-tuning causes a dead-zone. In [4], a switchable multi-core VCO using switch transistor or transformer is designed to realize multiple frequency bands. However, the parasitic capacitance of the switch transistor shifts the tuning range down, and the transformer has a much lower Q than a standalone inductor. ...
... A cross-coupled transistor pair compensating for the loss of the LC tank, a tied tail current source comprising the VCO core, and a buffer for impedance matching has been designed. The target tuning range is 18.82 -23.28 GHz, which is a portion of the K-band, and it is slightly raised in consideration of the parasitic capacitance of the switch transistor, which is an issue in [4]. ...
A wideband LC voltage-controlled oscillator (VCO) using a 3-bit switched-capacitor bank is proposed for improving the frequency bandwidth in K-band applications. The capacitor bank is composed of metal-oxide-metal (MOM) capacitors to obtain a high-quality factor of the LC tank. The size of the unit capacitor in the capacitor bank is optimized to achieve a wide tuning range. The fabricated chip area is 400 µm × 610 µm by using the TSMC 65-nm RF CMOS process. The overall tuning range of the proposed VCO is from 18.82 to 23.28 GHz in measurement, and it consumes 46.4 mW, including a buffer stage at a 1 V supply voltage. The measured phase noise is −105.8 dBc/Hz at a 1-MHz offset frequency. A figure-of-merit (FOM) and FOM incorporating the tuning range (FOMT) are −179 dBc/Hz and −185.2 dBc/Hz at a 1-MHz offset from the center frequency, respectively.
... However, SW considerably increases both resistive losses and parasitic capacitances of the VCO tank, thus affecting PN and limiting the maximum VCO operating frequency and TR. To overcome this issue, the switched core solution proposed in [50] can be used, which takes advantage of two different VCOs, each one operated with an LC-tank that is designed to address a specific application (i.e., LR or S/MR applications). This allows both SM/R and LR requirements to be fulfilled at the cost of a larger silicon area occupation and higher system complexity. ...
This paper presents recent results on CMOS integrated circuits for automotive radar sensor applications in the 77 GHz frequency band. It is well demonstrated that nano-scale CMOS technologies are the best solution for the implementation of low-cost and high-performance mm-wave radar sensors since they provide high integration level besides supporting high-speed digital processing. The present work is mainly focused on the RF front-end and summarizes the most stringent requirements of both short/medium- and long-range radar applications. After a brief introduction of the adopted technology, the paper addresses the critical building blocks of the receiver and transmitter chain while discussing crucial design aspects to meet the final performance. Specifically, effective circuit topologies are presented, which concern mixer, variable-gain amplifier, and filter for the receiver, as well as frequency doubler and power amplifier for the transmitter. Moreover, a voltage-controlled oscillator for a PLL efficiently covering the two radar bands is described. Finally, the circuit description is accompanied by experimental results of an integrated implementation in a 28 nm fully depleted silicon-on-insulator CMOS technology.
... To minimize the frequency tuning step, the coupling coefficient of the transformer k is set to 0.21. In addition, the detrimental effects of parasitic capacitance in the tuning bank can also be reduced by using a coupled transformer with such a small k [17][18][19] . The binary-weighted array of switched capacitors connected to the transformer's secondary coil can be used to achieve smaller fine-tuning steps. ...
An optimized millimeter-wave digital controlled oscillator (DCO) in a 40-nm CMOS process is presented in this work. The coarse-tuning modules and medium-tuning modules of the DCO utilize modified binary-weighted digitally controlled transmission lines (DCTLs) to achieve a better compromise among smaller chip size, higher resonant frequency, better tuning resolution and lower phase noise. The tuning precision and die size of the medium tuning bank are improved without changing the binary coding rules by replacing the lowest-weight bit of the DCTLs with switched capacitors. In comparison with traditional DCTLs, the control bits of the coarse and medium tuning modules have been changed from 30 to 8, resulting in a 34.4% reduction in overall length (from 122[Formula: see text]m to 80[Formula: see text]m). In addition, the DCO's fine-tuning modules are achieved using a binary-weighted switched capacitors array connected to the secondary winding of a low-coupling transformer, which enhances the DCO's fine-tuning bank for better frequency resolution with less circuit complexity. The measured tuning range of the optimized DCO is 76-81GHz with a smaller die size of 0.12mm[Formula: see text]. This results in an outstanding figure of merit ([Formula: see text]) of - 190.52dBc/Hz.
... In power electronics, one key parameter to examine is %THD, which represents a system's power efficiency. The lower the percentage of THD, the greater the power efficiency [2]. Oscillators are categorized into two types: ring and LC voltage controlled oscillator (LC VCO). ...
A novel delay cell circuit for differential ring oscillator (DRO) with large tuning range along with application in charge pump phase lock loop (CP-PLL) frequency synthesizer has been presented in this paper. Using 0.18\(\mu \)m CMOS technology with power supply of 1.8 V, the two DRO architectures: 3-stage and 5-stage, were built and simulated. In both 3-stage and 5-stage DROs, single controlled voltage is employed. The suggested 3-stage and 5-stage DRO circuits generate a tuning range of 96.77 MHz\(-\)5.296 GHz and 36.33 MHz\(-\)2.803 GHz, respectively. The % total harmonic distortion (%THD) of both DRO architectures is also evaluated. The suggested 3-stage and 5-stage DROs consume 6.63 mW and 11.05 mW power at an oscillation frequency of 4.76 GHz and 2.479 GHz, respectively. At an offset frequency of 10 MHz from the oscillation frequency, the proposed circuits have phase noise of \(-\)119.93 dBc/Hz and \(-\)128.24 dBc/Hz, respectively. The layout of proposed design has been drawn and pre- and post-layout simulation results show satisfactory variations of tuning range and phase noise of proposed design. The suggested circuit’s robustness is verified with the help of PVT and Monte Carlo analysis. When compared to contemporary research, the proposed DROs have the widest tuning range. Proposed DRO application in CP-PLL frequency synthesizer has locking time of 1.17 \(\upmu \)s and shows good settling behaviour with dynamic parameter variations.
... Nevertheless, at the state of the art, dual-band operation is typically achieved by means of LC VCOs with switched components, such as switched capacitor (SC) [16], switched inductor (SL) [17], or switched core [18], as schematically shown in Fig. 6(a)-(c), respectively. SC-and SL-based VCOs exploit a shunt switch, SW, to enable/disable either a capacitor or an inductor. ...
This article presents a 77-GHz transmitter (TX) in a 28-nm fully depleted silicon-on-insulator CMOS technology for automotive radar applications. The circuit has been designed to simultaneously fulfill both short-/medium-range (S/MR) and long-range (LR) operations. It exploits an LO frequency doubling architecture, which allows preventing voltage-controlled oscillator (VCO) pulling effects for improved phase noise (PN) performance. The proposed TX comprises a 38-GHz VCO driving a frequency doubler and then a current-combining two-path power amplifier. The VCO takes advantage of a novel tank architecture to cope S/MR and LR requirements with an effective and silicon area-saving solution. The proposed TX also features a feedback loop that allows properly setting the power delivered to the output load. It exhibits a 5-GHz bandwidth, ranging from 76 to 81 GHz, with a PN performance as low as
$-$
93 dBc/Hz at a 1-MHz offset frequency from a 77-GHz carrier. It is also able to deliver a maximum output power as high as 17.5 dBm with a dynamic control range of around 13 dB. The overall power consumption is 351 mW.
... Owing to the higher phase noise performance, LC-tank VCOs with spiral inductors and varactors are extensively adopted in radio frequency circuit implementations [21]. Theoretically, the VCO tuning range is determined by the maximum to minimum capacitance ratio of the varactor [22,23]. The tuning range of an LC-tank VCO is approximately restricted for a classical capacitance ratio in a typical CMOS process, rendering it unsuitable for wideband applications. ...
The inductor was primarily developed on a low-voltage CMOS tunable active inductor (CTAI) for radar applications. Technically, the factors to be considered for VCO design are power consumption, low silicon area, high frequency with reasonable phase noise, an immense quality (Q) factor, and a large frequency tuning range (FTR). We used CMOS tunable active inductor (TAI) topology relying on cascode methodology for 24 GHz frequency operation. The newly configured TAI adopts the additive capacitor (Cad) with the cascode approach, and in the subthreshold region, one of the transistors functions as the TAI. The study, simulations, and measurements were performed using 65nm CMOS technology. The assembled circuit yields a spectrum from 21.79 to 29.92 GHz output frequency that enables sustainable platforms for K-band and Ka-band operations. The proposed design of TAI demonstrates a maximum Q-factor of 6825, and desirable phase noise variations of -112.43 and -133.27 dBc/Hz at 1 and 10 MHz offset frequencies for the VCO, respectively. Further, it includes enhanced power consumption that varies from 12.61 to 23.12 mW and a noise figure (NF) of 3.28 dB for a 24 GHz radar application under a low supply voltage of 0.9 V.
... Usually, the voltage-controlled oscillator (VCO) and the millimeter-wave frequency divider need to work in high frequencies and a wide band. Recently, some wideband VCOs [9,10,11] and multi-mode VCOs [12,13,14,15,16,17] have been demonstrated with ultra-wide tuning bands. For example, [9] exhibits a wideband VCO with a 39.5% relative tuning range. ...
This paper presents an ultra-wideband injection-locked frequency divider (ILFD) design which is applicable to a multi-applications system. A transformer-based multi-order resonator is utilized in the ILFD to attain a flat phase response. The passive injection-boosted technique is proposed to increase the injection signal amplitude and thus widen the locking range. With the injection-boosted technique and the multi-order resonator, the proposed ILFD demonstrates a measured locking range of 50 GHz, covering 48 GHz to 98 GHz. The divider designed in a 40-nm process consumes a DC power of 11.2 mW excluding buffers and occupies a core size of 0.38 × 0.63 mm².
... Not only varactor tuning cannot provide sufficient tuning range but also its big size is sensitive to input noise. That is why there are growing efforts to get multi-standard LO, focusing on implementation of both broadband LOs and dual-band and multiband LO topologies with low phase noise and low current consumption [1][2][3][4]. ...
Using an analytical approach, new design for a dual band LC oscillator is presented. The core of circuit contains a cross coupled CMOS LC oscillator with two serried LC tanks so that the inductors of the two serried tanks have mutual inductance. There are some switches in the circuit that change mutual inductance direction to produce two different frequencies. This technique increases the oscillation amplitude in the same power consumption and consequently decreases the phase noise. In fact using two serried LC tank somehow compensate the injected phase noise from switches. The symmetrical structure is another advantage of the circuit that makes it possible to be used in multiphase oscillator. To evaluate the proposed circuit, a dual band quadrature LC-Tank oscillator has been design to oscillate at 3.8 GHz and 6.7 GHz with 1.8 V supply and 2 mA current consumption. The circuit has been simulated using TSMC 0.18 CMOS practical model where all the results confirm the analytical results.
... Among the currently available designs, the authors in [5] introduced a wide-band VCO implemented by CMOS differential stages connected in a ring topology. Other design guidelines to improve the VCO's performance can be found in [16][17][18][19]. ...
The optimization of analog integrated circuits requires to take into account a number of considerations and trade-offs that are specific to each circuit, meaning that each case of design may be subject to different constraints to accomplish target specifications. This paper shows the single-objective optimization of a complementary metal-oxide-semiconductor (CMOS) four-stage voltage-controlled oscillator (VCO) to maximize the oscillation frequency. The stages are designed by using CMOS current-mode logic or differential pairs and are connected in a ring structure. The optimization is performed by applying differential evolution (DE) algorithm, in which the design variables are the control voltage and the transistors’ widths and lengths. The objective is maximizing the oscillation frequency under the constraints so that the CMOS VCO be robust to Monte Carlo simulations and to process-voltage-temperature (PVT) variations. The optimization results show that DE provides feasible solutions oscillating at 5 GHz with a wide control voltage range and robust to both Monte Carlo and PVT analyses.
... In this manner, this article introduces the design of a wide-band voltage-controlled oscillator (VCO) that is implemented using CML stages connected in a ring topology. It is worth mentioning that designing VCOs is a challenge [4][5][6]; besides, one can find guidelines to deal with modern design issues, such as ultra-low-power requirements [7]. Other important applications require robust VCOs, such as in designing analog-to-digital converters [8,9] or phase-locked loops [10]. ...
The design of a wide-band voltage-controlled oscillator (VCO) modified as a VCO with programmable tail currents is introduced herein. The VCO is implemented by using CMOS current-mode logic stages, which are based on differential pairs that are connected in a ring topology. SPICE simulation results show that the VCO operates within the frequency ranges of 2.65–5.65 GHz, and when it is modified, the VCO with programmable tail currents operates between 1.38 GHz and 4.72 GHz. The design of the CMOS differential stage is detailed along with the symbolic approximation of its dominant pole, which is varied to increase the frequency response in order to achieve a higher oscillation frequency when implementing the ring oscillator structure. The layout of the VCO is described and pre- and post-layout simulations are provided, which are in good agreement using CMOS technology of 180 nm. Finally, process, voltage and temperature variations are performed to guarantee robustness of the designed CMOS ring oscillator.
Conventional transformer-based magnetic tuning has demonstrated dual-band or even multi-band operation for voltage-controlled oscillators (VCOs). However, the destructive magnetic coupling employed introduces implicit loss to the transformer thus degrading its quality factor (Q), and achieves a continuous frequency coverage resulting in inferior performance. To address this issue, this paper proposes a constructive switched magnetic coupling (CSMC) technique, realizing dual-band operation with the Q improvement into one band due to the in-phase coupling and the explicit switch. For validation, a transformer employing the CSMC technique is designed and deployed in a dual-band VCO design. Fabricated in a 65-nm CMOS process, the VCO is measured with an oscillation frequency range of 37.8%, from 11.3 to 16.6 GHz, while consuming 2.5-mW from a 0.65-V voltage supply. Within the entire frequency coverage, the measured phase noise ranges from –129.6 to –123.7 at 10-MHz offset, resulting in FoM of 186-192.1 dBc/Hz. The core area of the chip is 0.43×0.25 mm
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excluding pads.
Voltage-controlled Oscillator (VCO) is a prominent part that has been used to generate a stable frequency for the high-frequency transceiver system. This survey encompasses a comparative analysis of two commonly used VCO architectures: the Ring VCO and LC-VCO. The Ring VCO has been constructed with the collection of ring delay cells. Moreover, the LC-VCO utilizes inductors, capacitors, fine-tuning circuits, coarse-tuning circuits to generate frequency. Furthermore, this study investigates an in-depth exploration of VCO structures, operational principles, advantages, limitations, and performance metrics. In addition, it evaluates performance parameters, including operating frequency range, phase noise, figure of merit, and tuning techniques. This research suggests that based on the application and its requirements, the VCO performance parameters need to be varied. This survey employs diverse types of VCO, and its design methods. Implications for future research and study of VCO design and integration are discussed.
The design of a wide tuning range LC-Voltage controlled oscillators (VCOs) in CMOS technology presents certain challenges, including the low-quality factor that is associated with passive elements and the considerable impact of routing parasitics. The challenges necessitate an innovative approach to the methodology employed in designing VCOs. This paper presents a design methodology of an extended wide TR LC-VCO utilizing a folded feedline layout-based parasitic reduction technique. Furthermore, the technique being proposed relaxes the required \({g}_{m}\) for the oscillation startup condition, thereby diminishing power consumption and phase noise.KeywordsFigure-of-merit (FOM)phase noiseLC voltage-controlled oscillator (LC-VCO)wide tuning rangefolded feedline
This letter presents a dual-core, wide-tuning, class-C voltage-controlled oscillator (VCO) operating at millimeter-wave (mm-wave) frequencies. Each core contains a 7-bit switched capacitor array and a switchable transformer to maximize the entire tuning range. The proposed class-C VCO can achieve low phase noise (PN) by using a noise-filtering technique that blocks the second-harmonic current. The two VCO cores can be turned on or off by setting their bias voltages, eliminating the need for switching transistors in the high-frequency signal path. The proposed dual-core class-C VCO was designed and fabricated using 28-nm CMOS technology, with a core area of 0.048 mm
$^{2}$
. The average measured PN is
$-$
116 dBc/Hz at 10-MHz offset with a carrier of 36.96 GHz. The tuning range is 39%, from 31 to 46 GHz. The VCO consumes a dc power of 6.8 to 9.9 mW, achieving 181.8 dBc/Hz FOM and 193.6 dBc/Hz FOMT, respectively.
The rapid development of wireless communications, software-defined radios, and ultrawideband (UWB) engenders an ever-increasing demand for clock generators that fully covers multiple frequency bands
[1]
,
[2]
,
[3]
. As the “heartbeat” that pumps clock generators, such as phase-locked loops (PLLs), microwave oscillators with wideband frequency tuning range (TR) are thus attracting a great deal of research interest.
Ultra-high-speed data communication receivers (Rxs) conventionally require analog digital converters (ADC)s with high sampling rates which have design challenges in terms of adequate resolution and power. This leads to ultra-high-speed Rxs utilising expensive and bulky high-speed oscilloscopes which are extremely inefficient for demodulation, in terms of power and size. Designing energy-efficient mixed-signal and baseband units for ultra-high-speed Rxs requires a paradigm approach detailed in this paper that circumvents the use of power-hungry ADCs by employing low-power analog processing. The low-power analog Rx employs direct-demodulation with RF correlation using low-power comparators. The Rx is able to support multiple modulations with highest modulation of 16-QAM reported so far for direct-demodulation with RF correlation. Simulations using Matlab, Simulink R2020a® indicate sufficient symbol-error rate (SER) performance at a symbol rate of 8 GS/s for the 71 GHz Urban Micro Cell and 140 GHz indoor channels. Power analysis undertaken with current analog, hybrid and digital beamforming approaches requiring ADCs indicates considerable power savings. This novel approach can be adopted for ultra-high-speed Rxs envisaged for beyond fifth generation (B5G)/sixth generation (6G)/ terahertz (THz) communication without the power-hungry ADCs, leading to low-power integrated design solutions.
In this paper, the dual common-mode (CM) resonance technique is proposed for lowering the phase noise (PN) and flicker PN corner of LC voltage-controlled oscillators (VCOs) across wide tuning range. The dual CM resonator can provide high and resistive input impedance across a wide
$2^{\mathbf {nd}}$
harmonic band without dedicated tuning. It can both prevent the tank-loading effect and reshape the output waveform. Novel implementation methods are demonstrated to realize dual CM resonance at high frequencies. For comparison, both the dual CM resonance VCO and a reference one with a tail filter are fabricated in 65-nm CMOS, achieving the measured frequency range of 8-11.15 and 7.98-11.3 GHz, respectively. In 1/f
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region, the proposed VCO shows an average PN of −139 dBc/Hz and the FOM of 190-192.3 dBc/Hz across the band, leading to an excellent FOM
$_{\mathbf {T}}$
of larger than 200.3 dBc/Hz. The reference VCO shows the average PN and FOM of -137.7 and 190.5 dBc/Hz. In 1/f
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region, the former exhibits a low flicker PN corner of 280–350 kHz while the latter’s flicker PN corner varies largely from 290 to 950 kHz across the band. Both VCOs’ cores consume about 5 mW at 1 V supply and occupy approximately 0.13 mm
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.
This brief proposes a complementary common gate frequency doubler with a cross-coupling technique for conversion gain enhancement. The proposed frequency doubler enables a low-power and high-conversion-gain operation by implementing a current-reuse technique through a complementary architecture and a transconductance enhancement technique based on cross-coupling. The cross-coupling technique increases the effective input voltage by two times, resulting in a four-fold increase in the conversion gain. In this manner, the proposed technique can achieve a high conversion gain with low power consumption. A prototype frequency doubler is fabricated in a 28-nm CMOS SOI. Measurement results show a peak conversion gain of −1.41 dB at an output frequency of 79 GHz with a power consumption of 9.23 mW.
A reconfigurable injection-locked frequency multiplier (RE-ILFM) with both frequency
$\times 2$
doubler mode (DM) and
$\times 3$
tripler mode (TM) is proposed to increase both the operation frequency range and power efficiency. The proposed wideband RE-ILFM has common input and output ports by switching the working DM and TM without any calibration. For TM, harmonic suppression technology (HST) composed of notch filtering and transformer injection-coupling network is presented to optimize the harmonic rejection. For DM, an injection device composed of push-push pair operates in class-C to reduce power consumption and improve second-order harmonic current. Moreover, the concept of a dual core with multiple tanks is first introduced into ILFM, which can effectively improve the magnitude of output signal compared with traditional methods. The proposed RE-ILFM is designed and fabricated in a 55-nm CMOS process. The measurement results show that under a 0-dBm differential injection power, the RE-ILFM can achieve the bandwidth from 20.7 to 43.8 GHz, i.e., 71.6% with a good harmonic rejection of better than 27-dB using HST. From 22 to 30 GHz and 35.4 to 42 GHz for 28 and 39-GHz mm-wave fifth-generation bands, the RE-ILFM can achieve a differential output power of −5.9 to −14.06 dBm and −9.38 to −13.48 dBm with a low power consumption of 12 and 9.6 mW, respectively. The measured phase noise degradation is around 9.5 and 6 dB, which is close to the theoretical value.
This paper presents the design and characterization of an efficient high-output-power 55 GHz fundamental oscillator. The performance parameters of the oscillator are analysed as a function of the contributors of the tank capacitance, and the design choices in the varactor for phase noise and for tuning range are exemplified. The circuit was implemented in 22 nm FD-SOI CMOS technology and occupies 0.046 mm2 area including the matching network. On-wafer measurement results have demonstrated 6.5 dBm peak output power, 22% peak DC-to-RF efficiency and −98.3 dBc/Hz phase noise at 1 MHz offset frequency, while the core draws 8.3 mW power. To the best knowledge of the authors, the efficiency is the best, while the output power is the second best among CMOS oscillators in the same frequency range, and the phase noise is the best result for V-band fundamental CMOS oscillators reported to date.
A transformer-based magnetic tuning technique with both coarse and fine frequency tuning is proposed to enhance the frequency tuning range (FTR) and phase noise performance of
$W$
-band oscillators. Compared with our previous related works, a more detailed and thorough analysis of the magnetic tuning technique, especially the design and optimization of the proposed multicoil transformer with coarse- and fine-tuning switches, is included. Two prototypes are designed and evaluated in a 65-nm CMOS process. A proposed
$W$
-band varactor-less dual-band voltage-controlled oscillator (DB-VCO) prototype achieves an FTR of 14.3% from 95.7 to 110.5 GHz with a phase noise of −106.9 dBc/Hz at 10-MHz offset and consumes 6.2-mW power, corresponding to an FoM
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of −181.7 dBc/Hz. Another proposed
$W$
-band transformer-coupled quadrature VCO (TC-QVCO) prototype achieves an FTR of 11.9% from 88.8 to 100 GHz with a phase noise of −110.5 dBc/Hz at 10-MHz offset and consumes 14.5-mW power, corresponding to an FoM
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of −179.7 dBc/Hz. The proposed DB-VCO and TC-QVCO occupy small core areas of 0.02 and 0.022 mm
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, respectively.
A 2.8 – 4.6 GHz wideband multi-core VCO with a fast start-up scheme is presented in this brief. The proposed multi-core VCO uses a successive approximation register based auto frequency control (SAR-AFC) loop with the embedded 2/3 Judge to ensure the desired output frequency. To benefit a wider application, the VCO provides radio and low frequency outputs. A prototype of the multi-core VCO is implemented in 180-nm CMOS, and consumes 20 mA from a 3.3-V supply voltage with an active area of 4.8 mm
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. Measured results indicate that the multi-core LC VCO is capable of providing the phase noise of −120 dBc/Hz at 1-MHz offset from 4.6 GHz frequency. One of the attractive merits from the proposed LC VCO is that the response time could be saved 45% over the traditional VCO architecture.
A cascaded mode-switching sub-sampling PLL with quadrature dual-mode voltage waveform-shaping oscillator is proposed in this paper. The dual-mode voltage waveform-shaping oscillator is introduced to extend the tuning range and improve phase noise performance at mm-wave frequency, simultaneously. Meanwhile, the dual-mode quadrature topology is investigated to reduce the phase noise and quadrature phase error, compared to conventional quadrature oscillator. Then, the proposed oscillator is applied in a cascaded PLL with divider-less mode-switching sub-sampling loop, which can obtain the merits of high frequency-resolution, low loop noise, and wide frequency locking range. Both the dual-mode voltage waveform-shaping oscillator and the cascaded PLL are verified and fabricated in a 28-nm CMOS process. The FoM and FoMT of the oscillator at 10 MHz offset are -188.2 dBc/Hz and -200.7 dBc/Hz respectively. The proposed PLL prototype exhibits a frequency range from 22.8 to 33.9 GHz with a typical power consumption of 41.7 mW. The phase noise across the frequency band is from -104.1 to -108.2 dBc/Hz at 1 MHz offset. The jitter FoMj is -236.2 dB.
An ultrawideband millimeter-wave (mm-Wave) and subterahertz (sub-THz) signal generator is proposed leveraging a varactor-less quad-band voltage-controlled oscillator (QB-VCO), a dual-mode injection-locked frequency divider (DM-ILFD), a power-efficient injection-locked oscillator (ILO) as a driver, and self-mixing-based frequency multipliers for frequency extension. A switched-quadruple-coil transformer is proposed to vary the inductances of the resonant coils in the transformer tank to improve the frequency tuning range of the varactor-less QB-VCO. Besides, a locking-range-enhancement technique is proposed for the DM-ILFD. Implemented in a 65-nm CMOS process, the proposed mm-Wave and sub-THz signal generator achieves a record frequency tuning range from 58.8 to 275.6 GHz with 10-MHz offset phase noise from -115.8 to -89.2 dBc/Hz, while consuming 54 mW and occupying a core area of 0.65 mm
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, corresponding to a FoM
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of -190.4 dBc/Hz.
A wide tuning range, low phase noise oscillator with 3 stage differential configuration is presented. GPDK 45 nm CMOS Technology is selected for the design and simulation of the proposed circuit, under power supply impediment of 1.1 V. Proposed delay cell features ultra wide tuning range as it utilizes dual control voltages (Vc1 and Vc2), enabling large current to flow in the circuit. As frequency of oscillation has linear proportionality with the bias current, this oscillator generates frequencies from 534 MHz to 18.56 GHz. The proposed circuit occupies chip area of 102.87μ m2. This circuit offers power consumption of 1.13 mWatt and phase noise of −108.61dBc/Hz (10 MHz offset frequency) at 5.82 GHz oscillation frequency. Performance of the proposed circuit is evaluated on various temperature, supply voltage and process corners. Total Harmonic Distortion (THD) profile is also measured through simulation. Because of wide frequency spectrum, low phase noise, small area and low power budget, proposed circuit can be utilized in various power electronic applications, medical equipments, communication and navigation systems.
This paper proposes a mm-wave frequency generation technique that improves its phase noise (PN) performance and power efficiency. The main idea is that a fundamental 20 GHz signal and its sufficiently strong third harmonic at 60 GHz are generated simultaneously in a single oscillator. The desired 60 GHz local oscillator (LO) signal is delivered to the output, whereas the 20 GHz signal can be fed back for phase detection in a phase-locked loop. Third-harmonic boosting and extraction techniques are proposed and applied to the frequency generator. A prototype of the proposed frequency generator is implemented in digital 40 nm CMOS. It exhibits a PN of -100\;\text{dBc/Hz} at 1 MHz offset from 57.8 GHz and provides 25% frequency tuning range (TR). The achieved figure-of-merit (FoM) is between 179 and 182 dBc/Hz.
A quadrature LC-VCO incorporating passive coupling and broadband harmonic combining for frequency multiplication by 4, and NMOS switched variable inductors is fabricated in 65 nm bulk CMOS to generate signals at 85 to 127 GHz. The passive quadrature coupling bypasses the need for a broadband on-chip bias-T, while reducing power consumption, phase noise, and the theoretical conversion loss for the 4th order harmonic generation by 3 dB over the linear superposition. The 39% frequency tuning range is at least 4x higher than the other CMOS implementations with center frequency over 90 GHz. At power consumption of 30–45 mW from a 1.5 V power supply, the measured output power varies from ${-}$ 15 to ${-}$23 dBm and phase noise at 10 MHz offset varies from ${-}$ 108 to ${-}$102 dBc/Hz over the output frequency range. These are sufficient for use in millimeter wave rotational spectroscopy.
This work presents a millimeter-wave (mm-wave) dual-mode voltage-controlled oscillator (VCO) topology with switchable coupled VCO-cores for wide frequency tuning range and low phase noise application. By taking advantage of the different parasitic capacitance of cross-coupled pair when the VCO-core operates in ON and OFF states, the dual-mode operation of VCO can be realized, and the oscillations for both modes can be excited at the lower resonant frequency of tank, such that tank Q and phase noise performance could be improved for both modes. Strongly coupled transformer with large coupling coefficient (k) is utilized to increase the oscillation stability at the desired resonant frequency for both modes. The large k transformer will also facilitate the enhancement of tank Q at the lower resonant frequency. Frequency tuning range of the VCO is increased by properly designing the VCO-cores and combining the frequency bands of the two modes. In addition, the cross-coupled pair of VCO-core at OFF state is able to act as high Q active capacitor, which can further increase the tank Q and thus reduce the phase noise. Fabricated in a 0.18 μm BiCMOS process, the VCO exhibits a wide tuning range of 17.2% from 55.7 GHz to 66 GHz, and low phase noise from -87.5 dBc/Hz to -93.5 dBc/Hz at 1 MHz offset over the entire tuning range.
A dual-mode LC-tank based VCO for mm-wave applications is described. The design employs reconfiguration of the active negative resistance core around the LC tank, in order to provide two oscillation modes. The frequency spacing of the two modes is determined by an inductor ratio. The design is implemented in a 65nm CMOS process, with measured tuning ranges of 56.9 GHz to 65.4 GHz, and 64.6 GHz to 75.3 GHz in the two modes respectively, for a net tuning range of 28%. The oscillator consumes 13 mW from a 1 V supply. The minimum switch size that is required to ensure mode switching is analyzed.
To provide wide frequency tuning range (FTR) with compact implementation area, a new inductive tuning method is introduced in this paper for CMOS 60 GHz voltage controlled oscillator (VCO). The inductive tuning is based on a switching inductor-loaded transformer by configuring different current return-paths in the secondary coil of the transformer. Different from previous inductive tuning methods, the proposed VCO topology can achieve wide FTR for multiple sub-bands at 60 GHz within compact area by only one transformer. Two 60 GHz VCOs are demonstrated in 65 nm CMOS with design targets for the maximum FTR and the balanced phase noise in each sub-band, respectively. As measured by experiments, the first VCO (asymmetric) achieves a wide FTR of 25.8% from 51.9 to 67.3 GHz with phase noise variation of $pm$8.2 dB ($-$90.2 to $-$106.7 dBc/Hz at 10 MHz offset) in all sub-bands; and the second VCO (symmetric) realizes a low phase noise variation of $pm$ 2.5 dB ($-$ 105.9 to $-$ 110.8 dBc/Hz at 10 MHz offset) in all sub-bands with a FTR of 14.2% from 57.0 GHz to 65.5 GHz.
This paper presents a novel inductive tuning method for 60GHz voltage controlled oscillator (VCO) design. A new inductor-loaded transformer is proposed by configuring different current return-paths in the secondary coil of a transformer. Different from published inductive tuning methods, the proposed topology can achieve a multi-band, wide tuning range within compact area using only one transformer. A 60GHz VCO is implemented at 65nm CMOS process for demonstration. The obtained oscillation frequency can vary from 51.9GHz to 67.3GHz, which covers the full 60GHz band and provides a wide frequency tuning range of 25.8%.
A novel inductor switching technique is used to design and implement a wideband LC voltage controlled oscillator (VCO) in 0.13 mum CMOS. The VCO has a tuning range of 87.2% between 3.3 and 8.4 GHz with phase noise ranging from -122 to -117.2 dBc/Hz at 1 MHz offset. The power varies between 6.5 and 15.4 mW over the tuning range. This results in a power-frequency-tuning normalized figure of merit (PFTN) between 6.6 and 10.2 dB which is one of the best reported to date.
This paper presents a multi-band CMOS VCO using a double-tuned, current-driven transformer load. The dual frequency range oscillator is based on enabling/disabling the driving current in the secondary port of the transformer. This approach eliminates the effect of switches connected directly to the VCO tank whose capacitance and on-resistance affect both the tuning range and the phase noise of a typical multi-band oscillator. The relation between the coupling coefficient of the transformer load, selection of frequency bands, and the resulting quality factor at each band is investigated. The concept is validated through measurement results from a prototype fabricated in 0.25 ¿m CMOS technology. The VCO has a measured tuning range of 1.94 to 2.55 GHz for the low frequency range and 3.6 to 4.77 GHz for the high frequency range. It draws a current of 1 mA from 1.8 V supply with a measured phase noise of -116 dBc/Hz at 1 MHz offset from a 2.55 GHz carrier. For the high frequency band, the VCO draws 10.1 mA from the same supply with a phase noise of -122.8 dBc/Hz at 1 MHz offset from a 4.77 GHz carrier.
A fully integrated 0.024 mm<sup>2</sup> differentially tuned 6-GHz LC-VCO for 6+Gb/s high-speed serial (HSS) links in 90-nm bulk CMOS is presented. It is smaller than any LC-VCO reported to date at this frequency. Its size is comparable with ring oscillators but it has significantly better phase noise. A circuit technique is introduced to dynamically set the common-mode (CM) voltage of the differential varactor control signals equal to the VCO's CM. Compared to other commonly used techniques such as replica biasing, this technique does not dissipate any extra power and it accurately tracks the output common-mode voltage of the VCO during the oscillations. Using a differential control a very wide tuning range from 4.5 GHz to 7.1 GHz (45%) is achieved. The VCO has a measured phase noise of -117.7 dBc/Hz at a 3-MHz offset from a 5.63-GHz carrier while dissipating 14 mW from a 1.6-V supply.
An exponentially scaling C-2C switched-capacitor (SC) ladder is proposed for millimeter-wave digitally controlled oscillators (DCOs) to achieve high-frequency resolution with small chip area. The 65-nm-CMOS DCO prototype measures a frequency resolution of 4 Hz over a frequency range of 14.2%, from 54.79 to 63.16 GHz, with a phase noise at 1-MHz frequency offset of -90.7 to -94.1 dBc/Hz while consuming 18 mW, corresponding to an FOMT from -176.6 to -180 dB. The DCO occupies a core area of 0.10 mm², with only 0.012 mm² for the C-2C SC ladder.
Several transformer-based techniques are proposed to enhance the frequency tuning range of mm-wave voltage-controlled oscillators (VCOs) and the frequency locking range of injection-locked frequency dividers (ILFDs). Firstly, a switched-transformer VCO (ST-VCO) based on dual-band topology is proposed to increase the frequency tuning range. Secondly, transformer-distribution ILFDs (TD-ILFDs) are demonstrated to achieve much improved frequency locking range with compact chip area and low power consumption. Thirdly, the injection-saturation problem of ILFDs is identified, analyzed, and solved in this work. A VCO and three different TD-ILFDs are designed and fabricated in a 65 nm CMOS process. The proposed ST-VCO measures wide tuning range of 22.3% from 62.1 GHz to 78.3 GHz with phase noise of −112 dBc/Hz at 10 MHz offset while consuming 7.7 mW, corresponding to FoM and FoMT of −180.4 dBc/Hz and −187.4 dBc/Hz, respectively. The proposed 60-GHz TD-ILFDs measure locking range of 19.6 GHz (29.6%), 19.8 GHz (29.2%), and 3.8 GHz (6.1%) while consuming 1.44 mW, 1.44 mW, and 0.44 mW.
This paper presents an E-band quadrature voltage-controlled oscillator implemented in 28-nm CMOS. Two fundamental oscillators are coupled by means of gate-to-drain transformers to realize accurate quadrature phases and switched coupled inductors are added for tuning extension. Closed-form expressions of the oscillation frequency and the tuning extension design parameters are derived. The time-variant nature of the circuit noise to phase noise (PN) of the presented topology is investigated, resulting in simple design guidelines for optimal design. Based on the proposed techniques, the realized prototype is tunable over two bands of almost 5 GHz each separated in frequency, while occupying only 0.031 mm2. The peak measured PN at 10-MHz offset is −117.7 dBc/Hz from a 72.7-GHz carrier and −110 dBc/Hz from a 88.2-GHz carrier and varies less than 3.5 dB within each band.
A wide tuning range millimeter-wave voltage-controlled oscillator (VCO) based on a magnetically coupled π-type LC network in 65-nm CMOS is proposed. By configuring the switched negative-resistance unit, the VCO can oscillate at the even mode or the odd mode of the magnetically coupled π-type LC network, thus the tuning range is widened without introducing the switch loss into the resonator. The proposed VCO achieves a measured continuous tuning range of 39%, from 47.6 to 71.0 GHz. The measured phase noise for a 47.6-GHz carrier at the even mode and 56.2-GHz carrier at the odd mode are -110.3 and -107.3 dBc/Hz at 10-MHz offset with a corresponding FOMT of -185.5 and -183.9 dBc/Hz, respectively. The measured phase noise in the whole frequency tuning range varies from -101.7 to -113.4 dBc/Hz at 10-MHz offset, while the corresponding figure-of-merit (FOM) and FOMT vary from -167.8 to -179.0 dB and -179.6 to 190.6 dB, respectively. The VCO core consumes 8.9-10.4-mA current from 1.0-V power supply and 320 × 230 μm 2 die area.
A switched resonator concept which allows better trade-off between phase noise and power consumption is demonstrated using a dual-band VCO. The dual-band VCO operates near 900 MHz and 1.8 GHz with phase noise of -125 and -123 dBc/Hz at a 600-KHz offset and 16-mW power consumption. Compared to a single band 1.8GHz VCO, the dual-band VCO has almost the same phase noise and power consumption.
This paper presents the design of a 60-GHz low-noise amplifier (LNA) in a 28-nm low-power (LP) bulk CMOS process. As the technology is optimized for digital LP applications, the design of millimeter-wave (mm-wave) circuits requires high-frequency design and modeling of all active and passive devices. This includes the development of a suitable RF-transistor layout, as well as transmission lines and high- capacitors. The mm-wave circuit design aspects are further discussed with considerations about possible dc-distribution approaches, broadband matching networks, and optimum transistor loads. The proposed approach and device models have been validated with the fabrication and characterization of a two-stage 60-GHz LNA. This circuit exhibits 13.8 dB of power gain, 18 GHz of bandwidth, 4 dB of minimum noise figure, and an input referred 1-dB compression point at 12.5 dBm consuming 24 mW of dc power. Based on this performance and to the authors’ best knowledge, the presented amplifier shows the highest reported value for a commonly used figure-of-merit of 60-GHz LNAs.
In this paper, we propose a standing-wave push–push voltage-controlled oscillator (VCO) using a transmission-line (TL) resonator that covers a frequency range of 151–174 GHz. By properly distributing negative cells in the TL resonator, a wide frequency tuning range with low phase noise can be obtained. The electrical length of the TL resonator is determined to achieve a high second-harmonic output power. The fabricated VCO demonstrates a phase noise of 91.3 dBc/Hz at 1-MHz offset at a push–push output frequency of 151.1 GHz (the estimated result) and a tuning range of 14% with a dc power consumption of 33 mW at a 1-V supply voltage. The push–push output power ranges from 14.5 to 16 dBm. The figure-of-merit including the tuning range is 182.6 dBc/Hz.
To demonstrate high tuning range and large output power, we propose a loop of coupled oscillators in this work. Two different tuning mechanisms are simultaneously exploited. First, each core oscillator is tuned using a variable capacitor. Next, by controlling the phase/delay between the coupled oscillators, the entire loop dynamics, and hence, its frequency is tuned. In this paper, we analyze a loop of “n” coupled oscillators using Adler's equation and derive the expression for the maximum tuning range. Perturbation analysis is used to study the stability conditions of the loop of coupled system. The analysis is extended toward a nested loop of coupled oscillators. The activity condition from two-port theory is used to squeeze maximum power out of active devices. The proposed system is designed and implemented using four coupled Colpitts voltage-controlled oscillators (VCOs) in a 65-nm bulk CMOS process. The VCO achieves continuous tuning range of 9.5% at the center frequency of 105 GHz with the peak output power of 2.8 mW. The circuit consumes 54 mW from a 1.2-V supply. To the best of our knowledge, this VCO has the highest output power and tuning range among all the CMOS oscillators at or above 100 GHz.
A wideband inductance–capacitance voltage-controlled oscillator (VCO) with a $g_{m}$-switching technique was designed and fabricated in the 65-nm CMOS process. With a switchable secondary gate-biased active core and a primary core, the VCO operates in two different modes. In the LF mode, in which switches turn on the secondary core, the increased start-up gain facilitates LF oscillation. In the HF mode, in which the switches isolate the secondary core from the primary core, the reduced capacitive loading allows for HF oscillation. In addition, since the gate bias of the secondary core transistors guarantees the high transconductance of the secondary core, the switch size can be minimized, which further extends the upper boundary of the oscillation frequency. The VCO achieved a 41 $%$ frequency range, i.e., 3.36–5.1 GHz, and a phase noise of $-$123.1 dBc/Hz at an offset of 1 MHz from an output frequency of 4.21 GHz. The active silicon area was 0.24 $hbox {mm}^{2}$, and the power consumption was 8.7 mW at 5 GHz.
Signal processing in ultra-wide bandwidths is one of the key challenges in the design of multi-Gb/s wireless transceivers at mm-Waves, where channels covering 57GHz to 66GHz are specified. Further considering spreads due to process variations and the stringent reference phase noise to ensure signal integrity calls for an ultra-wide tuning range and low-noise on-chip oscillator. Meeting this target is even more challenging when adopting an ultra-scaled CMOS technology node where key passive components suffer from a reduced quality factor (Q) [1]. In a 32nm node the thickness of metals closer to the substrate is half that in a 65nm process leading, for example, to MOM capacitors with roughly half Q. The penalty is only marginally compensated by the higher transistor ft, improved only by ~20%. Various techniques exploiting alternative tuning implementations have been published recently. Magnetic tuning methods where the equivalent tank inductance is varied through reflection of the secondary coil impedance of a transformer demonstrate outstanding tuning ranges but at the cost of a severe trade-off with tank Q and poor noise FOMs [2,3]. A bank of capacitors switched in and out in an LC tank is the most popular tuning approach [4-6]. However the quality factor is severely degraded, when large ranges are involved. In this work, the switched-capacitor tank of the VCO shown in Fig. 20.3.1 is centered around two different resonance frequencies by splitting the inductor through the switch Msw. In particular, an up-shift is produced when the switch is off due to its parasitic capacitance. The frequency range is significantly increased without compromising tank Q leading to large tuning range and high FOM simultaneously. Prototypes of the VCO have been realized in 32nm CMOS showing the following performances: 31.6% frequency tuning range, minimum phase noise of -118dBc/Hz at 10MHz offset from 40GHz with 9.8mW power dissipation. Despite being realized in a- ultra-scaled 32nm standard digital CMOS process without RF thick metal options, the oscillator shows state-of-the-art performances.
The performance characteristics of transmission lines, silicon integrated waveguides, tunable LC resonators and passive combiners/splitters and baluns are described in this paper. It is shown that Q-factor for an on-chip LC tank peaks between 20 and 40 GHz in a 65 nm RF-CMOS technology; well below the bands proposed for many mm-wave applications. Simulations also predict that the Q-factor of differential CPW transmission lines on-chip can exceed 20 at 60 GHz in RF-CMOS when a floating shield is applied, outperforming unshielded variants employing more advanced metal stacks. A PA circuit demonstrator for advanced on-chip passive power combiners, splitters and baluns realizes peak-PAE of 18% and Psat better than 20 dBm into a 50 Ω load at 62 GHz. An outlook to the enablement of digitally intensive mm-wave ICs and low-loss passive interconnections (0.15 dB/mm measured loss at 100 GHz) concludes the paper.
This paper presents a 60 GHz, 16% tuning range VCO, and a 40 GHz, 18 bits, 14% tuning range DCO incorporating variable inductor (VID) techniques. The variable inductor, consisting of a transformer and a variable resistor, is tunable by adjusting its resistor. By employing the proposed frequency tuning scheme, wide-tuning range as well as multi-band operation are achieved without sacrificing their operating frequencies. To verify the operation principles, the VCO and DCO are both fabricated in 90 nm CMOS technology. The tuning range of VCO is from 52.2 GHz to 61.3 GHz. The measured phase noise from a 61.3-GHz carrier is about - 118.75 dBc/Hz at 10-MHz offset, and the output power is -6.6 dBm. It dissipates 8.7 mW from a 0.7-V supply, and the chip size is 0.28×0.36mm2. On the other hand, the DCO is capable of covering frequency range from 37.6 GHz to 43.4 GHz. The measured phase noise from a 43 GHz carrier is about -109 dBc/Hz at 10-MHz offset, and the output power is -11 dBm. The DCO core dissipates 19 mW from a 1.2-V supply. Chip size is 0.5×0.15mm2.
This paper presents a magnetically tuned (MT) multimode VCO featuring an ultrawide frequency tuning range. A switched-triple-shielded transformer is proposed to change the magnetic coupling coefficient between the primary and secondary coils in the transformer tank to greatly increase the frequency tuning range of the dual-band VCO to cover the whole E-band continuously. Fabricated in a 65-nm CMOS process, the MT-VCO measures a frequency tuning range of 41.1% from 57.5 to 90.1 GHz while consuming 7 to 9 mA at 1.2-V supply with chip area of 0.03 mm2. The measured phase noises at 10-MHz offset from carrier frequencies of 58, 72.2, 80.5, and 90.1 GHz, are -107.4, -111.8, -107.8, and -105.1 dBc/Hz, respectively, which correspond to FOMT between -184.2 and -192.2 dBc/Hz.
Two new millimeter-wave digitally controlled oscillators (DCOs) that achieve a tuning range >10% and fine frequency resolution 1 MHz simultaneously are described. Switched metal capacitors distributed across a passive resonator tune the oscillation frequency. To obtain sub-MHz frequency resolution, tuning step attenuation techniques exploiting an inductor and a transformer are proposed. Two 60-GHz implementations, a fine-resolution inductor-based DCO (L-DCO) and a transformer-coupled DCO (T-DCO), are demonstrated in 90-nm CMOS. The phase noise of both DCOs is lower than -90.5 dBc/Hz at 1-MHz offset across 56-62 GHz. The T-DCO achieves a fine frequency tuning step of 2.5 MHz, whereas the L-DCO tuning step is over one order of magnitude finer at 160 kHz. The L-DCO and T-DCO consume 10 and 12 mA, respectively, from a 1.2-V supply. The size of each DCO core is 0.4 ×0.4 mm2.
A wide band CMOS LC-tank voltage controlled oscillator (VCO) with small VCO gain ( KVCO ) variation was developed. For small KVCO variation, serial capacitor bank was added to the LC-tank with parallel capacitor array. Implemented in a 0.18 mum CMOS RF technology, the proposed VCO can be tuned from 4.39 GHz to 5.26 GHz with the VCO gain variation less than 9.56%. While consuming 3.5 mA from a 1.8 V supply, the VCO has -113.65 dBc/Hz phase noise at 1 MHz offset from the carrier.
Coupled inductors can create multiple resonant frequencies in a compact high-order resonator. Together with proper nonlinear active circuitry, such a high-order resonator realizes a multi-mode oscillator covering a wide frequency range. Compared with conventional switched-resonator-based approaches that consume the same chip area, the proposed coupled-inductor-based resonator results in larger quality-factor, and hence, lower oscillator phase noise. In the proposed multi-mode oscillator that uses the multi-port coupled inductors, mode switching is achieved using independent active cores without using lossy switches in the resonator path. The behavior of the multi-mode resonator as a multi-port network in an oscillator, design trade-offs, and switching transient response of the multi-mode oscillator have been studied analytically. As a proof of concept, an integrated voltage-controlled oscillator (VCO) with a 1.28-6.06 GHz tuning range is designed and fabricated in a 0.13 mum CMOS technology. The triple-mode VCO uses a sixth-order resonator based on three coupled inductors with a compact common-centric layout. Depending on the oscillation frequency, the VCO current consumption is automatically adjusted from 2.9 to 6.1 mA to achieve a low phase noise throughout the frequency range. The measured phase noises at 1 MHz offset from carrier frequencies of 1.76, 2.26, 3.3, 4.5, and 5.6 GHz are -119.3 , -120.15 , -118.1 , -117 , and -113.5 dBc/Hz , respectively. The chip area, including the pads, is 1 mm times 1 mm and the supply voltage is 1.5 V.
A novel resonant circuit consisting of transformer-based variable inductors and MOS varactors is proposed to implement an ultra-wideband voltage-controlled-oscillator (VCO). The VCO is designed and fabricated using 0.13 mum CMOS, and fully evaluated on wafer. The VCO IC exhibits a frequency tuning range as high as 92.6 % spanning from 1.2 GHz to 3.27 GHz. The measured phase noise of -120 dBc/Hz at 1 MHz offset from the 3.1 GHz carrier is obtained.
A completely integrated PLL is realized in 45 nm digital CMOS, using two techniques to enable the coverage of the 57-to-66 GHz band. First, the targeted band of 9 GHz (plus margin for process variations) is divided in two parts, each part being covered by a separate oscillator. This relaxes the tunability requirements for each oscillator. To enable direct conversion, the PLL uses quadrature VCOs (QVCOs) having quadrature signals at the output. The outputs of both QVCOs are buffered and multiplexed by a frequency selector. Next, the wideband frequency divider chain is realized with an injection-locked divide-by-4 prescaler, followed by a divide-by-2 prescaler and an integer-N frequency divider. A frequency counter at the output of the divider is read via a shift register and used to calibrate the PLL. A phase-frequency detector (PFD), a charge pump (CP) and a 3rd-order active loop filter complete this 4th-order type-ll PLL.
A novel variable inductor using a bridge circuit is proposed. Because of a bypass switch MOSFET placed at a balance point, the effect of the switch resistance which is a penalty of the variable inductance is suppressed and degradation of the Q factor is mitigated. A 10-20 GHz tunable LC-VCO core using this inductor was also fabricated. Because of the multi-stage variable inductor, 20 GHz operation having over 10 GHz continuous tuning range with phase noise of -103 to -84 dBc/Hz is achieved with only 5.2 to 7.1 mW power consumption. By using a 1/2 divider, a 5-20 GHz continuous tuning range is also obtained. The chip area is 1/10 smaller than that of conventional wide range LC-VCOs because of the miniature 3-D structure variable inductor. This variable inductor and the wide range LC-VCO are suit able for the clock generation of high-speed communication systems, multi-core processors, as well as low-power, low-cost wireless transceivers.
This work presents complete analysis of both one- port and two-port dual-band oscillators using transformer-based fourth-order LC tanks, from which critical parameters including oscillation frequency, start-up condition, tank Q, phase noise—are thoroughly derived and compared. It is shown that one-port oscillators consume less power than two-port counterparts but may suffer from stability problem which can be solved by a notch-peak cancellation technique. On the other hand, compared to one-port oscillators, two-port oscillators need to consume more power to obtain the same output swing, but their phase noise can be improved more linearly with increasing bias current, and thus they can achieve lower phase noise with a sufficiently large bias current. Based on the results, a dual-band quadrature voltage- controlled oscillator (Q-VCO) is systematically designed and implemented in a 0.13- $\mu$m CMOS process for software-defined -radio (SDR) applications, in which the two-port topology is used in the low band for low phase noise and the one-port topology is employed in the high band for low power consumption. The prototype achieves a dual-band operation with in-phase and quadrature-phase (IQ) output signals from 2.7 GHz to 4.3 GHz and from 8.4 GHz to 12.4 GHz. At 3.6 GHz and 10.4 GHz, phase noise at 3 MHz offset of ${-}135.9$ dBc/Hz and ${-}119$ dBc/Hz and sideband-rejection ratios (SBR) of 37 dB and 41 dB are measured, respectively.
A switched resonator concept which allows better trade-off between
phase noise and power consumption is demonstrated using a dual band VCO.
The dual-band VCO operates near 900 MHz and 1.8 GHz with phase noise of
-125 and 123 dBc/Hz at a 600-KHz offset and 16-mW power consumption.
Compared to a single band 1.8 GHz VCO, the dual-band VCO has almost the
same phase noise and power consumption
In this brief, we propose to use a transformer-based resonator to build a dual-mode oscillator, e.g., a system capable of oscillating at two different frequencies without recurring to switched inductors, switched capacitors, or varactors. The behavior of the resonator configured as a one-port and a two-port network is studied analytically, and the dependence of the quality factor on the design parameters is thoroughly explored. These results, combined with the use of traditional frequency tuning techniques, are applied to the design of a wide-band voltage-controlled oscillator (VCO) that covers the frequency range 3.6-7.8 GHz. The performance of the designed VCO, implemented in a digital 0.13-mum CMOS technology, has been studied by transistor-level and 2.5D electromagnetic simulation (Agilent Momentum). A typical phase noise performance at 1-MHz offset of -104 dBc/Hz has been predicted, while the power consumption ranges from 1 to 8 mW, depending on the VCO configuration
A switched resonator concept, which can be used to reduce the size of multiple-band RF systems and which allows better tradeoff between phase noise and power consumption, is demonstrated using a dual-band voltage-controlled oscillator (VCO) in a 0.18-μm CMOS process. To maximize Q of the switched resonator when the switch is on, the mutual inductance between the inductors should be kept low and the switch transistor size should be optimized. The Q factor of switched resonators is ∼30% lower than that of a standalone inductor. The dual-band VCO operates near 900 MHz and 1.8 GHz with phase noise of -125 and -123dBc/Hz at a 600-kHz offset and 16-mW power consumption. Compared to a single-band 1.8-GHz VCO, the dual-band VCO has almost the same phase noise and power consumption, while occupying ∼37% smaller area.
Two designs of voltage-controlled oscillators (VCOs) with mutually coupled and switched inductors are presented in this paper to demonstrate that the tuning range of an LC VCO can be improved with only a small increase in phase noise and die area in a standard digital CMOS process. Particular attention is given to the layout of the inductors to maintain Q across the tuning range. In addition, different capacitive coarse-tuning methods are compared based on simulated and measured data obtained from test structures. Implemented in a 90 nm digital CMOS process, a VCO with two extra coupled inductors achieves a 61.9% tuning range with an 11.75 GHz center frequency while dissipating 7.7 mW from a 1.2 V supply. This VCO has a measured phase noise of -106 dBc/Hz at 1 MHz offset from the center frequency resulting in a higher figure-of-merit than other recently published VCOs with similar operating frequencies. In addition, the area overhead is only 30% compared to a conventional LC VCO with a single inductor.
As the tuning range of integrated LC-VCOs increases, it becomes difficult to co-design the active negative resistance core and the varactor size optimally for the complete frequency range. The presented VCO design solves this by adjusting the size of the negative resistance transistors with a switched active core, with the additional benefit that this reduces parasitics and hence allows to achieve better phase noise and an even higher tuning range. Also the VCO gain variations are counteracted by employing an analog varactor that can change in size. The implementation in 0.13-mum CMOS shows a tuning range from 3.1 to 5.2 GHz, with a power consumption varying accordingly from 7.7 to 2.1 mA from a 1.2 V supply. The measured phase noise is -118 dBc/Hz at 1 MHz from a 4-GHz carrier.
The unlicensed band around 60 GHz can be utilized for wireless communications at data rates of several gigabits per second. This paper describes a receiver front-end that incorporates a folded microstrip geometry to create resonance at 60 GHz in a common-gate LNA and active mixers. Realized in 0.13-μm CMOS technology, the receiver front-end provides a voltage gain of 28 dB with a noise figure of 12.5 dB while consuming 9 mW from a 1.2-V supply.
A low voltage multiband all-pMOS VCO was fabricated in a 0.18-μm CMOS process. By using a combination of inductor and capacitor switching, four band (2.4, 2.5, 4.7, and 5 GHz) operation was realized using a single VCO. The VCO with an 1-V power supply has phase noises at 1-MHz offset from a 4.7-GHz carrier of -126 dBc/Hz and -134 dBc/Hz from a 2.4-GHz carrier. The VCO consumes 4.6 mW at 2.4 and 2.5 GHz, and 6 mW at 4.7 and 5 GHz, respectively. At 4.7 GHz, the VCO also achieves -80 dBc/Hz phase noise at 10-kHz offset with 2 mW power consumption.
A 1.8-GHz LC VCO designed in a 0.18-μm CMOS process achieves a very wide tuning range of 73% and measured phase noise of -123.5 dBc/Hz at a 600-kHz offset from a 1.8-GHz carrier while drawing 3.2 mA from a 1.5-V supply. The impacts of wideband operation on start-up constraints and phase noise are discussed. Tuning range is analyzed in terms of fundamental dimensionless design parameters yielding useful design equations. An amplitude calibration technique is used to stabilize performance across the wide band of operation. This amplitude control scheme not only consumes negligible power and area without degrading the phase noise, but also proves to be instrumental in sustaining the VCO performance in the upper end of the frequency range.