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A Comparative Analysis of Different 32-bit Adder Topologies with Multiplexer Based Full Adder

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Saravanakumar Natarajan at Bannari Amman Institute of Technology
Saravanakumar Natarajan
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Adders form an almost imperative component of every contemporary integrated circuit. Due to the rapidly growing mobile industry not only the speed arithmetic unit but also less area and low power arithmetic units are needed. The prerequisite of the adder is that it is predominantly fast and secondarily efficient in chip area. Several types of adders are available in practice; each type is used for meticulous purpose based on their performance and features. In this paper, the multiplexer based full adder is implemented in the design of various adders and they are compared on the basis of their execution parameters such as area, delay and power distribution by using conventional full adder and multiplexer based full adder.
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International Journal of Engineering Science and Computing, May 2016 4850 http://ijesc.org/
DOI 10.4010/2016.1102
ISSN 2321 3361 © 2016 IJESC
A Comparative Analysis of Different 32-bit Adder Topologies with
Multiplexer Based Full Adder
D.Mohanapriya1, Dr.N.Saravanakumar2
PG Scholar1, Assistant Professor2
Department of ECE
BIT, Erode, Tamil Nadu, India
d.mohanapriya92@gmail.com1
Abstract:
Adders form an almost imperative component of every contemporary integrated circuit. Due to the rapidly growing mobile
industry not only the speed arithmetic unit but also less area and low power arithmetic units are needed. The prerequisite of the
adder is that it is predominantly fast and secondarily efficient in chip area. Several types of adders are available in practice; each
type is used for meticulous purpose based on their performance and features. In this paper, the multiplexer based full adder is
implemented in the design of various adders and they are compared on the basis of their execution parameters such as area, delay
and power distribution by using conventional full adder and multiplexer based full adder.
Keywords: Multiplexer based FA, Carry Bypass Adder, Carry Increment Adder, Carry Save Adder, Carry Select Adder, Carry
Skip Adder, Ripple Carry Adder.
I. INTRODUCTION
Arithmetic unit are the crucial blocks of digital systems such
as Digital Signal Processor (DSP), micro processors,
microcontrollers, and further data processing units. Adders
become a critical hardware unit for the efficient
implementation of arithmetic unit. In plentiful arithmetic
applications and other sort of applications, adders are not
only in the arithmetic logic unit, but also in other segment of
processor. Addition operation can also be used in
complement operations, encoding, decoding and so on. In
prevalent, addition is a process which involves two numbers
which are added and carry will be propagated. The addition
operations will result in sum value and carry value. All
complex adder architectures are constituted from its basic
building blocks such as Half Adder (HA) and Full Adder
(FA). In this paper, the multiplexer is used for propagate the
carry segment in the full adder and that proposed FA is
implemented in different types of adders.
II. ADDERS
The conventional and proposed full adder are figured in
Figure 1 and 2. In conventional adder the cary is propagated
by using three AND gate and one OR gate. In Figure 2
shows that the proposed Multiplexer based full adder where
the carry is propagated by using one 2:1 Multiplexer. The
design and of various adders such as Ripple Carry Adder
(RCA), Carry Increment Adder (CIA), Carry Save Adder
(CSA ),Carry Skip Adder (CSkA), and Carry Bypass Adder
(CBA) Carry Select Adder (CSlA) are disputed. The each
and every adder is designated based on the propagation of
carry between the stages.
Figure 1: Conventional full adder
Figure 2: Multiplexe based full adder
A.Ripple Carry Adder
The ripple carry adder is constituted by cascading full
adders (FA) blocks in series. One full adder is responsible
for the addition of two binary digits at any phase of the
ripple carry. The carryout of one phase is fed directly to the
carry-in of the next phase. A number of full adders may be
added to the ripple carry adder or ripple carry adders of
different sizes may be cascaded in order to furnish binary
vector strings of larger sizes. For an n-bit parallel adder, it
desire n computational elements (FA). It is composed of
four full adders. The augends’ bits of x are added to the
Research Article Volume 6 Issue No. 5
International Journal of Engineering Science and Computing, May 2016 4851 http://ijesc.org/
addend bits of y regard fully of their binary position. Each
bit addition creates a sum and a carry out. The carry out is
then dispatched to the carry in of the next higher-order bit.
The final result creates a sum of four bits plus a carry out
(c4). The four bit RCA adder is show in Figure 3.
Figure 3: Ripple carry adder for 4bit
B. Carry Skip Adder
As the name demonstrate, Carry Skip Adder (CSkA) uses
skip logic in the propagation of carry [1]. It is designed to
speed up the addition manipulation by adding a propagation
of carry bit around a portion of entire adder. The carry-in bit
cognominated as Ci. The output of RCA (the last stage) is
Ci+4. The Carry Skip circuitry consists of two logic gates.
AND gate acquire the carry-in bit and compares it with the
group of propagated signals [2] given below. The block
diagram of carry skip adder is show in Figure 4.
Figure 4: Block Diagram Carry Skip Adder
C. Carry Increment Adder
The architecture of Carry Increment Adder (CIA) subsists of
RCA’s and incremental circuitry [1]. The incremental circuit
can be arranged using HA’s in ripple carry chain with a
sequential order. The addition operation is done by dividing
total number of bits in to faction of 4bits and addition
operation is done using several 4bit RCA’s. The block
diagram of carry increament adder is show in Figure 5.
Figure 5: Block Diagram CIA
D. Carry Save Adder
In Carry Save Adder (CSA), the carry is not propagated
through the phases. Instead, carry is stored in present phase,
and updated as addend value in the next phase [2]. Hence,
the delay due to the carry is reduced in this scheme. The 8
bit for carry save adder is shown in Figure 6.
Figure 6: Carry Save Adder for 8 Bit
E. Carry Select Adder
Carry Select Adder (CSlA) architecture subsists of
independent generation of sum and carry i.e., Cin=1 and
Cin=0 are executed parallelly [14]. Sustained by Cin, the
external multiplexers elect the carry to be propagated to next
phase. Further, based on the carry input, the sum will be
elected. Hence, the delay is diminished. However, the
structure is increased due to the multiplicity of multiplexers
[4]. The block diagram of carry select adder is show in
Figure 7.
Figure 7: Block Diagram Carry Select Adder
International Journal of Engineering Science and Computing, May 2016 4852 http://ijesc.org/
F. Carry Bypass Adder
Here, RCA is used to add 4-bits at a time and the carry
generated will be propagated to next phase with help of
multiplexer using elect input as Bypass logic. By pass logic
is formed from the product values as it is computed in the
CLA. Sustained by the carry value and by pass logic, the
carry is propagated to the next phase [1].The architecture of
CBA is given in Figure 8..
Figure 8: Block Diagram of CBA
III IMPLEMENTATION
The Schematic diagram of Carry Bypass Adder, Carry
Increment Adder, Carry Save Adder, Carry Select Adder,
Carry Skip Adder and Ripple Carry Adder by using
multiplexer based full adder for 32 bit are listed below. All
adders are synthesized by Xmanager Enterprise 3(in 180nm
technology) Cadance tool.
Figure 9: Schematic diagram of 32 bit RCA
Figure 10: Schematic diagram of 32 bit CSkA
Figure 11: Schematic diagram of 32 bit CIA
Figure 12: Schematic diagram of 32 bit CSA
Figure 13: Schematic diagram of 32 bit CBA
International Journal of Engineering Science and Computing, May 2016 4853 http://ijesc.org/
Figure 14: Schematic diagram of 32 bit CSLA
IV. COMPARISON
The pursuance of adder topologies are discussed for
robustness against area, delay and power dissipation [1].
They are elected for this work since they have been
frequently used in many applications. Addition is an
indispensable manipulation for any high speed digital signal
processing, digital system or control system. Therefore
pertinent choice of adder topologies is an requisite concerns
in the design of VLSI integrated circuits for high speed and
high performance CMOS circuits. Power distribution, area,
gate count and delay for all adder topologies discussed
earlier are observed for using both conventional and
multiplexer based full adder.
Table 1: Comparison of Area inx10-6 m
Adders
Area by using
Conventional FA
Area by using
Multiplexer
based FA
RCA
4842
2980
CSkA
6426
4563
CIA
5681
3818
CSA
5913
4284
CSLA
10756
7264
CBA
6286
4423
Table 2: Comparison of Delay in ps
Adders
Delay by
using
Conventional
FA
RCA
7854
CSkA
8646
CIA
5904
CSA
8048
CSLA
2807
CBA
8583
From the power distribution, it is observed that the
maximum power distribution occurs for carry select adder
and next comes the carry save adder. The least power
distribution results for ripple carry adder and carry
increment adder. From the area distribution and cell usage,
the carry select and carry skip adders occupies more area
and cell usage, ripple carry and carry increment occupies
less area and cell usage. From this, it can be observed that
ripple carry adder is slowest adder but occupies less area
and power among all other. And the carry select adder is
fastest adder but occupies more area and power among all
other. Table shows that area, delay, power and gate count of
different types of adder by using conventional and
multiplexer based full adder.
Table 3. Comparison of Power in nW
Adders
Power by
using
Conventional
FA
Power by
using
Multiplexer
based FA
RCA
237624
208760
CSkA
313864
285216
CIA
282604
260509
CSA
317939
299164
CSLA
460419
422133
CBA
309403
280733
Table 4. Comparison of Gate count(cells)
Adders
Gate count by
using
Conventional
FA
Gate count
by using
Multiplexer
based FA
RCA
192
96
CSkA
256
160
CIA
228
132
CSA
240
156
CSLA
396
216
CBA
244
148
V.CONCLUSION
The different types of adders such as Carry Bypass Adder,
Carry Increament Adder, Carry Save Adder, Carry Select
Adder, Carry Skip Adder and Ripple Carry Adder are
designed by using conventional and multiplexer based full
adder for 32 bit and coded in verilog. The simulation is done
by Xilinx ISE 14.2 and the synthesize is done by cadence
Xmanager Enterprise 3. Table shows that the proposed
adder topologies by multiplexer based full adder results an
efficient area, power distribution, delay and gate count than
by using conventional full adder. In future, the adders will
be implemented in FPGA Spartan 6
International Journal of Engineering Science and Computing, May 2016 4854 http://ijesc.org/
VI.REFERENCES
[1] R.Uma, Vidya Vijayan, M.Mohanapriya, Sharon Paul,
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[2] Raminder Preet Pal Singh, Praveen Kumar, Balwinder
Singh,“Performance Analysis of 32-Bit Array
Multiplier with a Carry Save Adder and with a Carry
Look Ahead Adder”, Letters of International Journal of
Recent Trends in Engineering, Vol. 2, No. 6, pp. 83-
89,Nov 2009.
[3] Sarabdeep Singh, Dilip Kumar,“Design of Area and
Power Efficient Modified Carry Select Adder”,
International Journal of Computer Applications, Vol.
33, No. 3, pp. 14-18, Nov 2011.
[4] Animul islam, M.W. Akram, S.D. pable, Mohd. Hasan,
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Technologies in Communication and Computing, 2010.
[5] Deepa Sinha, Tripti Sharma, K.G.Sharma,
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[6] Nabihah Ahmad, Rezaul Hasan,“A new Design of
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[7] Y. Sunil Gavaskar Reddy, V.V.G.S. Rajendra Prasad,
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[8] Mariano Aguirre-Hernandez and Monico Linares-
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[9] Ning Zhu, Wang Ling Goh, Weija Zhang, Kiat Seng
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[10] Sreehari Veeramachaneni, M.B. Srinivas, “New
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[11] Tripti Sharma, k.G.Sharma, Prof.B.P.Singh, Neha
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[12] G.Shyam Kishore,“A Novel Full Adder with High
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[13] Romana Yousuf, Najeeb-ud-din,“Synthesis of Carry
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2010.
... Jayanthi et al. [7] and SaiKumar et al. [21] did not restrict their research on PPA adders and further analyzed high speed VLSI adders. Mohanapriya et al. [15] investigated multiplexer-based adders using Cadence for 180nm technology. They reported the performance of the circuits in terms of speed, area, and power dissipation. ...
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