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IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. XX, NO. XX, X XXXX 1
Characterization and Modeling of
Gigarad-TID-induced Drain Leakage Current of
28-nm Bulk MOSFETs
Chun-Min Zhang, Student Member, IEEE, Farzan Jazaeri, Member, IEEE, Giulio Borghello, Federico Faccio,
Serena Mattiazzo, Andrea Baschirotto, Fellow, IEEE and Christian Enz, Senior Member, IEEE
Abstract—This paper characterizes and models the effects
of total ionizing dose (TID) up to 1 Grad(SiO2) on the drain
leakage current of nMOSFETs fabricated with a commercial
28-nm bulk CMOS process. Experimental comparisons among
individual nMOSFETs of various sizes provide insight into the
TID-induced lateral parasitic devices, which contribute the most
to the significant increase up to four orders of magnitude in the
drain leakage current. We introduce a semi-empirical physics-
based approach using only three parameters to model the parallel
parasitic and total drain leakage current as a function of TID.
Taking into account the gate independence of the drain leakage
current at high TID levels, we model the lateral parasitic device
as a gateless charge-controlled device by using the simplified
charge-based EKV MOSFET model. This approach enables us
to extract the equivalent density of trapped charges related to
the shallow trench isolation oxides. The adopted simplified EKV
MOSFET model indicates the weak inversion operation of the
lateral parasitic devices.
Index Terms—Charge-controlled, drain leakage current, gate-
less, parasitic leakage current, parasitic device, physics-based
modeling, shallow trench isolation, STI, total ionizing dose, TID,
trapped charges, 28-nm bulk MOSFETs, weak inversion
I. INTRODUCTION
T
HE forthcoming high-luminosity Large Hadron Collider
(HL-LHC) at CERN is anticipated to experience an
unprecedented radiation level up to
1 Grad
(SiO
2
) of total
ionizing dose (TID) and
1016neutrons/cm2
of hadron fluence
over ten years of operation [1]. To ensure long-term reliable
performance, the HL-LHC will require highly improved
tracking systems with higher bandwidth and more radiation-
tolerant front-end (FE) electronics [2], [3]. The aggressive
downscaling of CMOS technologies brings a higher operation
Manuscript received July 13, 2018; revised October 16 and October 20,
2018; accepted October 22, 2018. This work is part of the GigaRadMOST
project funded by the Swiss National Science Foundation (SNSF) under grant
number 200021 160185, in collaboration with the ScalTech28 project funded
by the Istituto Nazionale di Fisica Nucleare (INFN).
Chun-Min Zhang (corresponding author), Farzan Jazaeri, and Christian Enz
are with the Integrated Circuits Laboratory (ICLAB),
´
Ecole Polytechnique
F
´
ed
´
erale de Lausanne (EPFL), Neuch
ˆ
atel 2002, Switzerland (e-mail: chun-
min.zhang@epfl.ch, farzan.jazaeri@epfl.ch; christian.enz@epfl.ch).
Giulio Borghello and Federico Faccio are with the EP department of CERN,
Geneva 1211, Switzerland. Giulio Borghello is also with the DPIA, University
of Udine, Udine 33100, Italy (e-mail: giulio.borghello@cern.ch).
Serena Mattiazzo is with the Department of Information Engineering,
INFN Padova and University of Padova, Padova 35131, Italy (e-mail:
serena.mattiazzo@dei.unipd.it).
Andrea Baschirotto is with the Microelectronic Group, INFN Milano-
Bicocca and University of Milano-Bicocca, Milano 20126, Italy (e-mail:
andrea.baschirotto@unimib.it).
Drain
Source
LDD
Halo Gate oxide
p-Sub
STI
W
n
I
Dleak.par
Retrograde w ell
+++++ ++++++
+ + + + + + + + +
+ + + + + + + +
+ + + + + +
I
Dleak.par
Gate
L
n
Fig. 1. Three-dimensional schematic illustration of an irradiated
n
MOSFET
illustrating the formation of two lateral parasitic devices. The main
n
MOSFET
is surrounded by the shallow-trench isolation (STI) structure, as shown in light
green. The front face of the STI structure is represented by the light-green
frame to make the channel doping profile and the STI-related trapped-charge
distribution (+markers) visible.
Gate
L
n
Drain
Source
I
Dleak.par
Q
)
)
:
:
1
I
Dleak.par
Fig. 2. Layout of an irradiated multi-finger
n
MOSFET illustrating the scaling
property of the total parallel parasitic drain-to-source leakage current with two
times the number of fingers. The total width of the multi-finger
n
MOSFET
Wnis the width per finger WFtimes the number of fingers NF.
speed and an extended circuit functionality [4], [5]. Moreover,
the introduced ultrascaled gate oxides suppress the relevant
TID-induced charge buildup and reduce the susceptibility to
TID effects [6], [7]. However, at ultrahigh TID levels, effects on
parasitic oxides, such as shallow trench isolation (STI) oxides
and spacer oxides, often dominate the radiation response of
nanoscale CMOS technologies [8], [9]. With the perspective
of using ultrascaled CMOS technologies in future radiation-
tolerant tracking systems, we have been characterizing the
radiation tolerance of a commercial 28-nm bulk CMOS process
up to
1 Grad
(SiO
2
) of TID [10], [11] and modeling the observed
effects for supporting radiation-tolerant circuit designs [12].
Static measurements on our 28-nm bulk MOSFETs demonstrate
an improved radiation tolerance at the switched-on region,
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. XX, NO. XX, X XXXX 2
whereas most of the irradiated
n
-type MOSFETs undergo a
significant increase in the drain leakage current [10], [11]. To
characterize these effects, we have introduced the simplified
charge-based EKV MOSFET model in [12] to describe the
large- and small-signal characteristics. We are currently devel-
oping physics-based models of TID effects on bulk MOSFETs
that can ultimately be implemented into the BSIM6 compact
model for the design of radiation-tolerant circuits. Among all
the various effects of TID on bulk MOSFETs, the significant
increase of the drain leakage current observed for
n
-type
MOSFETs is certainly the most important to model. Most
of the other effects such as threshold voltage shift can be
compensated by proper circuit biasing techniques. This work
therefore focuses on modeling the TID-induced drain leakage
current by means of a gateless charge-controlled model similar
to the simplified charge-based EKV MOSFET model.
The significant increase in the drain leakage current is mainly
attributed to the radiation-induced charge trapping in relatively
thick STI oxides. For an
n
MOSFET, trapped holes in STI oxides
can invert the p-type substrate along the STI sidewalls and
open two parallel parasitic leakage paths [13]–[16]. This allows
two parallel leakage components to flow from drain to source,
even when the main
n
MOSFET is switched off, as shown in
Fig. 1. The situation becomes even worse for a multi-finger
n
MOSFET because the total parasitic drain-to-source leakage
current scales with the number of fingers [17], as shown in
Fig. 2. This radiation-induced leakage current questions the
main advantage of nanoscale CMOS technologies—i.e., low
power consumption [18]. In contrast, for a
p
MOSFET, trapped
holes in STI oxides tend to accumulate electrons at the surface
of the n-type substrate and prevent the formation of p-type
channels. Therefore, the drain leakage current of the irradiated
pMOSFETs is not an issue, as shown in [11].
This paper characterizes and models in detail the effects
of TID up to
1 Grad
(SiO
2
) on the drain leakage current
of
n
MOSFETs. To our knowledge, no publication has been
devoted from the perspective of both experiment and modelling
to the impact of such high TID levels on the drain leakage
current of this commercial 28-nm bulk CMOS process. We
propose a semi-empirical physics-based approach with only
three parameters to model the parallel parasitic and total drain
leakage current as a function of TID. The lateral parasitic device
has been investigated using TCAD device simulations [19]–
[21], compact models [22], or a combination of these two
approaches [16], [23]. However, these models involve complex
device structures and intensive analytical computations. We
aim at a simpler approach for evaluating the TID-induced drain
leakage current. Taking into account the gate independence
of the drain leakage current at high TID levels, we propose
modelling the lateral parasitic device as a gateless charge-
controlled device by using the simplified charge-based EKV
MOSFET model.
II. EXP ERI MEN TAL DETAILS
Test chips with a matrix of individual MOSFETs were
fabricated with a commercial 28-nm bulk CMOS technology,
which allows the width per finger
WF
from
100 nm
to
3 µm
and the length
Ln
from
30 nm
to
1 µm
. We explore standard
single-finger and multi-finger
n
MOSFETs of various sizes for
identifying the dominant components of drain leakage current
at different TID levels and the favorable device geometry for
radiation-tolerant applications. Each chip has only one transistor
of each size. However, a brief comparison of the same size of
transistors on different chips demonstrates the repeatability of
our measurement results. Enclosed-layout transistors are often
used for isolating the effects of TID on STI oxides [8], [9].
However, the strict design rules of this commercial 28-nm bulk
CMOS process exclude such special structures.
Chips were irradiated at CERN’s in-house 10-keV X-ray
irradiation system (Seifert RP149) at room temperature (
300 K
).
Reference [8] shows that the conducting bias condition
VGB =
VDS =VDD
is the real worst-bias case for commercial 65-nm
bulk
n
MOSFETs from the same foundry, where
VGB
is the
gate-to-bulk voltage,
VDS
is the drain-to-source voltage, and
VDD
is the nominal voltage supply. This is different from the
historical worst-bias case—i.e., the switched-on bias condition
VGB =VDD
and
VDS = 0
[24]. Nevertheless, these two bias
conditions induce no big difference in the drain leakage current
of our 28-nm bulk MOSFETs [25]. Moreover, in most analog
circuits and particularly the analog FE electronics, MOSFETs
are biased in saturation with a nonzero
VDS
except the switches
working at a zero
VDS
. To reproduce as closely as possible the
realistic bias condition, we used the conducting bias condition.
Single-finger and multi-finger
n
MOSFETs were irradiated up
to
1 Grad
(SiO
2
) with steps of 0, 0.5, 1, 5, 10, 50, 100, 200, 400,
600, 800, and 1000
Mrad
at a dose rate of
8.82 Mrad/h(SiO2)
and
10 Mrad/h(SiO2)
, respectively. These two dose rates are
quite similar and make no big difference in terms of TID effects
on our 28-nm bulk MOSFETs. Immediately after each TID step,
static measurements were performed with the Keithley 4200-
SCS Parameter Analyzer. As oxide-trapped charges anneal
with time [26], we chose a voltage step of
25 mV
as a suitable
compromise between limiting the measurement duration and
providing a sufficient measurement resolution. Reference [11]
shows the relatively slow oxide-trapped charge annealing at
room temperature for our 28-nm bulk MOSFETs. This allows
us to neglect the annealing effects that happened during less
than one hour of measurements. More measurement details
can be found in [10], [11].
III. CHARACTERIZATION OF THE DRAIN LEAKAGE
CURRENT
Fig. 3 plots the drain current
ID
of single-finger (a-c) and
multi-finger (d-f)
n
MOSFETs measured in saturation (
VDS =
1.1 V
) versus the overdrive voltage
VGB −VT0
with respect
to TID up to
1 Grad
(SiO
2
), where the threshold voltage
VT0
is extracted as the intercept of the linear extrapolation at the
maximum slope of
√ID
-
VGB
curves at the
VGB
axis. Both single-
finger and multi-finger
n
MOSFETs demonstrate a substantial
increase in the drain leakage current.
Furthermore, the drain leakage current of single-finger
n
MOSFETs presents a width independence and a length
dependence. At high TID levels, single-finger
n
MOSFETs of
the same length (
Ln= 1 µm
), as shown in Fig. 3a and Fig. 3b,
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. XX, NO. XX, X XXXX 3
Fig. 3. Drain current
ID
of single-finger (a-c) and multi-finger (d-f)
n
MOSFETs measured in saturation (
VDS = 1.1 V
) versus overdrive voltage
VGB −VT0
with respect to the total ionizing dose TID.
VT0
is the threshold voltage extracted as the intercept of the linear extrapolation at the maximum slope of
√ID
-
VGB
curves at the VGB axis. The vertical arrow lines point out the location where the drain leakage current IDleak is extracted.
exhibit a close amount of drain leakage current. However,
those of the same width (
Wn= 3 µm
) but different lengths,
as shown in Fig. 3a and Fig. 3c, display different values of
drain leakage current. This width independence and length
dependence jointly indicate the dominant contribution of the
lateral parasitic devices.
In addition to the gate length dependence, the drain leakage
current is also proportional to the number of fingers. At high
TID levels, multi-finger
n
MOSFETs of the same gate length
and the same number of fingers (
Ln= 100 nm
and
NF= 4
), as
shown in Fig. 3d and Fig. 3e, present almost the same amount
of drain leakage current. However, those of the same device
geometry (
Wn/Ln= 12 µm/100 nm
), as shown in Fig. 3d
and Fig. 3f, have the drain leakage current proportional to
the number of fingers. This scalability with the number of
fingers confirms the primary contribution of the lateral parasitic
devices.
Even though the increase in the drain leakage current slows
down at relatively high TID levels, we do not see the rebound
effects of interface-trapped charges [13]. For the tested 28-
nm bulk
n
MOSFETs, trapped holes in STI oxides therefore
play a more important role than charges trapped at silicon/STI
interfaces.
IV. MODELING OF THE DRAIN LEAKAGE CURRENT
This work mainly studies single-finger
n
MOSFETs at the
four corners of the
Wn
versus
Ln
plot, the multi-finger
n
MOSFET with
Wn= 3 µm
and
NF= 4
, and those with
Wn= 12 µm
and
NF=
4, 6, 8, and 12. The total drain leakage
current
IDleak
is extracted at a constant
VGB −VT0
from the
transfer characteristics. Fig. 4a and Fig. 5a plot the extracted
IDleak
of single-finger and multi-finger
n
MOSFETs as closed
markers, respectively. The tested
n
MOSFETs of the same gate
length and the same number of fingers exhibit a close amount
of
IDleak
. This confirms the width independence, the length
dependence, and the dependence on the number of fingers,
demonstrating the main contribution of the lateral parasitic
devices. The log-lin plots with closed markers in Fig. 4b and
Fig. 5b show that the significant increase in
IDleak
mostly
happens before
200 Mrad
of TID. Afterwards, the increase
tends to slow down. This might be due to the saturation effect
of STI-related trapped charges [27].
IDleak
comes from the main
n
MOSFET (
IDleak.main
) and the
lateral parasitic devices (2NFIDleak.par):
IDleak =IDleak.main + 2NFIDleak.par.(1)
The drain leakage current of the main
n
MOSFET
IDleak.main
is mainly composed of the drain-to-gate tunneling current,
the gate-induced drain leakage current, and the subthreshold
current [28]. These leakage components are as a function of the
threshold voltage
VT0
, which is among the most TID-sensitive
device parameters. Plotting
ID
versus
VGB −VT0
isolates the
effects of the TID-induced
VT0
shift.
IDleak
extracted at a
constant
VGB −VT0
with respect to TID therefore has almost the
same contribution from the main
n
MOSFET. In addition, the
substantial increase in
IDleak
is mostly the contribution of the
lateral devices, which allows us to assume a constant
IDleak.main
,
as confirmed by the plateau at low TID levels (
<∼1 Mrad
)
in Fig. 4a and Fig. 5a. Prior to irradiation, neither the oxide-
trapped charge density from the semiconductor processing nor
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. XX, NO. XX, X XXXX 4
Fig. 4. Model validation of the total drain leakage current
IDleak
of single-finger
n
MOSFETs in log-log scale (a) and log-lin scale (b) versus the total ionizing
dose
TID
; (c) model validation of the average parasitic drain-to-source leakage
current
IDleak.par
versus
TID
; (d) average parasitic drain-to-source leakage
current at 1 Grad of TID versus Ln.
Fig. 5. Model validation of the total drain leakage current
IDleak
of multi-finger
n
MOSFETs in log-log scale (a) and log-lin scale (b) versus the total ionizing
dose
TID
; (c) model validation of the average parasitic drain-to-source leakage
current
IDleak.par
versus
TID
; (d) total parasitic leakage current
IDleak −IDleak0
of multi-finger
n
MOSFETs of the same size versus the number of fingers
NF
.
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. XX, NO. XX, X XXXX 5
TABLE I
MOD EL PARAM ETE RS FOR T HE DRA IN-TO -SOUR CE LE AKAGE C URR ENT
Wn/LnNFIDleak0 (A) k TIDcrit (Mrad)
3 µm/1 µm 1 1.34 ×10−10 0.8 58.6
100 nm/1 µm 1 8.47 ×10−12 0.8 1.78
3 µm/30 nm 1 2.17 ×10−10 1.4 7.35
100 nm/30 nm 1 1.90 ×10−11 1.4 1.24
3 µm/100 nm 4 1.65 ×10−10 0.9 4.10
12 µm/100 nm 4 7.84 ×10−10 0.9 22.4
12 µm/100 nm 6 7.37 ×10−10 0.9 12.3
12 µm/100 nm 8 6.37 ×10−10 0.9 8.95
12 µm/100 nm 12 6.42 ×10−10 0.9 5.29
the fringing field from the gate bias is high enough to induce
the parasitic leakage paths in parallel with the main channel or
a total parasitic drain-to-source leakage current comparable to
IDleak.main [29]. This allows us to neglect the parallel parasitic
drain-to-source leakage current before irradiation.
Therefore, the pre-irradiation drain leakage current
IDleak0
,
as plotted by dashed lines in Fig. 4a and Fig. 5a, measures
IDleak.main
. Solving
(1)
gives the average parasitic drain-to-
source leakage current IDleak.par:
IDleak.par =IDleak −IDleak0
2NF
.(2)
Closed markers in Fig. 4c and Fig. 5c exhibit a significant
increase in
IDleak.par
. Moreover, the lateral parasitic devices in
parallel with the main
n
MOSFETs of the same gate length have
almost the same contribution to
IDleak
.
IDleak.par
of long-channel
parasitic devices is actually linearly dependent on
1/Ln
, as
shown in Fig. 4d. The shortest gate length
Ln= 30 nm
falls
beyond the linear fit due to short-channel effects. The linearity
in Fig. 5d evidences the scaling property of the total parasitic
drain-to-source leakage current with the number of fingers.
Considering the constant
IDleak.main
at all TID steps and the
linear relation between
IDleak
and TID in log-log scale at high
TID levels, as shown in Fig. 4a and Fig. 5a, we propose a
simple semi-empirical physics-based model for the total drain
leakage current IDleak:
IDleak =IDleak0 "1 + TID
TIDcrit k#,(3)
where
TIDcrit
is the critical total dose at which the lateral
parasitic devices contribute the same amount of current as
the main
n
MOSFET and
k
is the slope of the log-log plot
at relatively high TID levels calculated by
(log10 IDleak2.par −
log10 IDleak1.par)/(log10 TID2−log10 TID1)
with two sets of
data
IDleak1.par(TID1)
and
IDleak2.par(TID2)
. Solving (2) and (3)
produces the model for the parallel parasitic drain-to-source
leakage current IDleak.par:
IDleak.par =IDleak0
2NFTID
TIDcrit k
.(4)
Fitting (3) with measurement results determines the values
of
TIDcrit
and
k
. Together with
IDleak0
, model parameters are
listed in Table I. The power
k
is the same for
n
MOSFETs
of the same length, whereas the pre-irradiation drain leakage
Drain
Source
LDD Gate oxide
p-Sub
STI
Wn
IDleak.par
+++++ +++++
+++++ +++++
+++++ +++++
Noxeq IDleak.par
Wneq
Gate
Ln
x
z
y
I
Dleak.main
I
Dleak.par
I
Dleak.par
DS
B
G
Fig. 6. Equivalent circuit of an irradiated
n
MOSFET with two gate-independent
lateral parasitic devices (left) and three-dimensional schematic illustration of
the irradiated
n
MOSFET with two parallel parasitic leakage paths formed by
uniformly distributed trapped charges related to shallow trench isolation (STI)
oxides (right).
current
IDleak0
and the critical total dose
TIDcrit
depend on
the device geometry and the number of fingers. Model results
are plotted as solid lines in Fig. 4 and Fig. 5. Using only
three parameters, the proposed semi-empirical physics-based
model demonstrates good agreement with measurement results.
This efficiency makes it a practical method of evaluating the
parallel parasitic and total drain leakage current with respect
to TID.
TIDcrit
indicates the TID level, above which the lateral
parasitic devices contribute the most to the total drain leakage
current
IDleak
. Recent measurements show the independence of
the parallel parasitic drain-to-source leakage current
IDleak.par
on the applied
VDS
during irradiation. This demonstrates the
promising use of this model in accurately predicting the drain
leakage current of
n
MOSFETs working across the whole range
of
VDS
from zero to
VDD
. By extracting the corresponding
values of three model parameters, we can apply this model
easily to alternative CMOS technologies.
V. MODELING THE LATERAL PARASITIC DEVICE AS A
GATE LES S CHA RGE -CONTROLLED DEVICE
A. Equivalent structure for the lateral parasitic device
At high TID levels, the drain current at low values of
overdrive voltage is independent of the gate bias, as shown in
Fig. 3. This weak or negligible gate control is one distinctive
feature of the lateral parasitic device. It is the STI-related
trapped charges that modify the surface potential of the edge
channel and control the mobile charge density of the lateral
parasitic device. This motivates us to model the lateral parasitic
device as a gateless charge-controlled device, as shown by the
equivalent circuit in Fig. 6. Since this lateral parasitic device
has no gate control and is fully controlled by STI-related
trapped charges, we name it as n-QFET.
The applied bias and the dynamic charge movement during
irradiation make the electrical condition inside the device
complex. This results in a non-uniform charge buildup related
to STI oxides [19], [20]. Moreover, the complex channel
doping engineering has been widely used in modern CMOS
technologies, including the retrograde well for preventing the
latch-up effect, the threshold voltage adjustment by ion implant
at the surface, the lightly-doped drain (LDD) for suppressing
the hot carrier degradation, and the halo implant for inhibiting
the punchthrough effect [30]. This leads to a non-uniform
doping profile [16], [19], as illustrated in Fig. 1. Both aspects
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. XX, NO. XX, X XXXX 6
Fig. 7. Surface potential
Ψs
versus the equivalent density of STI-related
trapped charges per unit area Noxeq.
influence the electrical characteristics of the lateral parasitic
n-QFET.
To simplify the modeling task, we introduce an equivalent
structure for the lateral parasitic
n-Q
FET, as illustrated in Fig. 6.
It has a uniform channel doping concentration (
Nb
) that is the
same as the main channel. It also has an equivalent STI-related
trapped-charge density
Qoxeq =qNoxeq
that models the complex
charge distribution:
Qoxeq =RWn.par
0RLn.par
0Qox(x,y)dxdy
WneqLneq
,(5)
where
Qox(x,y)
is the local STI-related trapped-charge density,
Wn.par
is the local width,
Ln.par
is the local length,
Wneq
is the
equivalent channel width, and
Lneq
is the equivalent channel
length. The equivalent STI-related trapped-charge density
Qoxeq
is uniform over a certain width
Wneq
and a certain length
Lneq
.
IDleak.par
is assumed above the bottom of source and drain
extensions. It is then straightforward to assume
Lneq
equal to
the gate length of the main channel Lnand Wneq equal to the
junction depth of source and drain extensions
Xj
, where
Ln
and Xjare two known parameters.
B. Utilization of the simplified EKV MOSFET model
The simplified EKV MOSFET model is able to fully describe
large- and small-signal characteristics over a wide range of
bias from weak via moderate to strong inversion with only four
parameters—i.e., the slope factor
n
, the specific current
Ispec
, the
velocity saturation parameter
λc
, and the threshold voltage
VT0
.
References [12], [31], [32] have verified the applicability of this
model for this commercial 28-nm bulk CMOS process. Since
the gateless charge-controlled concept involves no gate voltage
or gate oxide capacitance, we need to modify the simplified
EKV MOSFET model for the lateral parasitic n-QFET.
Solving the Gauss’s law and the Poisson’s equation gives
the relation between the local silicon charge density
Qsi
and
the surface potential Ψs:
Qsi =
−Γb.par√UTsexp −2ΦF−Vch
UTexp Ψs
UT−1+Ψs
UT
,(6)
Fig. 8. Linearization of the mobile charge density
Qm
with respect to the
surface potential Ψs.
where
Γb.par =√2qsiNb
is defined as the substrate modulation
factor,
q
is the elementary charge,
si
is the silicon permittivity,
UT=kT/q
is the thermal voltage,
k
is the Boltzmann constant,
T
is the temperature,
ΦF=UTln(Nb/ni)
is the Fermi potential,
ni
is the intrinsic carrier concentration,
Vch
is the channel
voltage equal to
VS
at source and
VD
at drain, and
VS
and
VD
are
the source and drain voltages, respectively. Note that in [33], the
substrate modulation factor is defined as
Γb=√2qsiNb/Cox
that links
Γb.par
by
Γb.par =ΓbCox
, where
Cox
is the gate oxide
capacitance.
The charge neutrality condition provides the key bridge
between STI-related trapped-charge density and total silicon
charge density:
Qoxeq =−Qsi.(7)
Solving (6) and (7) gives the link between
Qoxeq
and
Ψs
. Fig. 7
shows that for a higher channel doping concentration, a higher
STI-related trapped-charge density is needed to switch on the
lateral parasitic
n-Q
FET. Since
Nb= 3.7×1018cm−3
and
ΦF= 0.5 V
for our 28-nm bulk
n
MOSFETs,
Noxeq
needs to
be higher than
4.94 ×1012cm−2
to bias the lateral parasitic
n-Q
FET in weak inversion (
ΦF<Ψs<2ΦF
) and
7.06 ×
1012cm−2
in strong inversion (
Ψs≥2ΦF
). Therefore, we expect
that advanced bulk CMOS technologies, which have a higher
channel doping concentration, can withstand a much higher TID
before having enough STI-related trapped charges to switch
on the lateral parasitic n-QFET.
The charge-sheet approximation gives the expression of
depletion charge density
Qb=−Γb.par√Ψs
. The differen-
tiation of
Qb
versus
Ψs
gives the depletion capacitance
Cd=Γb.par/(2√Ψs)
. As shown in Fig. 8,
Cd
slightly depends
on
Ψs
in inversion operation. This enables us to linearize the
depletion charge density
Qb
, as shown by the approximated
red dashed line in Fig. 8. The length of the vertical double-
arrowheaded line in Fig. 8 represents the mobile charge density
Qm=−Qoxeq −Qb
that can be linearized in inversion region
as
Qm=−Cd(ΨP.par −Ψs),(8)
where
ΨP.par
is the pinch-off potential. Once
Ψs
reaches
ΨP.par
,
Qm
becomes 0 and
Qb
equals to
−Qoxeq
, which gives the
expression of
ΨP.par
:
ΨP.par =Q2
oxeq/Γ2
b.par
. Note that in [33],
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. XX, NO. XX, X XXXX 7
5.83
6.00
6.16
6.32
6.48
6.63
6.78
6.93
(7.07 12)2
5.83
6.00
6.16
6.32
6.48
6.63
6.78
6.93
(7.07 12)2
5.83
6.00
6.16
6.32
6.48
6.63
6.78
6.93
(7.07 12)2
5.83
6.00
6.16
6.32
6.48
6.63
6.78
6.93
(7.07 12)2
Fig. 9. Square of the extracted (markers) and modeled (lines) equivalent density of STI-related trapped charges per unit area
N2
oxeq
versus the total ionizing
dose (
TID
) in lin-log scale for single-finger (ac) and multi-finger (bd)
n
MOSFETs. (a) and (b) correspond to the full simplified EKV MOSFET model, whereas
(c) and (d) correspond to the weak inversion approximation.
the slope factor
n
is defined as
n= 1 + Γb/(2√Ψs)
that links
the depletion capacitance Cdby Cd=Cox(n−1).
Subtracting Qbfrom Qsi gives the expression of Qm:
Qm=−Γb.par√UT
"sexp −2ΦF−Vch
UTexp Ψs
UT−1+Ψs
UT−rΨs
UT#.(9)
Under the flatband condition,
Ψs
and
Qm
equal to zero.
Combining (8) and (9) and following the steps from (3.40)
to (3.48) in [33] with the redefined parameters, we obtain the
charge-voltage relation:
vp.par −vs,d = 2qs,d + ln qs,d ,(10)
where
qs=QiS/Qspec.par
is the normalized mobile charge
density at source,
qd=QiD/Qspec.par
is the normalized mobile
charge density at drain,
QiS
and
QiD
are the mobile charge
densities at source and drain, respectively,
Qspec.par =−2CdUT
is the specific charge,
vp.par =VP.par/UT
is the normalized
pinch-off voltage,
VP.par =Q2
oxeq/Γ2
b.par −2ΦF−(ln 2)UT
is
the pinch-off voltage,
vs=VS/UT
is the normalized channel
voltage at source, and
vd=VD/UT
is the normalized channel
voltage at drain.
Adopting the drift-diffusion model
ID=
−µn(Wneq/Ln)RVD
VSQmdVch
, we obtain the charge-current
relation:
if,r =q2
s,d +qs,d,(11)
where
if=IF/Ispec.par
is the normalized forward current,
ir=IR/Ispec.par
is the normalized reverse current,
IF
and
IR
are the forward and reverse currents, respectively,
Ispec.par =
2µnCdU2
TWneq/Ln
is the specific current, and
µn
is the low-
field electron mobility that is assumed equal to that of the
main
n
MOSFET. The parallel parasitic drain-to-source leakage
current
IDleak.par
is the difference between the forward current
IF
and the reverse current
IR
. Since the reverse current
IR
is
negligible in saturation, combining (10) and (11) and neglecting
IRleads to the current-voltage relation:
vp.par −vs=p1+4idleak.par
+ ln p1+4idleak.par −1−(1 + ln 2),(12)
where
idleak.par =IDleak.par/Ispec.par
is the normalized parasitic
leakage current. Taking into account the velocity saturation (VS)
effect, the current-voltage relation for short-channel parasitic
n-QFETs becomes [34]:
vp.par −vs=q(1 + λcidleak.par)2+ 4idleak.par +
ln q(1 + λcidleak.par)2+ 4idleak.par −1−(1 + ln 2),
(13)
where
λc=Lsat/Ln
is the VS parameter and
Lsat
corresponds
to the section of the channel where the carrier drift velocity
saturates.
Lsat
is assumed equal to that of the main
n
MOSFET.
The proposed charge-controlled concept is similar to the
work of Zebrev et al. [35]. However, the work of Zebrev
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. XX, NO. XX, X XXXX 8
5.48 6.70
5.91 6.32 7.07x10
12
( )25.48 6.70
5.91 6.32 7.07x10
12
( )2
Fig. 10. Extracted and modelled parasitic drain-to-source leakage current
IDleak.par
of single-finger (a) and multi-finger
n
MOSFETs (b) versus the square of the
density of STI-related trapped charges N2
oxeq.
et al. focuses on the inter-device parasitic leakage current
underneath the STI oxide between the n-well of a pMOSFET
and the source/drain of the nearby nMOSFET, whereas our
work focuses on the intra-device parasitic leakage current along
the STI sidewalls in parallel with the main n-type channel.
Moreover, the work of Zebrev et al. is limited to the linear
operation and validated at low TID levels (krad), whereas our
approach is able to cover the parallel parasitic drain-to-source
leakage current from linear to saturation and extends to rather
high TID levels up to 1 Grad.
C. Extraction of the equivalent density of STI-related trapped
charges
Solving (2) with (12) or (13), we extract the equivalent
density of STI-related trapped charges
Noxeq
from measurement
results. Combining (4) with (12) or (13), we obtain the
Noxeq
predicted by the proposed models. The square of the extracted
and modeled
Noxeq
are plotted as closed markers and solid lines
in Fig. 9a and Fig. 9b, respectively. Model results are in good
agreement with the extraction. The lateral parasitic
n-Q
FETs of
the same length have the same amount of STI-related trapped
charges, which is consistent with their close amount of parallel
parasitic drain-to-source leakage current.
D. Weak inversion approximation
As mentioned in Section
V-B
,
Noxeq
needs to be higher
than
7.06 ×1012cm−2
for
Ψs
to be higher than
2ΦF
and to
bias the parasitic
n-Q
FET in strong inversion. However, as
shown in Fig. 9a and Fig. 9b, the highest value of
Noxeq
is
around
6.95×1012 cm−2
. This meets our intuition that even after
1 Grad
(SiO
2
) of TID, the lateral parasitic
n-Q
FET still works
in weak inversion and might eventually enter the moderate
inversion. Therefore, we consider only the weak inversion
operation for an approximated solution to the equivalent density
of STI-related trapped charges.
Now we focus on the logarithmic term of (10):
vp.par −vs=
ln qs
. Substituting the normalized variables with the absolute
values brings back to the original expression:
Qm/(−2CdUT) =
exp[(VP.par −V)/UT]
. Introducing it into the drift-diffusion
model gives
IDleak.par =2µnCdUTWneq
LnZVD
VS
exp VP.par −Vch
UT
dVch.(14)
Solving the integral gives the parallel parasitic drain-to-source
leakage current in weak inversion IDleak.par:
IDleak.par =Ispec.par exp VP.par −VS
UT−exp VP.par −VD
UT!.
(15)
Since
VD>VP.par
in saturation,
IDleak.par
is finally modeled as:
IDleak.par =Ispec.par exp VP.par −VS
UT
.(16)
Combining (4) and (16), replacing
VP.par
with
Q2
oxeq/Γ2
b.par −
2ΦF−(ln 2)UT
, and including the VS parameter
λc
, we
obtain the approximated solution for STI-related trapped-charge
density:
Q2
oxeq =Γ2
b.parUT
ln (2 + λc)IDleak0
2Ispec.par +kln TID
TIDcrit +2ΦF
UT
+ ln 2.
(17)
Setting λcto zero leads to the long-channel model.
The square of the extracted and modeled
Noxeq
using the weak
inversion approximation are plotted as open markers and dashed
lines in Fig. 9c and Fig. 9d, respectively. The weak inversion
approximation presents almost the same results as the full
simplified EKV MOSFET model, except the slight mismatch
at ultra-high TID levels where the lateral parasitic
n-Q
FET
approaches the moderate inversion. In addition, the straight
lines fit the relation of
Q2
oxeq ∝kln(TID/TIDcrit)
in (17). The
weak inversion model is therefore a very good approximation
for the parallel parasitic drain-to-source leakage current.
Replacing all defined terms in (16) with the full expressions
provides a direct link between the parallel parasitic drain-
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. XX, NO. XX, X XXXX 9
to-source leakage current
IDleak.par
and the channel doping
concentration Nb:
IDleak.par ∝exp Q2
oxeq
2qsiNbUT
.(18)
The parallel parasitic drain-to-source leakage current IDleak.par
increases exponentially with the square of STI-related trapped-
charge density
Q2
oxeq
, as shown by the straight lines in the log-lin
plots in Fig. 10. For a higher channel doping concentration
Nb
,
the lateral parasitic
n-Q
FET needs a higher
Qoxeq
to reach the
same amount of
IDleak.par
. Advanced CMOS technologies with a
higher channel doping concentration is therefore advantageous
in terms of radiation-induced static power consumption.
VI. CONCLUSION
This paper characterizes and models the effects of total
ionizing dose (TID) up to
1 Grad
(SiO
2
) on the drain leakage
current of
n
MOSFETs fabricated with a commercial 28-nm bulk
CMOS process. Static measurements demonstrate a significant
increase up to four orders of magnitude in the drain leakage
current. At high TID levels, the drain leakage current is
independent of the width but dependent on the length and
the number of fingers, indicating the dominant contribution of
the TID-induced lateral parasitic devices.
We model the parallel parasitic and total drain leakage current
as a function of TID with a semi-empirical physics-based
approach. Using only three parameters, model results have good
agreement with measurements. One of those three parameters
is the critical total dose that is defined as the TID, above which
the parallel parasitic drain-to-source leakage current dominates
the total drain leakage current. This model provides a practical
way of predicting the parallel parasitic drain-to-source leakage
current.
Owing to the gate independence of the drain leakage current
at high TID levels, we model the lateral parasitic device as a
gateless device that is fully controlled by STI-related trapped
charges. The simplified charge-based EKV MOSFET model
indicates that even at
1 Grad
, the STI-related trapped-charge
density is not high enough to bias the lateral parasitic device
in strong inversion. The weak inversion approximation gives a
direct link between the STI-related trapped-charge density and
the parallel parasitic drain-to-source leakage current, indicating
the advantage of a higher channel doping concentration in
termas of radiation-induced static power consumption.
ACKNOWLEDGMENT
The authors would like to thank Dr. Alessandro Pezzotta
from ICLAB of EPFL for his support. The authors would also
like to thank Henri D. Koch from EP department of CERN and
University of Mons for the great help with the measurements.
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