A substrate-dissipating (SD) mechanism for a ruggedness-improved SOI LDMOS device

Abstract

An SOI LDMOS device with improved ruggedness under unclamped inductive switching (UIS) is described based on the substrate-dissipating (SD) mechanism. The key feature of this device is the introduction of a -shape P-island window with a relatively high doping concentration to connect the N-drift region to the P-substrate under the source, which is designed to achieve an avalanche breakdown point at the edge of the P-island instead of near the gate contact. Thus the avalanche current is shortened to the substrate contact through the P-island and the P-substrate, avoiding the avalanche current to pass through the N+ source/P-well junction and thus suppressing the activation of the parasitic bipolar transistor (BJT) with a relaxed self-heating effect especially in the P-well region. As verified by the Medici device simulation results, the SD mechanism of the device under the UIS condition, may endure a remarkably higher avalanche current as compared with the conventional SOI LDMOS device.

Full text

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the Electron Devices Society
WANG et al.: A substrate-dissipating (SD) mechanism for a ruggedness-improved SOI LDMOS device
1

Abstract—An SOI LDMOS device with improved ruggedness
under unclamped inductive switching (UIS) is described based on
the substrate-dissipating (SD) mechanism. The key feature of this
device is the introduction of a Г-shape P-island window with a
relatively high doping concentration to connect the N-drift region
to the P-substrate under the source, which is designed to achieve
an avalanche breakdown point at the edge of the P-island instead
of near the gate contact. Thus the avalanche current is shortened
to the substrate contact through the P-island and the P-substrate,
avoiding the avalanche current to pass through the N+ source/
P-well junction and thus suppressing the activation of the parasitic
bipolar transistor (BJT) with a relaxed self-heating effect
especially in the P-well region. As verified by the Medici device
simulation results, the SD mechanism of the device under the UIS
condition, may endure a remarkably higher avalanche current as
compared with the conventional SOI LDMOS device.
Index Terms—Unclamped inductive switching (UIS), SOI
LDMOS, avalanche current, parasitic BJT, substrate-dissipating
(SD), self-heating.
I. INTRODUCTION
ILICON-ON-INSULATOR lateral diffused metal-oxide
semiconductor (SOI LDMOS) devices are widely used in
power electronic control systems owing to their fast switching
speed and high-impedance capability [1~3]. Many efforts have
been done to achieve the high breakdown voltage (BV) and low
on-state resistance (Ron) [4~6] of the SOI LDMOS devices.
However, as the switching control device, their energy handing
capability and ruggedness performance should also be
considered. Unclamped inductive switching (UIS) test is used as
an extremely severe condition to evaluate the ruggedness of the
device under an inductive load, where the device must dissipate
all of the energy stored in the inductor during the on-state when
turned off. As a consequence, a simultaneous high voltage and
large current may cause a high power loss, which may destroy
the device. Specifically, the failure of a power MOSFET during
a UIS test is mainly due to the activation of the parasitic bipolar
This work was supported by the National Natural Science Foundation of
China (61404110) and National Higher-education Institution General Research
and Development Project (2682014CX097). (Corresponding author: Zhigang
Wang.)
Bing Wang and Zhigang Wang are with the School of Information Science
and Technology, Southwest Jiao Tong University, Chengdu 611756, China.
(E-mail: zhigangwang@swjtu.edu.cn).
James B. Kuo is with the Department of Electrical Engineering, National
Taiwan University, Taipei. (E-mail: kuojb@msn.com).
transistor (BJT), which increases the current and raises the
junction temperature, eventually forcing the device into the
thermal runaway condition [7~9]. In order to suppress the
activation of the parasitic BJT in the device, several methods
have been reported [10~13]. These methods include reducing the
sheet resistance of the P-well beneath the N+ source by using a
high-energy boron implantation or a deep diffusion [10~11] or
minimizing the N+ source/P-well junction with a very thin
vertical source region [12, 13]. As a result, these techniques have
improved the UIS performance considerably. However, the
control of the additional delicate process to define the high dose
body implant is difficult [10, 11] and minimizing the N+ source
region may bring in problems in contacting or threshold-voltage
(Vth) shifting [12, 13].
There is also another method by diverting the avalanche
current direction from the edge to the bottom of the P-well by
employing a segmented trench body contact [14, 15]. However, the
use of trench contact to reroute the avalanche current path
requires more complex contacting technology, especially for the
devices with narrow cell pitches. In addition, the avalanche
current flowing to the P-well may also cause a rise in
temperature to lower the carrier mobilities in the region,
prompting the easier turn-on of the parasitic BJT and thus offset
the improvement in UIS.
In this paper, a substrate-dissipating (SD) mechanism in the
PW-SOI LDMOS device as shown in Fig.1 (a) is proposed to
improve the UIS durability. The SD mechanism is implemented
by introducing an auxiliary pathway to dissipate the UIS energy
to the substrate. Based on this SD mechanism, an SOI LDMOS
device with a Г- shape P-island window (PW) using partial
technique is proposed. In this PW-SOI LDMOS device, the Г-
shape P-island window with the drift region connected to the
substrate offers an auxiliary substrate-dissipated pathway for
expunging the UIS energy. In particular, the P-island window
can move the avalanche breakdown point at the drain side of the
channel to the edge of the P-island window. Thus, the avalanche
current is shorted to the substrate through the window without
activating the parasitic bipolar transistor. Furthermore, this
avalanche current pathway can dramatically relax the
self-heating effect during the UIS-mode operation. Hence, the
UIS durability of this PW-SOI LDMOS may be enhanced
remarkably by the SD mechanism, as compared with
conventional SOI LDMOS (C-SOI LDMOS) device.
Additionally, the aforementioned contact problem or Vth
shifting is avoided.
A substrate-dissipating (SD) mechanism for a
ruggedness-improved SOI LDMOS device
Bing Wang, Zhigang Wang and James B. Kuo, Fellow, IEEE
S

2168-6734 (c) 2018 IEEE. Translations and content mining are permitted for academic research only. Personal use is also permitted, but republication/redistribution requires IEEE permission. See
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the Electron Devices Society
WANG et al.: A substrate-dissipating (SD) mechanism for a ruggedness-improved SOI LDMOS device
2
II. STRUCTURE AND MECHANISM
The schematic cross-section views of the proposed PW-SOI
LDMOS device and the C-SOI LDMOS device are given Fig.
1(a), with the inherent parasitic bipolar junction transistors
(BJTs), which are made of an N+ source as the emitter, a P-well
as the base, and an N-drift region as the collector. As shown in
Fig. 1(a), the base resistance Rb comprises the P-well series
resistance connected to the parasitic BJT base. Unlike the
C-SOI LDMOS device, the proposed device features a
highly-doped P-island window, connecting the N-drift region to
the P-substrate. Moreover, this P-island window is designed in a
specific way, stretching into the N-drift region on the top
surface of the buried oxide (BOX) for ensuring the vertical SD
channel.
Figs.1 (b) and (c) show the schematic UIS test setup and its
typical relevant waveforms. The UIS test can be divided into
three stages. The 1st stage is the turn-on stage, where the device
under test (DUT) is switched on by the pulse voltage generator
(VGS) and the inductance current is at its peak value (Ipeak) in a
time period of tON. The 2nd stage is the breakdown stage, where
the avalanche breakdown state is generated by the switch-off of
the DUT. In the breakdown stage, the DUT must tolerate a
breakdown voltage (BVss) until the drain current decreases from
Ipeak to zero in a time period tAV. The 3rd stage is where the
device sustains a drain applied voltage (VDD). Here, the device is
analyzed only during the second stage.
Based on the description in Figs.1 (a) ~ 1(c), an equivalent
circuit of the device during the second stage under the UIS
condition is given in Fig. 1(d). In the C-SOI LDMOS device, the
avalanche breakdown is occurred at point P1 as shown in Fig. 1
(a). At this point, a vast number of impact-generated carriers are
created to create the avalanche current to consume the UIS
energy. The avalanche-breakdown-induced holes are attracted
to the P+ source contact through the P-well region to generate
the current (ISP), developing a voltage drop Vb across Rb. When
Vb grows to be larger than the built-in potential of the N+
source/P-well junction (~0.7 V), the parasitic BJT is triggered
to form the current path (ISN) with a thermal breakdown.
The avalanche-current handling capacity can be improved by
the introduction of the P-island window in the PW-SOI LDMOS
device as shown in Fig. 1(a). As seen from the Medici
simulation results, the SD mechanism with the P-island window
connecting the drift region to the substrate offers an
avalanche-current pathway to dissipate the UIS energy. In
addition, the P-island window and the N-drift region form an
island junction in the vertical direction, where pre-breakdown is
easier to occur and thus the avalanche point is occurred at
location P2, where the avalanche-induced current flows to the
substrate through the P-island window. As shown in the Fig.
1(d), this substrate-conduct pathway may prevent the forward
bias of the base-emitter junction of the parasitic BJT. Thus, the
trigger of parasitic BJT can be suppressed. Furthermore, the
P-island window provides a self-heating channel for achieving a
good thermal capability.
III. RESULT AND DISCUSSION
Two-dimensional (2D) MEDICI device simulation of the test
device is carried out in this study. In the test setup as shown in
Fig.1 (b), the test device is connected to VDD with an inductive
load of 50 μH. The power supply VDD is 50 V and VGS is 15 V.
tON is the charge time during the turn-on stage, (tON =50 μs). A
short time of 1μs after the tON is defined as the quasi-static point
for analyzing the working mechanism under the UIS avalanche
breakdown condition. The active area of the device 13 mm2 and
other main physical parameters are listed in Table 1.
In particular, the doping concentration ND=7×1015 cm-3 is the
Table 1
Parameters
PW-SOI
LDMOS
C-SOI
LDMOS
N-drift Doping, Nd /cm-3
7×1015
7×1015
P-island Doping, NP-island/ cm-3
(1 ~ 25)×1016
—
P-well Doping, Nwell/cm-3
1×1017
1×1017
P-Substrate Doping, NSub/cm-3
5×1015
5×1015
Device Length, Lsi/μm
13
13
BOX layer Length, Lox/μm
12
13
P-island Length, LP-island/μm
2 ~ 4
—
N-drift Thickness, tsi/μm
2.5
2.5
BOX layer Thickness, tox/μm
1.0
1.0
Device Width, Wsi/mm
103
103
RG
G
Sub
D
S
VDD
VGS
V / I
t
0
IDS
VDS
tON tAV
VDD
BVss
Ipeak
GND
L
VGS
1st 2nd 3rd
x
yN+
N+
P+
P-Substrate
N-drift
x
yN+
P+
P-Well
P-Substrate
N-drift
P2
P1 N+
SGD
SGD
P-Window
BVss
ISub
DSub Rb
Parasitic
BJT
GND
P+
ISP ISN
N+
Sub
P1
P2
ID
tsi
Lsi
tsi
tox
Lsi
LP-island
Rb
BJT
Rb
BJT
P-Well
BOX tox
tox
BOX
(a) (b) (c) (d)
Fig. 1. (a) Structures of PW-SOI LDMOS device (top) and conventional SOI LDMOS device (bottom). (b) The UIS test setup and (c) the typical relevant
waveforms for the DUT under the UIS test condition. (d) The equivalent circuit of the proposed device during the UIS avalanche breakdown period (2nd stage). ID
is the total avalanche current in the device. ISP/ISN/ISub is the avalanche current flowing to the source P+/source N+/substrate.

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the Electron Devices Society
WANG et al.: A substrate-dissipating (SD) mechanism for a ruggedness-improved SOI LDMOS device
3
optimal doping for a best BV of 172 V in the C-SOI LDMOS.
For comparison purposes, this ND=7×1015 cm-3 is also selected
in proposed device. At this ND=7×1015 cm-3, the proposed
device with an optimal NP-island of 1.2×1017 cm-3 and LP-island of
3.5 μm can achieve a BV of 169 V. These results can be verified
from the Fig. 2(a). The Vth and Ron are also simulated and shown
in Fig. 2(b). Apparently, the C-SOI LDMOS and PW-SOI
LDMOS devices share almost the same Vth and Ron, that is,
problems such as the Vth shifting and conductive degradation are
all avoided in the proposed device.
Fig.3 shows the distributions of the impact ionization rate in
the PW-SOI LDMOS and C-SOI LDMOS device under the
quasi-static condition. In the C-SOI LDMOS device, the
avalanche breakdown point is located at P1. In contrast, the
avalanche breakdown point in the PW-SOI LDMOS device is
switched to P2 due to the pre-breakdown occurring at the island
junction. This avalanche breakdown point switched to P2, may
result in reshaping the avalanche-current pathway. The
corresponding distributions of the avalanche current are shown
in Fig.4, where the avalanche current injects into the P+ source
through the P-well in the C-SOI LDMOS device. In contrast, the
avalanche current goes into substrate contact directly in the
PW-SOI LDMOS device when the avalanche breakdown point
switched to P2. Under the UIS test condition as given in Fig. 1
(b), at the avalanche breakdown point, the impact-generated
electrons are swept into drain and holes into ground electrode
(source or substrate). Thus, a different location of avalanche
breakdown may result in a different pathway of avalanche
current.
Fig.5 (a) shows ISN, ISP and ISub in the PW-SOI LDMOS
device and C-SOI LDMOS device. It is clearly both devices
keep conductive by the ISN during the period of tON. These ISN
increase linearly with the time until device are turned off. When
device are turned off, the avalanche current flows mainly as ISP
in the C-SOI LDMOS device as predicted. In contrast, in the
PW-SOI LDMOS device, a high barrier along the substrate
direction is achieved in the N-drift between the P-well and the
P-island. Thus, most avalanche current is driven to the substrate
and ISP has little effects, which confirms the SD mechanism.
0 50 100 150
10-8
10-6
10-4
10-2
100
102
Drain Current (A)
Drain Voltage (V)
C-SOI LDMOS
PW-SOI LDMOS
4 5 6 7 8
50
100
150
200
BV (V)
Nd (1015 cm-3)
BV=172 V
(a)
0 3 6 9 12 15
0
30
60
90
120
Ron= 6.4 mcm2
Transfer
characteristics
@ VDS=5 V
Output characteristics @ VGS=10 V
C-SOI LDMOS
PW-SOI LDMOS
Drain Current (A)
Gate or Drain Voltage (V)
Vth= 5V
(b)
Fig. 2. (a) Output characteristics under the blocking state and (b) Output
characteristics and transfer characteristics in the PW-SOI LDMOS device and
the C-SOI LDMOS device. Insert in (a) is the influence of N-drain region
doping on BV in C-SOI LDMOS.
0 20 40 60 80 100
30
20
10
0
30
20
10
0
30
20
10
0
-10
ISub (A)
Time (s)
C-SOI LDMOS
PW-SOI LDMOS
ISP (A)
ISN (A)
tON=50 s
(a)
0 1 2 3 4 5 6 7 8 9
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
Potential well
P+
P-well
N-drift
BOX
P-island
P-substrate
Potential (V)
y Distance (m)
N+
Barrier=0.6 V
Cutline @x=0.01 m
(b)
Fig. 5. (a) ISN, ISP and ISub in the PW-SOI LDMOS device and the C-SOI
LDMOS device, (b) the potential distribution in the substrate direction at
x=0.01μm in the PW-SOI LDMOS device during the UIS avalanche
breakdown based on Medici simulation results.
I.I. (1027 cm-3 s-1)
0.5 1.0
(b)
I.I. (1027 cm-3 s-1)
0.5 1.0
(a)
Fig. 3. Impact ionization rate distribution in (a) the PW-SOI LDMOS and (b)
the C-SOI LDMOS device during the UIS avalanche breakdown.
0.0
2.0
4.0
6.0
8.0
0.0 4.0 8.0 12.0 0.0 4.0 8.0 12.0
20V/contour
Current flowlinesP1
Current flowlines
P2
y (µm)
x (µm) x (µm)
(a) (b)
20V/contour
Fig. 4. Avalanche current distribution of (a) PW-SOI LDMOS and (b) C-SOI
LDMOS device during the UIS avalanche breakdown.

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WANG et al.: A substrate-dissipating (SD) mechanism for a ruggedness-improved SOI LDMOS device
4
Fig.5 (b) gives the potential in the substrate direction at x=0.01
μm in the PW-SOI LDMOS device during the avalanche
breakdown. A potential barrier of about 0.6 V in the P-well
region is induced in the drift region, driving the
avalanche-induced holes to the substrate instead of the source.
Fig.6 shows the potential distribution along y=0.6 μm in the x
direction in the P-well region of the PW-SOI LDMOS device
and C-SOI LDMOS device based on the Medici simulation
results. The potential contours in the P-well region are given in
the inserts of Fig. 6. In the C-SOI LDMOS device, the voltage
drop between A’-B’ is about 0.4 V. However, in the proposed
device, the voltage drop between A-B is about 0 V. The
existence of Г-shape P-island window impels the avalanche
current, flowing into the substrate contact to avoid a voltage
drop at Rb. Thus, the parasitic BJT is more difficult to trigger.
The inserted illustration also demonstrates that no avalanche
current flows through the P-well region in the proposed device
without the voltage drop in the P-well underneath the N+ region.
In contrast, a large avalanche current in the C-SOI LDMOS
device flows through the P-well with a voltage drop of ~ 0.4 V.
If the charge time tON is big enough to develop a voltage drop
Vb over 0.7 V, the parasitic BJT is triggered on with a current
flowing into the N+ source contact (ISN) during the time tAV. Fig.7
shows the ISN at different tON’s of the PW-SOI LDMOS device
and the C-SOI LDMOS device and the corresponding ISN,AV (the
maximal ISN during the second stage under the UIS test) based
on the Medici simulation results. ISN,AV in the proposed structure
begins to increase at about tON > 305 μs, while ISN,AV in C-SOI
LDMOS device begins to express a rising trend only about tON >
65 μs. That is, the activation of parasitic BJT in PW-SOI
LDMOS needs more charging time. In particular, the maximum
of the sustainable avalanche current (IAV,max) in the C-SOI
LDMOS device is extracted to be 32 A at tON = 64 μs. In contrast,
the IAV,max in PW-SOI LDMOS device is extracted to an even
high avalanche current of ~136 A at tON = 305 μs. This implies
that the sustained avalanche current of the PW-SOI LDMOS
device is about 4.25 times higher than the conventional one,
which is due to the fact that the proposed device offers a wider
vertical pathway to drive the avalanche current away from the
turn-on of the parasitic BJT.
Fig.8 illustrates IAV,max and BV varying the P-island doping
concentration (NP-island) at various lengths of the P-island
(LP-island). At a given LP-island, IAV,max increases with the increment
of NP-island. An increase in NP-island offers a much higher peak in
the electric field at the island-junction. When this electric field
peak is larger than the critical electric field, the pre-avalanche
breakdown is generated at the island junction. This
pre-avalanche at the island junction leads to more avalanche
currents to flow into the substrate directly, thus the avalanche
current to trigger the parasitic BJT is enhanced. A longer LP-island
can also lead to an increment in IAV,max for the same reason that a
pre-avalanche breakdown is easier to occur at the island
junction. Therefore, a high NP-island or long LP-island is a
considerate way to achieve an improved-UIS capacity.
However, a high NP-island or long LP-island brings in a
pre-breakdown at the island-junction and thus results in a
decrease in BV. Namely, under a high NP-island or long LP-island,
island-junction work as the main junction to determine the BV.
Moreover, the higher NP-island or longer LP-island is, the higher
impact ionization at island-junction occurs and the lower BV is
obtained in novel device. The maximum BV can be guaranteed
with low NP-island or short LP-island. The reason is P/N junction at
P1 behaves as the main junction to determine the BV and such a
P-island behaves very little influence on blocking avalanche
breakdown.
Fig.9 shows the influence of the NP-island at various lengths of
the LP-island in ISub/ID of the PW-SOI LDMOS device. A high
NP-island may result in a pre-avalanche breakdown occurring at
the island junction, rendering the avalanche current flowing to
0 4 8 12 16 20 24
40
80
120
160
LP-island (m)
2.0
2.5
3.0
3.5
IAV,max (A)
NP-island (1016 cm-3)
100
120
140
160
180
Breakdown Voltage (V)
Fig. 8. Influence of the doping concentration of the P-island (NP-island) and the
varying length of the P-island (LP-island) in IAV_max and BV of the PW-SOI
LDMOS device.
0 100 200 300 400 500 600
200
150
100
50
0
-50
ISN,AV
tON=305 s;
ISN=136 A
C-SOI LDMOS
PW-SOI LDMOS
ISN (A)
Time (s)
tON=64 s;
ISN=32 A
Fig. 7. ISN at different tON in the PW-SOI LDMOS device and the C-SOI
LDMOS device during the UIS avalanche breakdown based on the Medici
simulation results. ISN,AV is the maximal avalanche current flowing into the N+
source when the device is turned off. The condition ISN,AV > 0 means an
activation of parasitic BJT.
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
-0.4
-0.2
0.0
0.2
0.4
0.6
C-SOI LDMOS
PW-SOI LDMOS
B
B'
A/A'
tON=50 s；
y=0.6 m
Voltage (V)
x Distance (m)

V0.4 V
P+ N+
A' Current
flowlines
SG
B'
P+ N+
A
SG
B
Equi-potenial lines
l
Fig. 6. Potential distribution along the lateral direction at y=0.6 μm (line l) in
the P-well region in the PW-SOI LDMOS device and the C-SOI LDMOS
device during the UIS avalanche breakdown based on Medici simulation
results. Inserts are the corresponding potential contours and current flowlines
in the P-well region in these both devices.

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JEDS.2018.2831278, IEEE Journal of
the Electron Devices Society
WANG et al.: A substrate-dissipating (SD) mechanism for a ruggedness-improved SOI LDMOS device
5
the substrate. In Fig.9 (a), at a given length LP-island of 3.5 μm,
ISub/ID is increased with the increment in the NP-island. In
particular, at a high NP-island of 1.0×1017 cm-3, about 90% of the
avalanche current injects into the substrate. In contrast, at a low
NP-island of 0.2×1017 cm-3, the avalanche current injects into the
substrate is lower than the 20 percent of the total current. In
Fig.9 (b), at the NP-island =8×1016 cm-3, a long LP-island can also
lead an increment in ISub/ID for the same reason that a
pre-avalanche breakdown is easier to occur at the island
junction. If all the avalanche current works as ISub, the parasitic
BJT in the device would never be triggered.
Fig.10 shows the influence of NP-island and LP-island on the
impact ionization rate of the PW-SOI LDMOS device. In Fig.10
(a), at a given LP-island of 3.5 μm, the impact ionization rate at the
island-junction is increased with an increase in NP-island, but the
impact ionization rate at the gate edge is decreased. In Fig.10
(b), at NP-island =8×1016 cm-3, the impact ionization rate at the
island-junction can be increased with an increase in LP-island, but
the impact ionization rate at the gate edge decreases. These
Medici simulation results confirm the trends described in Fig.8
and Fig. 9.
Results presented above are based on the isothermal
condition. In fact, a large amount of energy dumped into the
device during the UIS condition may cause considerable
self-heating of the devices [7, 8]. The self-heating and the ambient
temperature rise may cause the depression of the carrier
mobilities and an easier turn-on of the parasitic bipolar device.
Therefore, it is important to improve the UIS capacity even
under the non-isothermal conditions. Considering the
non-isothermal conditions, the thermal electrode along the top
and bottom are created, respectively. The corresponding
thermal resistances of 2.59×106 W/K•μm with packaging
material of Kapton and 5×103 W/K•μm with heatsink material
of AlSiC material are specialized referring to [16, 17].
Moreover, some temperature-dependent models such as the
temperature-dependent mobility and impact ionization, have
also been considered in the simulation.
Fig.11 (a) shows the maximal lattice temperature at tON=50 μs
in both the PW-SOI LDMOS device and the C-SOI LDMOS
device based on the Medici simulation results. During the first
stage of the UIS test, the lattice temperature keeps at about 300
K due to a low resistance at ON state. When the device is turned
off, the lattice temperature rises sharply at first and then
decreases slowly. In particular, the maximal lattice temperature
in the C-SOI LDMOS is about 442 K at t=59 μs, in contrast, the
maximal lattice temperature in the proposed device is just 401 K
at t=57 μs. Hence, the self-heating effect in the proposed device
is eased remarkably. Fig.11 (b) shows the lattice temperature
along the horizontal direction at y=1 μm at the time of maximal
lattice temperature achieved. It is noted that the lattice
temperature at the P-well region is only smaller than 365 K in
the proposed device and ~438 K in the C-SOI LDMOS device.
Because of the P-island window at the source side offering a
heat-dissipating pathway, a lower lattice temperature is
achieved to reduce the effect on the depression of the carrier
mobilities especially at the source side for enhancing the UIS
capability of the novel device.
Fig.12 (a) shows the ISN in the PW-SOI LDMOS device and
the C-SOI LDMOS device under the non-isothermal condition.
When tON is 50 μs, ISN in the C-SOI LDMOS device is raised
from 0 A up to ~0.4 A as the current peak when device is turned
off. This phenomenon indicates that the UIS sustainable
avalanche current (IAV,max) in the C-SOI LDMOS device is
degraded to about 24 A due to a rise in temperature. In contrast,
2.0 2.5 3.0 3.5 4.0
0
5
10
15
y=2.49 m
x Distance (m)
LP-island=3.5 m
0
5
10
15
20
NP-island (cm)
0.2 0.4
0.6 0.8
1.0
y=0.01 m
I.I.R (1026 cm-3.s-1)
(a)
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
0
5
10 NP-island=81016 cm-3
y=2.49 m
y=0.01 m
x Distance (m)
0
5
10
15
20
LP-island (m)
2.0 2.5
3.0 3.5
4.0
I.I.R (1026 cm-3.s-1)
(b)
Fig.10. Influence of (a) NP-island and (b) LP-island in the impact ionization rate in
PW-SOI LDMOS devices based on the Medici
51 54 57 60 63
0.0
0.2
0.4
0.6
0.8
1.0
1.0
0.8
0.6
0.4
0.2
NP-island ( cm-3)
tON=50 s ;
LP-island=3.5 m
ISub /ID
Time (s)
(a)
51 54 57 60 63
0.0
0.2
0.4
0.6
0.8
1.0 4.0
3.5
3.0
2.5
2.0
LP-island (m)
tON=50 s ;
NP-island=8 cm-3
ISub /ID
Time (s)
(b)
Fig.9. Influence of (a) the doping concentration of the P-island (NP-island) and
(b) the length of the P-island (LP-island) in IPub/ID.

2168-6734 (c) 2018 IEEE. Translations and content mining are permitted for academic research only. Personal use is also permitted, but republication/redistribution requires IEEE permission. See
http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JEDS.2018.2831278, IEEE Journal of
the Electron Devices Society
WANG et al.: A substrate-dissipating (SD) mechanism for a ruggedness-improved SOI LDMOS device
6
in the PW-SOI LDMOS device, the parasitic BJT is more
difficult to turn on even at IAV,max= 72 A, about 3 times bigger
than that in C-SOI LDMOS device. This is due to, on one hand,
the fact a relatively low lattice temperature is achieved by the
heat-dissipating pathway to relax the depression of the carrier
mobilities. On other hand, the avalanche current vertically
injected into the substrate may directly avoid a high voltage
drop on the base resistance Rb even at a high lattice temperature.
Hence, a well UIS capacity can be achieved in the proposed
device even under the non-isothermal condition.
Fig. 13 shows the key process steps for realizing the PW-SOI
LDMOS based on the reference [18]. Firstly, the P-type
substrate wafer is prepared as shown in Fig. 13(a). Then, a thin
thermal oxide is grown on the wafer for preventing oxygen
implantation and structured by using photolithography (PR) and
reactive ion etching as shown Fig. 13(b). The next step is to
implant the O2+ with proper dose and optimized implant
energies to form the partial buried oxide layer as shown in Fig.
13(c). Fig. 13(d) shows that p-type impurities with proper dose
and optimized implant energies are implanted to form the
P-island window after annealing. As shown in Fig. 13(e),
N-type impurities are implanted to form the N-drift region. The
last processes of forming the P-well, source and drain region are
equivalent of the conventional CMOS process as shown in Fig.
13(f).
P-Substrate
Implanting O2+
(c)
Buried Oxide
P-Substrate
PW Buried Oxide
P-Substrate
PW Buried Oxide
N-Drift
P-Substrate
PW Buried Oxide
N-Drift
P-well
P+ N+ N+
Implanting Ion
Implanting Ion
G
SD
Si Wafer
P-Substrate
(a)
PR
Ntride
Oxide
Si Wafer
P-Substrate
(b)
(d)
(e) (f)
Fig.13 The key process steps for the new device: (a) P-type Si wafer; (b) P-type
Si wafer with grown thin thermal oxide; (c) implanting O2+ and annealing to
form the Partial SOI; (d) implanting boron ion and annealing to form the
P-island window; (e) implanting ion and annealing to form the N- drift; (f)
forming the source, P-well and drain region.
Finally, it is noted that the substrate-dissipating (SD)
mechanism can also be applied to the power LDMOS with
RESURF and plate technology. For example, implementation of
the SD mechanism to a double-RESURF SOI LDMOS with
gate plate is given in Fig. 14 under UIS condition. Obviously,
most of avalanche current is swept away into the substrate
contact due to SD effect. However, the BV in Fig. 14(a) with SD
effect is just decreased by 2 V compared with the conventional
one as shown in Fig. 14(b).
0 10 20 30 40 50 60 70
30
20
10
0
tON=50 s, ISN= 24 A
Zoom in
ISN (A)
Time (s)
PW-SOI LDMOS
C-SOI LDMOS
51 54 57 60
0.6
0.4
0.2
0.0
Time (s)
ISN (A)
(a)
0 50 100 150 200
80
60
40
20
0
tON=150 s,
ISN=72 A
Zoom in
ISN (A)
Time (s)
PW-SOI LDMOS
C-SOI LDMOS
152 160 168 176
0.2
0.1
0.0
Time (s)
ISN (A)
(b)
Fig. 12. Simulated ISN in both the PW-SOI LDMOS device and the C-SOI
LDMOS device during the avalanche breakdown under a non-isothermal
condition with tON=50 μs and (b) tON=150 μs, respectively. Insert Figs are
zoom-in diagram of ISN vs. time when devices are turned off.
45 50 55 60 65 70
300
350
400
450
500
tON=50 s
C-SOI LDMOS
PW-SOI LDMOS
401 K; t=57 s
442 K; t=59 s
Temperature (K)
Time (s)

T =41K
(a)
0 2 4 6 8 10 12
300
350
400
450
500
t=59 s ; y = 1 m
N-driftP-well
t=57 s ; y = 1 m
Temperature (K)
x Distance (m)
C-SOI LDMOS
PW-SOI LDMOS
(b)
Fig. 11. (a) The maximal lattice temperature during the UIS test and (b) the
lattice temperature along the horizontal direction at y=1 μm at the time of the
maximal lattice temperature achieved in both the PW-SOI LDMOS and the
C-SOI LDMOS devices.

2168-6734 (c) 2018 IEEE. Translations and content mining are permitted for academic research only. Personal use is also permitted, but republication/redistribution requires IEEE permission. See
http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JEDS.2018.2831278, IEEE Journal of
the Electron Devices Society
WANG et al.: A substrate-dissipating (SD) mechanism for a ruggedness-improved SOI LDMOS device
7
IV. CONCLUSION
A ruggedness-improved SOI LDMOS device using the
P-island window structure with its performance under
unclamped inductive switching is described, as verified by the
MEDICI simulation results. In the new device, the avalanche
current is shortened to the grounded substrate contact through
the P-island and the P-substrate, successfully avoiding the
avalanche current to pass through the N+ source/P-well junction
and thus avoiding the activation of the parasitic bipolar
transistor. With the P-island window, self-heating is relaxed and
thus the proposed device can sustain a larger avalanche current,
as compared with a conventional SOI LDMOS device.
ACKNOWLEDGMENT
Project supported by the National Natural Science Foundation
of China (61404110) and National Higher-education Institution
General Research and Development Project (2682014CX097).
REFERENCES
[1] Jongdae Kim, Tae Moon Roh,Sang-Gi Kim, Q. S. Song,Dae Woo
Lee,Jin-Gun Koo,Kyong-IK Cho,Dong Sung Ma, “High-voltage power
integrated circuit technology using SOI for driving plasma display
panels,” IEEE Transactions on Electron Devices., vol. 48, no. 6, pp.
1256-1263, Jun 2001, DOI: 10.1109/16.925257.
[2] D.MGarner,F Udrea,H.T Lim,G Ensell,A.E Popescu,K Sheng,W.I Milne,
“Silicon-on-insulator power integrated circuits,” Microelectronics
Journal., vol. 32, no. 5, pp. 517-526, Jun 2001, DOI:
10.1016/S0026-2692(01)00024-6.
[3] Florin Udrea, “SOI-based devices and technologies for High Voltage Ics,”
in Proc. Bipolar/BiCMOS Circuits and Technology Meeting., Oct 2007,
pp. 74-81, DOI: 10.1109/BIPOL.2007.4351842.
[4] A.W. Ludikhuize, “A review of RESURF technology,” in Proc. Power
Semiconductor Devices and ICs., May 2000, pp. 11-18, DOI:
10.1109/ISPSD.2000.856763.
[5] I.-Y. Park, C.A.T. Salama, “New superjunction LDMOST with N-buffer
layer,” IEEE Transactions on Electron Devices., vol. 53, no. 8, pp.
1909-1913, Jul 2006, DOI: 10.1109/TED.2006.877007.
[6] Bo Zhang, Zhaoji Li, Shengdong Hu, Xiaorong Luo, “Field enhancement
for dielectric layer of high-voltage devices on silicon on insulator,” IEEE
Transactions on Electron Devices., vol. 56, no. 10, pp. 2327-2334, Sep
2009, DOI: 10.1109/TED.2009.2028405.
[7] K. Fischer, K. Shenai, “Dynamics of power MOSFET switching under
unclamped inductive loading conditions,” IEEE Transactions on electron
devices., vol. 43, no. 6, pp. 1007-1015, Jun 1996, DOI:
10.1109/16.502137.
[8] K. Fischer, K. Shenai, “Electrothermal effects during unclamped
inductive switching (UIS) of power MOSFET's,” IEEE Transactions on
Electron Devices., vol. 44, no. 5, pp. 874-878, May 1997, DOI:
10.1109/16.568052.
[9] K. Chinnaswamy, P. Khandelwal, M. Trivedi, K. Shenai, “Unclamped
inductive switching dynamics in lateral and vertical power DMOSFETs,”
in Proc. Industry Applications Conference., Oct 1999, pp. 1085-1092,
DOI: 10.1109/IAS.1999.801639.
[10] Narazaki, Takano, Oku, Hamachi, Minato, “A marvelous low
on-resistance 20V rated self alignment trench MOSFET (SAT-MOS) in a
0.35 μm LSI design rule with both high forward blocking voltage yield
and large current capability,” in Proc. International Symposium on Power
Semiconductor Devices & ICs., May 2004, pp. 393-396, DOI:
10.1109/WCT.2004.240223.
[11] C. Kocon, J. Zeng, R. Stokes, “Implant spacer optimization for the
improvement of power MOSFETs' unclamped inductive switching (UIS)
and high temperature breakdown,” in Proc. Power Semiconductor
Devices and ICs., May 2000, pp. 157-160, DOI:
10.1109/ISPSD.2000.856795.
[12] Jacky C. W. Ng, Johnny K. O. Sin, Hitoshi Sumida, Yoshiaki Toyoda,
Akihiko Ohi, Hiroyuki Tanaka, Takeyoshi Nishimura, Katsunori Ueno,
“A novel low-voltage trench power MOSFET with improved avalanche
capability,” in Proc. Power Semiconductor Devices & IC's (ISPSD)., Jun
2010, pp. 201-204, ISSN 0018-9383.
[13] Jacky C. W. Ng, Johnny K. O. Sin, Hitoshi Sumida, Yoshiaki Toyoda,
Akihiko Ohi, Hiroyuki Tanaka , Takeyoshi Nishimura , Katsunori Ueno ,
“A new trench power MOSFET with an inverted L-shaped source
region,” IEEE Electron Device Letters., vol. 31, no. 11, pp. 1284-1286,
Sep 2010, DOI: 10.1109/LED.2010.2068032.
[14] Soo-Seong Kim, Jae-Keun Oh, Min-Koo Han, “A new trenched source
power MOSFET improving avalanche energy,” Japanese Journal of
Applied Physics., vol. 42, no. 4S, pp. 2156, Apr 2003, DOI:
https://doi.org/10.1143/JJAP.42.2156.
[15] In-Hwan Ji, Kyu-Heon Cho, Min-Koo Han, Seung-Chul Lee, Soo-Seong
Kim, Kwang-Hoon Oh, Chong-Man Yun, “New power MOSFET
employing segmented trench body contact for improving the avalanche
energy,” in Proc. Power Semiconductor Devices and IC's., May 2008, pp.
115-118, DOI: 10.1109/ISPSD.2008.4538911.
[16] Avant Corp. and TMA, Inc., MEDICI.
[17] Josef Lutz, Heinrich Schlangenotto, Uwe Scheuermann, Rik De Doncker.
Semiconductor Power Devices: Physics, Characteristics, Reliability [M].
2011: 358-340.
[18] S E Jamali Mahabadi, Ali A SOrouji, P Keshavarzi, Hamid Amini
Moghadam, “A new partial SOI-LDMOSFET with a modified buried
oxide layer for improving self-heating and breakdown
voltage,” Semiconductor Science and Technology, vol. 26, no. 9, Jul 2011,
095005, DOI: https://doi.org/10.1088/0268-1242/26/9/095005.
With SD Mechanism
BV=192 V
Without SD Mechanism
BV=194 V
(a) (b)
Fig. 14. Avalanche current distribution of RESURF LDMOS (a) with (a) and
(b) without SD mechanism during the UIS avalanche breakdown.
James B. Kuo (S’85–M’85–SM’92–F’00)
received the B.S.E.E. degree from National Taiwan
University, Taipei, Taiwan, the M.S.E.E. degree
from Ohio State University, Columbus, Ohio, and
the Ph.D. degree from Stanford University, Stanford,
CA. He is currently a Professor with the Department
of Electrical Engineering, National Taiwan
University. His current research interests include
low-voltage CMOS circuits and compact modeling
of SOI CMOS devices.
Zhigang Wang received a PhD degree in
Microelectronics and Solid State Electronics from
University of Electronics Science and Technology of
China in 2013. In 2013, he joined Southwest Jiao
Tong University (SWJTU) in August. His current
research interests include TCAD and modeling of
silicon power devices, wide bandgap power devices
and smart power ICs.
Bing Wang received the B.S. degree from the
Southwest Jiao Tong University (SWJTU),
Chengdu, China, in 2015, where he is currently
pursuing the M.S. degree in microelectronics. His
current research interests include TCAD and
modeling of silicon power devices, wide bandgap
power devices and smart power ICs.