Strong Efficiency Improvement of SOI-LEDs Through Carrier Confinement

Abstract

Contemporary silicon light-emitting diodes in silicon-on-insulator (SOI) technology suffer from poor efficiency compared to their bulk-silicon counterparts. In this letter, we present a new device structure where the carrier injection takes place through silicon slabs of only a few nanometer thick. Its external quantum efficiency of 1.4middot10^-4 at room temperature, with a spectrum peaking at 1130 nm, is almost two orders higher than reported thus far on SOI. The structure diminishes the dominant role of nonradiative recombination at the n⁺ and p⁺ contacts, by confining the injected carriers in an SOI peninsula. With this approach, a compact infrared light source can be fabricated using standard semiconductor processing steps

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IEEE ELECTRON DEVICE LETTERS, VOL. 28, NO. 5, MAY 2007 383
Strong Efficiency Improvement of SOI-LEDs
Through Carrier Confinement
Tu Hoang, Student Member, IEEE, Phuong LeMinh, Jisk Holleman, and
Jurriaan Schmitz, Senior Member, IEEE
Abstract—Contemporary silicon light-emitting diodes in
silicon-on-insulator (SOI) technology suffer from poor efficiency
compared to their bulk-silicon counterparts. In this letter, we
present a new device structure where the carrier injection takes
place through silicon slabs of only a few nanometer thick. Its
external quantum efficiency of 1.4 · 10
−4
at room temperature,
with a spectrum peaking at 1130 nm, is almost two orders higher
than reported thus far on SOI. The structure diminishes the
dominant role of nonradiative recombination at the n
+
and p
+
contacts, by confining the injected carriers in an SOI peninsula.
With this approach, a compact infrared light source can be
fabricated using standard semiconductor processing steps.
Index Terms—Integrated optics, integrated optoelectronics,
light-emitting diodes (LEDs), light sources, luminescent devices,
optoelectronic devices, semiconductor devices, silicon-on-insulator
(SOI) technology.
I. INTRODUCTION
R
ECENT progress in silicon light-emitting diodes (LEDs)
has led to reported internal quantum efficiencies around
3%, potentially offering a new integration approach for very
large scale integration (VLSI) circuits with optical communica-
tion [1]. It was found that high-purity silicon, with low doping
levels and low defect density, leads to the highest efficiency at
the band-to-band recombination wavelength [2], [3]. However,
the silicon LEDs with the highest efficiency emit infrared
light from an extended volume within the silicon wafer. This
lack of spatial confinement prohibits the formation of compact
light-emitting arrays, limits switching speed, and will lead to
undesired crosstalk problems in integrated microsystems. One
approach to a better confinement of the light emission is to form
a silicon LED in silicon-on-insulator (SOI) material. This is
attractive, because both VLSI electronics and integrated optics
are commonly fabricated on SOI wafers [4]. Yet, the highest
reported efficiency of silicon LEDs on SOI is two orders of
magnitude lower than in bulk-silicon LEDs [5].
In this letter, we introduce a novel device structure that
reduces the nonradiative recombination by confining the
carriers in an SOI peninsula. The device exhibits a record-
high quantum efficiency for SOI-LEDs, closing in on bulk-
Manuscript received January 17, 2007. This work was supported by The
Dutch Technology Foundation STW under Project TEL.6159. The review of
this letter was arranged by Editor P. Yu.
The authors are with MESA+ Institute for Nanotechnology, Group of
Semiconductor Components, University of Twente, 7500 AE Enschede, The
Netherlands.
Color versions of one or more of the figures in this letter are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/LED.2007.895415
silicon efficiency levels. It is manufactured with normal VLSI
processing procedures.
II. E
XPERIMENTAL
The starting material is a 100-mm p-type “Smart-Cut” SOI
substrate. The device layer is a 200-nm p-type silicon with a
resistivity of 10–100 Ω · cm. The SOI layer is first etched into
islands. Then, through a repeated local oxidation of silicon, in
combination with buffered-HF wet-etching and ellipsometric
film thickness measurement, we locally create very thin silicon
regions (5–25 nm) of 2-µm wide and 60-µm long. Oxidation
on ultrathin silicon becomes self-limiting [6], [7], enlarging
the process window for this approach. On each wafer, four
different thin-silicon thicknesses are realized to minimize the
impact of wafer-to-wafer process variations. The thickness of
the thinned-down SOI layer was verified using a bright-field
high-resolution transmission electron microscopy (HRTEM).
Example HRTEM images are shown in the inset of Fig. 1(a).
The thinned layer thickness varies with ±2 nm across the
wafer, determined by the SOI uniformity.
After growing a 12-nm thermal oxide, highly doped p
+
and
n
+
regions were formed by annealing 5 × 10
15
cm
−2
BF
+
2
and
As
+
implants at 800
◦
C for 30 min. Then, a 300-nm P-doped
poly-silicon gate electrode was deposited and patterned over
the thinned regions. After opening contact windows, metal
contacts were made by sputtering and patterning TiW/Al(Si)
interconnect. Fig. 1(a) shows a schematic drawing of the device.
Electrical characteristics were measured using a Cascade probe
station and an Agilent 4156C parameter analyzer. The
integrated electroluminescence (EL) intensity emitted from
our devices was recorded by a calibrated Xenics InGaAs near-
infrared camera via a microscope with near-infrared objective
lenses; the camera can be extended with a Specim spectroscope.
The optical setup was calibrated using a halogen lamp, a Ge
detector, and a Spectralon Lambertian surface. The calibrated
energy measured from the device was then divided by the pho-
ton energy to obtain the number of collected photons. Then, the
external quantum efficiency is defined as the ratio of the number
of collected photons and the number of injected electrons.
III. R
ESULTS AND DISCUSSION
The basic philosophy behind the device architecture is that
a volume of lowly doped monocrystalline silicon can emit
infrared light with reasonable efficiency (through phonon-
assisted band-to-band recombination), as long as compet-
ing nonradiative recombination mechanisms [8] are well
0741-3106/$25.00 © 2007 IEEE

384 IEEE ELECTRON DEVICE LETTERS, VOL. 28, NO. 5, MAY 2007
Fig. 1. (a) Schematic cross section of the p
+
/p/n
+
diode. The infrared
emitted light is collected from the front side of the wafer. The distance between
the thinned-down regions is 5 µm; thinned-down regions are 2-µm wide,
and the device length is 60 µm. The insets show cross-sectional HRTEM
images of the thinned-down silicon regions with thickness of 5 nm. (b) I–V
characteristics of five diodes with the same structure, except the thickness of the
thinning-down region. Inset is a top-view infrared image of the device (biased
at 1 mA), taken with the InGaAs infrared camera via a 50×-microscope. The
dashed lines indicate the boundary of the SOI island. The bright central area is
the active region (p-type peninsula); the two outer bright lines are interpreted as
wave-guided light escaping from the edge of the two poly-gates. The integrated
intensity from the edges amounts to 10%–15% of the total light emission.
suppressed. To this purpose, high-quality Si is chosen (using
SmartCut wafers); the silicon layer is enclosed by thermally
grown SiO
2
with high-quality interfaces; and the doping level is
maintained as supplied. Under these circumstances, we expect
the recombination at the p
+
and n
+
contacts [9] as well as
the Si-SiO
2
interfaces [10] to dominate the nonradiative re-
combination. If the recombination at the p
+
and n
+
contacts is
effectively suppressed by creating a barrier to this recombina-
tion, the highest possible internal efficiency in this geometry is
close to 1%, assuming a surface recombination velocity of s
r
=
10 cm/s [11].
Current–voltage (I–V ) characteristics of devices were mea-
sured between the n
+
and p
+
regions showing diode operation
with a slope of 72 mV/decade. Holes and electrons are injected
into the central area through the thinned regions. The access
resistance of this diode is high and increases with decreasing
silicon thickness. By application of a negative voltage (V
b1
) to
the poly-gate next to the p
+
region and a positive voltage (V
b2
)
to the poly-gate next to the n
+
region, the carrier density in the
thinned silicon layer is enhanced. This leads to a good forward
conduction: At V
b1
= −1 V and V
b2
=+1 V, 1 mA flows at
∼2-V forward bias. Fig. 1(b) shows the I–V characteristics of
five diodes with varying thinned-region thickness. The distribu-
tion and the spatial location of the emitted light can be seen in
a top-view infrared image of the device [inset in Fig. 1(b)].
We compared the electroluminescence of five diodes, that
only differ in the thickness of the thinned access silicon film.
Their EL spectra with the same intensity peak at ∼1130-nm
wavelength are recorded in Fig. 2(a). The electroluminescence
increases with as much as a factor of 24 when access regions
are thinned from 145 to 5 nm, as quantified by the integrated
EL intensity in the inset of this figure. This enhancement of
electroluminescence, in identical silicon volumes (on the same
wafer) but with different access regions, is explained by a
confinement of the injected carriers in this volume.
Three effects may contribute to the carrier confinement in the
realized structure.
1) By administering the appropriate gate potential, minority
carriers experience a potential barrier in this thin film.
2) Injected carriers have difficulty in finding the exit through
diffusion, as it is geometrically small.
3) The silicon layer is so thin, that bandgap widening effects
may play a role (below ca. 10 nm).
The effect of gate voltages was studied on a diode with
19-nm thinned regions, forward-biasing the diode with 1 mA
under two biasing conditions: first, with both poly gates
grounded and, second, with gate biases of V
b1
= −1 V and
V
b2
=+1 V. The latter condition creates a high electron density
in the thin silicon region connected to the n
+
contact and a
high hole density in the thin film adjacent to the p
+
contact.
Not only does this reduce the diode’s external resistance but
holes, injected into the p-type silicon, now encounter a potential
barrier on their way to the n
+
region, and similar for electrons,
vice versa. We observe a factor 3 higher integrated electrolumi-
nescence under the biased condition.
Thinning down the access regions has a much stronger effect
[inset of Fig. 2(a)]. A monotonous increase of EL is observed,
while the quantum-size effect is known to be significant only
when the silicon layer thickness is below 10 nm [13], [14].
The electroluminescence is inversely proportional to the access
region thickness in the full range. This is evident that the effect
has a purely geometrical origin. The external quantum effi-
ciency of the device at room temperature under a 1-mA forward
current reaches 1.4 · 10
−4
for the device with the thinnest SOI
layers (5 nm). The light output–current (L–I) characteristics
of those diodes at room temperature are shown in Fig. 2(b).
Note that the surface of this device did not receive any special
treatment to maximize the outcoupling of light [1].
The temperature dependence of the integrated EL intensity
of the fabricated devices was investigated in the range of
253–473 K. An increase in the integrated EL intensity with
the temperature was observed for devices with and without
thinning when the gates are floating. This trend is in line with
the bulk-silicon LED behavior [3], [12], [15]. However, an

HOANG et al.: STRONG EFFICIENCY IMPROVEMENT OF SOI-LEDs THROUGH CARRIER CONFINEMENT 385
Fig. 2. Light emission properties of the fabricated SOI-LEDs. (a) Emission
spectra of five devices with varying access region thickness. Inset: Integrated
electroluminescence as a function of access silicon thickness. (b) L–I char-
acteristics of five diodes at room temperature at gate biases of V
b1
= −1V
and V
b2
=+1 V. (c) Integrated electroluminescence as a function of device
temperature for diodes with and without thinned access regions; and varying
the gate biasing.
opposite temperature dependence was seen when biasing the
poly-gates, as shown in Fig. 2(c). In confined-carrier systems,
the confinement is normally reduced with increasing temper-
ature. In our device, this happens through the increase of the
minority carrier concentration in the thin regions at fixed gate
potential. This qualitatively explains the weak thermal quench-
ing. The found temperature dependence behavior indicates that
our devices work efficiently at around room temperature and
above, allowing the utilization of this emission process in
integrated microsystems.
IV. C
ONCLUSION
A compact Si LED realized on SOI is presented. Its operation
is based on phonon-assisted band-to-band recombination in
high-quality silicon. Using thinned-down gated silicon access
regions, the quantum efficiency is shown to improve with
almost two orders of magnitude. The device exhibits a record
of electroluminescence efficiency for SOI-LEDs. Compared
to bulk-silicon LEDs, it has the advantage of a laterally and
vertically well-defined light emission spot and, possibly, a
higher switching speed.
A
CKNOWLEDGMENT
The authors would like to thank Y. Ponomarev (Philips)
for donating Smart-Cut SOI wafers; M. Kaiser and
M. Verheijen (Philips) for HRTEM measurement support;
M. Goossens (Philips) and G. ’tHooft (Philips/Leiden
University) for fruitful discussions; and S. Smits, T. Aarnink,
and the MESA+ Clean Room for the technical support.
R
EFERENCES
[1] M. A. Green, J. Zhao, A. Wang, P. J. Reece, and M. Gal, “Efficient
silicon light-emitting diodes,” Nature, vol. 412, no. 6849, pp. 805–808,
Aug. 2001.
[2] T. Trupke, J. Zhao, A. Wang, R. Corkish, and M. A. Green, “Very efficient
light emission from bulk crystalline silicon,” Appl. Phys. Lett., vol. 82,
no. 18, pp. 2996–2998, May 2003.
[3] T. Hoang, P. LeMinh, J. Holleman, and J. Schmitz, “The effect of disloca-
tion loops on the Light Emission of Silicon LEDs,” IEEE Electron Device
Lett., vol. 27, no. 2, pp. 105–107, Feb. 2006.
[4] G. T. Reed and A. P. Knights, Silicon Photonics: An Introduction.
Hoboken, NJ: Wiley, 2004, p. 57.
[5] J. Zhao, G. Zhang, T. Trupke, A. Wang, F. Hudert, and M. A. Green,
“Near-band edge light emission from silicon semiconductor on insulator
diodes,” Appl. Phys. Lett., vol. 85, no. 14, pp. 2830–2832, Oct. 2004.
[6] H. I. Liu, D. K. Biegelsen, F. A. Ponce, N. M. Johnson, and R. F. W. Pease,
“Self-limiting oxidation for fabricating sub-5 nm silicon nanowires,”
Appl. Phys. Lett., vol. 64, no. 11, pp. 1383–1385, Mar. 1994.
[7] F. E. Prins, C. Single, F. Zhou, H. Heidemeyer, D. P. Kern, and
E. Plies, “Thermal oxidation of silicon-on-insulator dots,” Nanotechnol-
ogy, vol. 10, no. 2, pp. 132–134, Jun. 1999.
[8] D. K. Schroder, “Carrier lifetimes in silicon,” IEEE Trans. Electron De-
vices, vol. 44, no. 1, pp. 160–170, Jan. 1997.
[9] F. Berz, “A simplified theory of the p-i-n diode,” Solid State Electron.,
vol. 20, no. 8, pp. 709–714, Aug. 1977.
[10] M. J. Kerr and A. Cuevas, “Very low bulk and surface recombination in
oxidized silicon wafers,” Semicond. Sci. Technol., vol. 17, no. 1, pp. 35–
38, 2002.
[11] T. Rudenko et al., “Determination of film and surface recombination in
thin-film SOI devices using gated-diode technique,” Solid State Electron.,
vol. 48, no. 3, pp. 389–399, Mar. 2004.
[12] W. L. Ng, M. A. Lourenco, R. M. Gwilliam, S. Ledain, G. Shao, and
K. P. Homewood, “An efficient room-temperature silicon-based light-
emitting diode,” Nature, vol. 410, no. 6825, pp. 192–194, Mar. 2001.
[13] A. T. Fiory and N. M. Ravindra, “Light emission from silicon: Some per-
spectives and applications,” J. Electron. Mater., vol. 32, no. 10, pp. 1043–
1051, Oct. 2003.
[14] N. M. Park, T. S. Kim, and S. J. Park, “Band gap engineering of amor-
phous silicon quantum dots for light-emitting diodes,” Appl. Phys. Lett.,
vol. 78, no. 17, pp. 2575–2577, Apr. 2001.
[15] M. Kittler, M. Reiche, T. Arguirov, W. Seifert, and X. Yu, “Silicon-
based light emitters,” Phys. Stat. Sol., A, vol. 203, no. 4, pp. 802–
809, 2006.