A new full-adder design using XNOR-XOR circuit

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Abstract—
XNOR-XOR circuit is an essential part of many
arithmetic circuits. In this seminal, proposed a 4T
XNOR-XOR and 8T full-adder circuit. The proposed full-
adder circuit designed by various logic styles is to be
performed at an elaborated transistor-level to compare
quantitatively and less number of transistor. The
Simulation outcome demonstrates that the newly-
proposed circuitry exhibit power consumption, less PDP
and better performance in silicon area. These
performances of all circuits are using the 90nm model
parameter. Whole circuit simulation outcomes were
obtained from TSPICE.
Keywords: XNOR, XNOR-XOR, power dissipation, delay.
I.
INTRODUCTION
Nowadays, low power-consumption, high-speed circuits, and
area are the design trade-offs in VLSI industries. The
evolution of portable electronics, computing devices is
the importance of low-power circuit design methodologies.
Low-power-dissipation, least delay, and area are to be needs
one of them important design factors for VLSI designers. To
increase the performance in VLSI circuits, there is required
to be less the power saving and the area. Behind these
designs, driving forces have the essential portable device
different applications for less power-dissipation, minimum
delay and higher throughput. An addition is an arithmetic
operation, extensively used in several low-power VLSI
circuits, like as specific application DSP architectures and
microprocessors. These modules are used for many
arithmetic operations, like as addition, subtraction [1]. Thus,
these facts of view, the design of a full-adder circuit are
having low-power-dissipations, lower the delay, and high-
speed performance [1-15]. Many researchers are
emphasizing on circuit performance through the minimum
level of transistor count. XOR-XNOR circuit are the basic
structures block of F-A. The increasing the performance of
an XNOR-XOR circuit can be significantly increases the
better perform of the F-A design.
In this brief article is consolidated as follows: Section II, we
discussed the mathematical equation which introduced new
circuit design and optimized previous full-adder. Section III,
proposed full-adder circuit design using XNOR-XOR circuit.
In section IV, The simulation an analysis outcomes proposed
and previous existing design is given papers and shows the
comparisons.
II. PRELIMINARIES
(A) Previous full-adder optimized
Several existing papers have been illumined about the
optimization of 1-bit full-adders (F-A) cell, which are trying
various logic styles, XOR & XNOR gate, XOR-XNOR
circuit, complementary pass-transistor-logic (CPTL) and
multiplexer [3], [4], [5]. Comparative studies to design the
implementation for block 1 were presented in [6]. In the
block 1 modified the XNOR-XOR circuit for F-A made with
the logic showing in fig.2. This module design is essential to
determine an intermediate
AB
:
and,
AB⊕
which are
used to drive other circuits to acquire the sum outputs.
Fig.1. Functional segment diagram Full-adder.
The functional segment diagram of the F-A is showing in
fig.1. Most improvements for the designing module have
been accepted as standard configurations. The proposed
configuration, the F-A module is made of three logical
blocks: XNOR-XOR circuit to obtain and block 1, block2, to
obtain the sum output of a multiplexer and Carry output
block 3.
In review all the circuits, it could be shown that the sum-
output is equalable to the A XNOR B (
AB:
) value when
Cin = 0, and when Cin=1, then even the output value is
equalable to
AB⊕
. Thus, the MUX could be utilized to
calculate the individual value taking the Cin input as the
selection signal.
For the same criteria applying, the Carry output logic levels
is equalable to the
AB•
(AND) value when Cin=0, and
when Cin=1, that is equalable to the
AB⊕
value. Cin
input utilized to select the individual value for a required
condition to driving a multiplexer in the F-A circuit.
Therefore, use of different logic schemes in F-A cell,
basically, it could be utilized by an XNOR-XOR circuit to
acquired the
AB:
and
AB⊕
signal, and
multiplexers are being driven by the Cin input to obtain the
outputs.
A new full-adder design using XNOR-XOR Circuit
Rajeev Kumar Sandeep Gotam Vikram Singh
ECE Dept, ECE Dept, SIRDA Group of Institutions
Glocal University, Saharanpur, THDC-IHET Tehri, Naulakha, Sunder Nagar,
UP, India Uttarakhand India Himachal Pradesh, India
rajeevkrc@gmail.com sandeepgotam@gmail.com tomar.vs@gmail.com

(A) XNOR-Gate
The XNOR-gate structures required non-complementary
output would be almost perfect. This assortment is showing
in fig.2 [2]. For these input cases of AB = 00, 01, 11 output
signal will be complete. While the input pattern of A=1 and
B = 0, nMOS transistor will be "ON" and passes the poor
“HIGH” output signal level. Which is give the bad output
signal levels, but to solved the problem, manipulation the
ratios (W/L) of MP1 and MN1 transistors until a logic level
is restored.
Fig.2- XNOR Gate function [2].
M. Vesterbackaet al. [3], a 16T F-A had been shown the
circuit using XOR/XNOR, one inverter, and multiplexer, as
showing in fig.3. Therefore, the circuit provides full output
voltage-swing at all nodes. In this article, the author also new
introduced 14T F-A circuit design, is showing in fig.4.The
circuit is designed by the cross-coupled pMOS and
complementary cross-coupled nMOS. These reasons for that
XOR circuit are realized using a feedback structure
containing two MOSFETs that needs to be rationed properly.
This F-A do not provide an output signal for A=B=1 and
A=B=0, respectively, which is provided by the reaction path
from MP and MN transistor marked with asterisks (*) in fig.
4.
Fig.3. 16T- full-adder [3].
Fig.4. 14T-full-adder [3].
Shivani et al.[4], to design 9T full-adder using an XNOR-
XOR circuit as showing in fig.5 and compared with the other
F-A (16T,14T) demonstrate the supremacy of low power,
energy. According to the author, sacrificing the transistor
count by one and increase the performance of previous 8T F-
A, while to achieve the best power-consumption at the cost of
negligible-area.
Sandeep et al [5], to design a higher performance full-adder
using an XOR-XNOR circuit as showing in fig.6 and also
show the increase the performance against previous F-A up
to 98%, delay and power-delay-product.
Fig.5 9T-full-adder [4].
Fig.6 9T-full-adder [5].

III- Proposed Circuits and expression
(A)
Proposed XNOR-XOR circuit logic expression and
truth table.
Redesigned an XNOR-XOR circuit. These entire designs are
implemented by the pass transistors logic. The proposed
XNOR-XOR circuit is showing in fig. 7. However, this
XNOR-XOR circuit gives very bad high output logic for the
certain input combination. These problems could be solved
by manipulates the width-length ratio of MP1 and MN1
transistors (fig.2), which restores the acceptable output.
Proposed circuit XNOR-XOR circuit waveform as showing
in fig. 9.The XNOR-XOR circuit assortment is showing in
tabulated 1 and notified by the logic
:
. The logic
expressions for proposed circuitry are:
''ABABAB=+
:
(1)
''
ABAB AB⊕= +
(2)
()
()
()
()
ABAB
ABAB
AA AB AB BB
=+ +
=+ +
=+++
ABABAB⊕= +
Table I. XNOR/XOR Gate Function
Fig.7. Newly XNOR-XOR circuit.
(
B) Proposed Full-adders Logic Equations
We are showing the mathematical expression which lead to
the proposed F-A cells using proposed XNOR-XOR circuit
could be follows: addition three inputs, which calculate the
outputs Sum and Carry:
Sum A B Cin=⊕:
(3)
Carry A B ACin=⊕+
(4)
The proposed F-A circuit consisting of two modules; one is
XNOR-XOR circuit and other multiplexers. The equations
(3) & (4) above, XNOR- XOR circuit are the essential parts
of F-A and to provide the 4T XNOR-XOR circuit to increase
the performance of existing F-A. The major role in currently
new designed an F-A circuit using XNOR-XOR circuit to
detract the power-dissipation of the existing F-A. Waveform
of proposed F-A is showing in fig.10.
Fig.8 New introduce full-adder using XNOR-XOR .
IV-Simulation results
In this seminal, compared the display of five various types of
full-adders, named: 16T [3], 14T [3], 9T [4], 9T [5]. All the
schematics an F-A have been analysis and simulation using
90n model parameter. To evaluates the power dissipation,
delay, and PDP. To compare, we have taken the transistors
size for each full-adder circuit, which were discuss in the
corresponding papers.
The working of proposed circuit summarized to the below
table 2.
In Table 3, shows simulation outcomes of a proposed circuit
and existing F-A circuit performance comparison power-
dissipation, delay, and PDP. All the design simulation
outcomes were given by supplied with 5 V and frequency for
the inputs was 100 MHz. It is assumed that in few cases,
power-dissipation less than total average power for the F-A
circuit. Because of this, few logic styles (PTL, XNOR-XOR
circuit) are retrieved from the input full-adder and used to
charge internal nodes.

Table-3: Compare the results of F-A (PDP in pw*ns.)
Proposed waveform XNOR-XOR circuit and proposed F-A
are showing in fig. 9 & fig .10, while plots of the power-
consumed by an F-A cells over time are showing in fig. 11.
Table-4: Comparison of power-consumption bit wise
proposed and existing F-A.


Fig.9. Proposed XNOR XOR circuit waveform.

Fig.10.Proposed full-adder using XNOR-XOR Circuit waveform.

Fig.11. Power-Consumption of all full- adder.
Conclusion
An all including performance, analysis, and simulation have
been presented in the terms of tabulated form. The proposed
full- adder circuit design 8T are derived from the different
algorithm based proposed XNOR-XOR circuit. All the
simulation outcomes using 90nm model parameter.
Demonstrate that the simulation outcomes of proposed
circuitry and existing various full adder have in points of the
power-consumption, delay and PDP using TSPICE.
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