Three Dimensional Integrated Circuit Design: EDA, Design and Microarchitectures
Abstract
This book presents an overview of the field of 3D IC design, with an
emphasis on electronic design automation (EDA) tools and algorithms
that can enable the adoption of 3D ICs, and the architectural
implementation and potential for future 3D system design. The aim of
this book is to provide the reader with a complete understanding of:
• the promise of 3D ICs in building novel systems that enable the chip
industry to continue along the path of performance scaling,
• the state of the art in fabrication technologies for 3D integration,
• the most prominent 3D-specific EDA challenges, along with solutions
and best practices,
• the architectural benefits of using 3D technology,
• architectural-and system-level design issues, and
• the cost implications of 3D IC design.
Three Dimensional Integrated Circuit Design: EDA, Design and Microarchitectures is intended for practitioners in the field, researchers and graduate students seeking to know more about 3D IC design.
Chapters (10)
Much as the development of steel girders suddenly freed skyscrapers to reach beyond the 12-story limit of masonry buildings 6, achievements in four key processes have allowed the concept of 3D integrated circuits 2, proposed more than 20 years ago by visionaries (such as Jim Meindl in the United States and Mitsumasa Koyanagi in Japan), to actually begin to become realized. These factors are (1) low-temperature bonding, (2) layer-to-layer transfer and alignment, (3) electrical connectivity between layers, and (4) an effective release process. These are the cranes which will assemble our new electronic skyscrapers. As these emerged, the contemporary motivation to create such an unusual electronic structure remained unresolved. That argument finally appeared in a casual magazine article that certainly was not immediately recognized for the prescience it offered 5.
Both form-factor and performance-scaling trends are driving the need for 3D integration, which is now seeing rapid commercialization.
While overall process integration schemes are not yet standardized across the industry, it is now important for 3D circuit
designers to understand the process trends and tradeoffs that underlie 3D technology. In this chapter, we outline the basic
process considerations that designers need to be aware of: strata orientation, inter-strata alignment, bonding-interface design,
TSV dimensions, and integration with CMOS processing. These considerations all have direct implications on design and will
be important in both the selection of 3D processes and the optimization of circuits within a given 3D process.
![Fig. 3.8 ( a ) Simplified PSN models for comparing impedance response in 2D and 3D. ( b ) Impedance response comparison between 2D and 3D. ( c ) Impedance response of the three tiers in a 3D IC [20] © IEEE 2007](https://www.researchgate.net/profile/Pingqiang-Zhou/publication/226225629/figure/fig5/AS:302321708879873@1449090520077/a-Simplified-PSN-models-for-comparing-impedance-response-in-2D-and-3D-b_Q320.jpg)
![Fig. 3.9 Insertion of a DC–DC converter near the load [37]. © 2004 IEEE](https://www.researchgate.net/profile/Pingqiang-Zhou/publication/226225629/figure/fig6/AS:302321708879874@1449090520102/Insertion-of-a-DC-DC-converter-near-the-load-37-C-2004-IEEE_Q320.jpg)
Compared to their 2D counterparts, 3D integrated circuits provide the potential for tremendously increased levels of integration
per unit footprint. While this property is attractive for many applications, it also creates more stringent design bottlenecks
in the areas of thermal management and power delivery. First, due to increased integration, the amount of heat per unit footprint
increases, resulting in the potential for higher on-chip temperatures. The task of thermal management must necessarily be
shared both by the heat sink, which transfers internally generated heat to the ambient, and by using thermally conscious design
methods. Second, the power to be delivered to a 3D chip, per package pin, is tremendously increased, leading to significant
complications in the task of reliable power delivery. This chapter presents an overview of both of these problems and outlines
solution schemes to overcome the corresponding bottlenecks.
Three-dimensional integration makes floorplanning a much more difficult problem because the multiple device layers dramatically
enlarge the solution space and the increased power density accentuates the thermal problem. This chapter introduces the algorithms
for 3D floorplanning with both 2D blocks and 3D blocks. In addition to stochastic optimizations based on various representations
that are briefly introduced, the analytical approach is also introduced. The effects of various 3D floorplanning techniques
on wirelength, area, and temperature are demonstrated by experimental results.
Three-dimensional IC technology enables an additional dimension of freedom for circuit design. Challenges arise for placement
tools to handle the through-silicon via (TS via) resource and the thermal problem, in addition to the optimization of device
layer assignment of cells for better wirelength. This chapter introduces several 3D global placement techniques to address
these issues, including partitioning-based techniques, quadratic uniformity modeling techniques, multilevel placement techniques,
and transformation-based techniques. The legalization and detailed placement problems for 3D IC designs are also briefly introduced.
The effects of various 3D placement techniques on wirelength, TS via number, and temperature, and the impact of 3D IC technology
to wirelength and repeater usage are demonstrated by experimental results.
Thermal challenges in 3D chips motivate the need for on-chip thermal conduction networks to deliver the heat to the heat sink.
The most prominent example is a passive network of thermal vias, which serves the function of heat conduction without necessarily
serving any electrical function. This chapter begins with an overview of techniques for thermal via insertion. Next, it addresses
the problem of 3D routing, overcoming challenges as conventional 2D routing is stretched to a third dimension and as electrical
routes must vie with thermal vias for scarce on-chip routing resources, particularly intertier vias.
Three-dimensional integration provides many new exciting opportunities for computer architects. There are many potential ways
to apply 3D technology to the design and implementation of microprocessors. In this chapter, we discuss a range of approaches
from simple rearrangements of traditional 2D components all the way down to very fine-grained partitioning of individual processor
functional unit blocks across multiple layers. This chapter also discusses different techniques and trade-offs for situations
where die-to-die communication resources are constrained and what the computer architect can do to alter a design deal with
this. Three dimensional integration provides many ways to reduce or eliminate wires within the microprocessor, and this chapter
also discusses high-level design styles for converting the wire reduction into performance or power benefits.
On-chip interconnects are predicted to be a fundamental issue in designing multi-core chip multiprocessors (CMPs) and system-on-chip
(SoC) architectures with numerous homogeneous and heterogeneous cores and functional blocks. To mitigate the interconnect
crisis, one promising option is network-on-chip (NoC), where a general purpose on-chip interconnection network replaces the
traditional design-specific global on-chip wiring by using switching fabrics or routers to connect IP cores or processing
elements. Such packet-based communication networks have been gaining wide acceptance due to their scalability and have been
proposed for future CMPs and SoC design. In this chapter, we study the combination of both three-dimensional integrated circuits
and NoCs, since both are proposed as solutions to mitigate the interconnect scaling challenges. This chapter will start with
a brief introduction on network-on-chip architecture and then discuss design space exploration for various network topologies
in 3D NoC design, as well as different techniques on 3D on-chip router design. Finally, it describes a design example of using
3D NoC with memory stacked on multi-core CMPs.
![Fig. 9.1 IDC estimates for annual cost spent (1) power and cooling servers and (2) purchasing additional servers [52]](https://www.researchgate.net/profile/Trevor-Mudge/publication/225832636/figure/fig3/AS:667828298457090@1536234082247/IDC-estimates-for-annual-cost-spent-1-power-and-cooling-servers-and-2-purchasing_Q320.jpg)
With power and cooling increasingly contributing to the operating costs of a datacenter, energy efficiency is the key driver
in server design. One way to improve energy efficiency is to implement innovative interconnect technologies such as 3D stacking.
Three-dimensional stacking technology introduces new opportunities for future servers to become low power, compact, and possibly
mobile. This chapter introduces an architecture called Picoserver that employs 3D technology to bond one die containing several
simple slow processing cores with multiple memory dies sufficient for a primary memory. The multiple memory dies are composed
of DRAM. This use of 3D stacks readily facilitates wide low-latency buses between processors and memory. These remove the
need for an L2 cache allowing its area to be re-allocated to additional simple cores. The additional cores allow the clock
frequency to be lowered without impairing throughput. Lower clock frequency means that thermal constraints, a concern with
3D stacking, are easily satisfied. PicoServer is intentionally simple, requiring only the simplest form of 3D technology where
die are stacked on top of one another. Our intent is to minimize risk of introducing a new technology (3D) to implement a
class of low-cost, low-power, compact server architectures.
The majority of the existing 3D IC research has focused on how to take advantage of the performance, power, smaller form-factor,
and heterogeneous integration benefits offered by 3D integration. However, all such advantages will ultimately have to be
translatee into cost savings when a design strategy has to be decided. Consequently, system-level cost analysis at the early
design stage is imperative to help the decision making on whether 3D integration should be adopted. In this chapter, we discuss
the design estimation method for 3D ICs at the early design stage. We also describe a cost analysis model to study the cost
implication for 3D ICs and address cost-related problems for 3D IC design.
... Scaling trend reduces the size of transistors and improves the performance of individual devices while reducing the power consumed by the devices. For a period of time, moore s law successfully motivated the electronic world to scale down the 1 Chapter 1. Introduction transistor size and increase the transistor density in integrated circuits as shown in Figure 1.1 [27]. ...
... Limitation in manufacturing technologies and materials makes the scaling of the feature size extremely difficult and expensive for deep sub-micron devices [28]. Certain device parameters like gate oxide thickness cannot be reduced anymore which results in high leakage and parasitics for extremely scaled devices [27,29]. Due to these continuing problems, increasing the operating frequency of the devices leads to high power consumption and uncontrollable thermal problems. ...
... As mentioned before interconnect delay becomes an important part of circuit delay in recent circuits and reducing interconnect delay can enhance the performance of the circuit. Moreover a considerable amount of power is dissipated in global interconnects which can be reduced by using shorter wire-lengths [27,28]. Shorter interconnects also improve the routing congestion which can subsequently reduce the number of metal layers used for routing each layer of 3-D circuits. ...
Three-dimensional (3-D) or vertical integration is a design and packaging paradigm that can mitigate many of the increasing challenges related to the design of modern integrated systems. 3-D circuits have recently been at the spotlight, since these circuits provide a potent approach to enhance the performance and integrate diverse functions within amulti-plane stack. Clock networks consume a great portion of the power dissipated in a circuit. Therefore, designing a low-power clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Synchronization issues can be more challenging for 3-D circuits since a clock path can spread across several planes with different physical and electrical characteristics. Consequently, designing low power clock networks for 3-D circuits is an important issue. Resonant clock networks are considered efficient low-power alternatives to conventional clock distribution schemes. These networks utilize additional inductive circuits to reduce power while delivering a full swing clock signal to the sink nodes. In this research, a design method to apply resonant clocking to synthesized clock trees is proposed. Manufacturing processes for 3-D circuits include some additional steps as compared to standard CMOS processes which makes 3-D circuits more susceptible to manufacturing defects and lowers the overall yield of the bonded 3-D stack. Testing is another complicated task for 3-D ICs, where pre-bond test is a prerequisite. Pre-bond testability, in turn, presents new challenges to 3-D clock network design primarily due to the incomplete clock distribution networks prior to the bonding of the planes. A design methodology of resonant 3-D clock networks that support wireless pre-bond testing is introduced. To efficiently address this issue, inductive links are exploited to wirelessly transmit the clock signal to the disjoint resonant clock networks. The inductors comprising the LC tanks are used as the receiver circuit for the links, essentially eliminating the need for additional circuits and/or interconnect resources during pre-bond test. Recent FPGAs are quite complex circuits which provide reconfigurablity at the cost of lower performance and higher power consumption as compared to ASIC circuits. Exploiting a large number of programmable switches, routing structures are mainly responsible for performance degradation in FPAGs. Employing 3-D technology can providemore efficient switches which drastically improve the performance and reduce the power consumption of the FPGA. RRAM switches are one of the most promising candidates to improve the FPGA routing architecture thanks to their low on-resistance and non-volatility. Along with the configurable switches, buffers are the other important element of the FPGAs routing structure. Different characteristics of RRAM switches change the properties of signal paths in RRAM-based FPGAs. The on resistance of RRAMswitches is considerably lower than CMOS pass gate switches which results in lower RC delay for RRAM-based routing paths. This different nature in critical path and signal delay in turn affect the need for intermediate buffers. Thus the buffer allocation should be reconsidered. In the last part of this research, the effect of intermediate buffers on signal propagation delay is studied and a modified buffer allocation scheme for RRAM-based FPGA routing path is proposed.
... Three-dimensional integrated circuit (3D IC) technology is a prominent answer to this problem [2]. It offers 'more-Moore' and 'more-than-Moore' in addition to improvement in total wire length, chip reliability, and performance [3]. However, the design complexity of 3D ICs has increased exponentially in comparison with 2D IC [4]. ...
... The dielectric material is filled between two different layers. The connection between different layers is made by TSV [3]. Metal layers are present between the device layer of each die and interlayer dielectric material. ...
... Three-dimensional integrated circuit (3D IC) technology is a prominent answer to this problem [2]. It offers 'more-Moore' and 'more-than-Moore' in addition to improvement in total wire length, chip reliability, and performance [3]. However, the design complexity of 3D ICs has increased exponentially in comparison with 2D IC [4]. ...
... The dielectric material is filled between two different layers. The connection between different layers is made by TSV [3]. Metal layers are present between the device layer of each die and interlayer dielectric material. ...
In this study, a new tier partitioning algorithm for three‐dimensional integrated circuits (3D ICs) using a genetic algorithm (GA) is presented. Design parameters for the proposed 3D IC partitioning method are average layer power density and number of through‐silicon vias (TSVs) subject to fixed‐outline constraint. The GA with newly introduced crossover and mutation operation, termed as even crossover and complement mutation, is employed for optimisation of design variables. Experimental results exhibit that the authors proposed method reduces the average number of TSVs by 45.75 and 44.68%, as compared to taboo search and simulated annealing‐based 3D partitioning methods. It also reduces the average number of TSVs, maximum power density among the layers and average layer area by 28.34, 40.29, and 27.85%, respectively, as compared to thermal‐aware 3D partitioning technique. The results of their proposed algorithm demonstrate the efficiency and effectiveness in tier partitioning for 3D ICs over existing methods.
... Network-on-chip (NoC) has gained large attention as a scalable communication solution for multi-and many-core chips.NoC paradigm obviates on-chip communication problems such as performance limitations that were formerly caused by long interconnects [1], [2]. Although planar NoCs were used for more than a decade as a communication mean for connecting on-chip cores, they lost their applicability when more and more number of cores were to be integrated onto a chip to achieve tera and peta scale performance needed for modern applications [3]. Three dimensional integration has recently enabled hosting hundreds of cores in stacked layers of 3D chips [4], [5] so, 3D NoCs popped up. ...
... Two sub-figures show a mesh-based 3D network with XY dimension of 5×8. In the sub-figures, source, destination and elevator nodes are located in (1,1,5), (1,2,4), (3,5,5) respectively. Congested links are marked by solid rectangles. ...
... 3D integration of semiconductor chips [1][2][3] is a very promising technology because it offers many advantages: ...
... Currently, the chip is thinned usually to the thickness of several dozen micrometers, but the accurate thickness may vary in different technological processes. Various silicon layer thicknesses in 3D ICs have been analyzed in literature [2], here we assumed a thickness of 60 µm. ...
Integrated liquid cooling is a promising idea for future 3D integrated circuits and potentially a scalable solution for ever-increasing power dissipation. In this paper, we analyze the efficiency of heat removal from a 3D stacked chip with microchannels. We build a detailed chip model and perform a coupled thermo-fluidic finite element method simulation for various microchannel designs. We explore the design space and point out the correlations between various chip and cooling parameters. In particular, we show that with ten microchannels of size 500 µm × 70 µm it is possible to remove 100 W of heat from a two-tier 3D chip while maintaining the temperature below 90°C and the pressure drop below 50 kPa.
... As the number of cores on a chip grows, the complexity of their interactions grows exponentially. Network-on-chip (NoC) [1][2][3] is one promising method for overcoming these restrictions. Moreover, the paradigm of three-dimensional (3D) integration is the most straightforward answer to most of the 2D integration vexing problems. ...
INTRODUCTION
The 3D integrated circuit technology, which smooths out the massive increase in transistors on a chip by stacking numerous silicon layers vertically, is quickly becoming a revolutionary technology. Thermal issues are more relevant for 3D Network-on-Chip (NoC) systems than their 2D counterparts.
METHOD
This paper presents a novel Vertically-Partially-Connected 3D-Network on-chip architecture that reduces the total length of interconnects and reduces the number of 3D routers. We also present an efficient XYZ routing technique for thermal management. The proposed algorithm distributes traffic based on the number of layers and congestion to achieve chip heat balancing, avoid high peak temperatures, improve average packet latency, and extending chip service life.
RESULT
Simulation results showed that the routing technique reduces the peak temperature of the chip by an average of 17 C° compared to the exiting routing algorithms, with minimized negative impact on performance
CONCLUSION
Furthermore, the Vertically-Partially-Connected 3D-Network on-chip implemented in this study using VHDL exhibits improved area occupation by reducing the number of employed LUT in the FPGA compared to previous works.
... With the advance in the semiconductor technology, the Network-on-Chip (NoC) as an efficient solution for multi-core chips has attracted wide attention [1,2]. In recent years, the 3D network-on-Chip is proposing to cope with the complicated on-chip interconnection issues by applying die stacking technology [3]. ...
Due to the stacking dies and unequal cooling effiency of different layers, 3D NoC-based systems suffer sever thermal issues. Adaptive routing can alleviate the thermal issues, but current routing algorithms either suffer from the thermal balance or traffic congestion. This paper proposed a collaborative thermal- and traffic-aware adaptive routing (CTTAR) scheme, which considers the traffic and temperature information together and avoids the packets transferring to congested region. Experiments show that, there is 19.4% to 48.4% system performance improvement compared with other routing algorithms under the same thermal limit.
... As shown in Figure 11, if there were no thermal constraint, the temperature would exceed 80°C. The baseline strategy throttles at 80°C until it cools down to 76.4°C in a few milliseconds (time constant similar to prior works [2,10,27,28,49]). However, TAM and FC can reduce leakage and dynamic power; hence, they eliminate thermal stalls and are able to maintain the temperature in the range of 76-79.4°C. ...
3D memory systems offer several advantages in terms of area, bandwidth, and energy efficiency. However, thermal issues arising out of higher power densities have limited their widespread use. While prior works have looked at reducing dynamic power through reduced memory accesses, in these memories, both leakage and dynamic power consumption are comparable. Furthermore, as the temperature rises, the leakage power increases, creating a thermal-leakage loop. We study the impact of leakage power on 3D memory temperature and propose turning OFF specific memory channels to meet thermal constraints. Data is migrated to a 2D memory before closing a 3D channel. We introduce an analytical model to assess the 2D memory delay and use the model to guide data migration decisions. The above strategy is referred to as FastCool and provides an improvement of 22%, 19%, and 32% on average (up to 57%, 72%, and 82%) in performance, memory energy, and energy-delay product (EDP), respectively, on different workloads consisting of SPEC CPU2006 benchmarks.
We further propose a thermal management strategy named Energy-Efficient FastCool (EEFC) , which improves upon FastCool by selecting the channels to be closed by considering temperature, leakage, access rate, and position of various 3D memory channels at runtime. Our experiments demonstrate that EEFC leads to an additional improvement of up to 30%, 30%, and 51% in performance, memory energy, and EDP compared to FastCool. Finally, we analyze the effects of process variations on the efficiency of the proposed FC and EEFC strategies. Variation in the manufacturing process causes changes in the leakage power and temperature profile. Since EEFC considers both while selecting channels for closure, it is more resilient to process variations and achieves a lower application execution time and memory energy compared to FastCool.
... where is the single gate area and is the total number of gates. Based on industrial empirical data, is estimated to be 3, 125 2 , where is the half feature size of the technology node [12]. When these 2-D dies are partitioned and bonded for 3-D integration, an overhead in silicon area is added by the TSVs. ...
Contactless three-dimensional (3-D) interconnects have been proposed as an alternative to through-silicon via (TSV) due to its manufacturing compatibility with two-dimensional (2-D) processes. Typically , contactless 3-D circuits are thought to require considerable silicon resources compared to TSV. However, recent manufacturing options, such as extreme wafer thinning, provide new opportunities for this approach. This paper, therefore, explores these opportunities for producing 3-D systems of lower cost. The presented cost analysis and models usefully combine fabrication cost with performance requirements for inter-tier communication as a critical component of 3-D systems. Thus, benchmark circuits are simulated for a two-tier system using a commercial 65 nm technology and communicating at a data rate of 1 Gbps per link, although the model is directly applicable to any technology or design specifications. Interestingly, inductive links can be a useful alternative to TSV for specific and expected manufacturing capabilities. Furthermore, the effectiveness of different multiplexing schemes and their effect on system cost is also evaluated. CCS CONCEPTS • Hardware → 3D integrated circuits; Radio frequency and wireless interconnect.
... The technologies which enable vertically stacked integrated circuits develop very rapidly [1][2][3], which indicates that in the next several years first 3D processors may be produced. Consider for example an octa-core processor i7-5960X (see Fig. 1) from Intel [4], which has the power budget of 140 W and 17.6 mm x 20.2 mm die size. ...
... In this methodology, separate dies are fabricated using standard lithography, TSVs are added (during or after lithography), individual dies or wafers are thinned, and 3D stacks are formed through alignment and bonding. Over the last two decades, many improvements have been made in the process technology, design automation, and system architecture for these 3D circuits[4,5]. Die-die interconnects with pitches from 1-40 µm[6,7]provide high-bandwidth, minimal latency connections and can reduce total wirelength. ...
Existing works on Three-dimensional (3D) hardware security focus on leveraging the unique 3D characteristics to address the supply chain attacks that exist in 2D design. However, 3D ICs introduce specific and unexplored challenges as well as new opportunities for managing hardware security. In this paper, we analyze new security threats unique to 3D ICs. The corresponding attack models are summarized for future research. Furthermore, existing representative countermeasures, including split manufacturing, camouflaging, transistor locking, techniques against thermal signal based side-channel attacks, and network-on-chip based shielding plane (NoCSIP) for different hardware threats are reviewed and categorized. Moreover, preliminary countermeasures are proposed to thwart TSV-based hardware Trojan insertion attacks.
... 3D integration of electronic circuits [1][2][3] is rapidly gaining interest among researchers and manufacturers due to its many advantages, most importantly due to the possibility of integrating various technologies on a single chip and increasing the number of transistors in the same chip footprint (Fig. 1). One of the most important problems of these 3D architectures is high dissipated power density and high temperature, which adversely affects chip reliability and reduces its lifetime. ...
Liquid cooling with microchannels is a very attractive idea for 3D ICs which could help solving the problem of ever-increasing power dissipation due to its good cooling efficiency and potential scalability. However, this cooling method has some very different properties compared to the well-understood forced air convection. In particular, its cooling efficiency with respect to power variations in the chip is still not completely analyzed. Therefore, in this paper a thorough study of microchannel cooling efficiency as a function of intra- and interlayer power consumption variability is presented. We use a finite element method analysis to run a coupled thermo-fluidic simulation of a dedicated 3D chip model. An analytical analysis is also provided which calculates analytically the optimal power density profile along the channel. Then, steps necessary for finding the optimal power distribution for chip units are proposed. It is also shown that by appropriately managing the power density according to the proposed methodology, it is possible to significantly reduce the peak chip temperature. In particular, for a 3D chip including Intel's i7-6950X 10-core processor, a temperature reduction of 8.9 °C was achieved by a proper orientation of microchannels and another 5.8 °C reduction was obtained by optimally distributing power consumption between processor cores.
... TSV-based 3D IC: To avoid the vulnerabilities of SiP, a Through-Silicon Via (TSV) 3D process can be employed to tightly integrate the functional and protective layers. Dies are thinned down to 20 um and connected physically and electrically with TSVs [24]. Closer proximity of the security layers increases the difficulty of layer removal and reduces any thermal differential between layers. ...
... Thus, the performance of a 3D-NoC-based system depends on a proper placement of these limited number of TSVs. Other router design strategies for 3D-NoCs, such as hybrid and complete 3D fabric may not be suitable because of communication contention, scalability, and complex design issues [Xie et al. 2009]. In contrast, the present work is based on a partially connected symmetric 3D-mesh-based NoC topology. ...
This article proposes a solution to the integrated problem of Through-Silicon Via (TSV) placement and mapping of cores to the routers in a three-dimensional mesh-based Network-on-Chip (NoC) system. TSV geometry restricts their number in three-dimensional (3D) ICs. As a result, only about 25% of routers in a 3D NoC can possess vertical connections. Mapping plays an important role in evolving good system solutions in such a situation. TSVs have been placed with detailed consultation with the application mapping process. The integrated problem was first solved using the exact method of Integer Liner Programming (ILP). Next, a solution was obtained via a Particle Swarm Optimization (PSO) formulation. Several augmentations to the basic PSO strategy have been proposed to generate good-quality solutions. The results obtained are better than many of the contemporary approaches and close to the theoretical situation in which all routers are 3D in nature.
... 3D integration of electronic circuits [1][2][3] is rapidly gaining interest among researchers and manufacturers due to its many advantages, most importantly due to the possibility of integrating various technologies on a single chip and increasing the number of transistors in the same chip footprint (Fig. 1). One of the most important problems of these 3D architectures is high dissipated power density and high temperature, which adversely affects chip reliability and reduces its lifetime. ...
Multicore chips are commonly seen as the solution to maintain the exponential increase of chips processing power observed over several decades. Unfortunately, regarding homogeneous multicore chips, this vision is not so evident because the evolution toward ever more cores exacerbates several complex issues at different abstraction levels which, by adding up, make the challenge very difficult. The first barrier is architectural: Almost all current architectures are with uniform memory access and consequently not scalable to hundreds of cores. This forces to move to non-uniform memory access architectures and induces a difficult challenge to programmers who have to allocate the resources (processing and memory) contrarily to decades of practice. The second barrier is with the massive parallelization of code, especially with the generation of seamless, efficient and automatic parallelization tools. Two additional barriers are related to the reduction of the dimensions to the nanometer scale. The heat dissipation barrier results from the rise of the total dissipated power of chips and in the increased temperature of hot spots. Finally, the dependability barrier comes from the increasing percentage of undetected manufacturing defects, forcing the circuit design to evolve towards self-immune building blocks. The paper provides a cross-disciplinary description of the mentioned challenges.
... Compared T with T , it is obvious that T < T. To prove our view, in the following simulation, we assume that the through-cache TSVs are made of copper, which appears to be a nearly optimal choice. Because many organizations have fabricated TSVs with dif- ferent pitches ranging from several microns up to tens of microns [17] , in this paper we assume a moderate TSV whose dimensions and RC data is given in Table 1 . The resistance of unit of alu- minum interconnect is 0.075 / μm, and the capacitance of unit of aluminum interconnect is 110 af/ μm. ...
... Recent work on the energy complexity of good decoding has focused largely on planar circuits. However, circuits implemented in three-dimensions exist [6], and so we generalize the recent information friction (or bit-meters) model introduced by Grover in [3] to circuits implemented in three-dimensions and extend the technique of Grover to show that, in terms of block length n, a bit-meters coding scheme in which block error probability is given by P e (n) has encoding/decoding energy that scales as Ω n (ln P e (n)) 1 3 . We show how this approach can be generalized to an arbitrary number of dimensions. ...
Using the Thompson circuit complexity model, it is shown that fully parallel encoding and decoding schemes with asymptotic block error probability that scales as O( f (n)) have energy that scales as Ω(n- ln f (n)
<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1/2</sup>
). In addition, it is shown that the number of clock cycles [T(n)] required for any encoding or decoding scheme that reaches this bound must scale as T(n) ≥ - ln f (n)
<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1/2</sup>
. Similar scaling results are extended to serialized computation. A similar approach is extended to three dimensions by generalizing the Grover information-friction energy model. Within this model, it is shown that encoding and decoding schemes with probability of block error Pe(n) consume at least Ω(n(- ln Pe(n))
<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">(1/3)</sup>
) energy.
... The most intuitive way to implement a 3D NoC is to simply stack 2D Mesh NoCs and utilize TSVs to connect vertically adjacent routers. Despite its simplicity, such 3D symmetric NoC is not taking advantage of the negligible inter-layer TSV delay [10]. To reduce the TSV amount, Hwang et al. [11] propose to connect only a few number of TSV routers to the vertical link, while the rest just connect with routers on the same silicon layer. ...
... Moreover, we assume that to build the 3D IC, chip thinning technique [16] was applied to chip layers and therefore their thickness was reduced to 150 µm. For joining chip layers, we assume here a Cu-adhesive bonding [17] (transfer-join assembly). It should then be emphasized that the results presented in this paper may not apply to 3D ICs which use other types of bonding, e.g. ...
In modern integrated circuits, manufactured in nanometer technologies, reducing the hotspot temperature even by several degrees may lead to significant advantages. In particular, in high performance processors, lower temperature translates into fewer reliability concerns, lower cooling costs, the possibility of increasing the operating frequency and extending the device׳s lifetime. Therefore, in this paper we investigate how the positioning of particular processor units in the floorplan (i.e. floorplanning) affects the chip temperatures. We take into consideration 8-and 6-core processors manufactured in 14 nm technology and simulate the temperature distribution for various floorplan designs. It is shown that the difference in maximal temperature for various floorplans can reach even 7.2 K for a typical case. Moreover, the idea for thermal buffers is presented. While it is shown that thermal buffers may not be of great significance in 2D integrated circuits, obtained results indicate that in 3D ICs the combination of thermal buffers and vertical thermal vias may considerably reduce the temperature of the hottest areas.
... Various representations for 3D floorplanning with 3D blocks[53] ...
The physical design process for 3D ICs is similar to that used for the traditional 2D physical design, in a sense that it transforms the circuit representation from a netlist into a geometric representation by the steps of floorplanning, placement, and-routing. While the multiple-layer metals have already had 3D structure in-traditional ICs for interconnects, the 3D IC technologies allow multiple layers of logical devices to be integrated in the third dimension by bonding stacks of multiple "tiers" to form 3D chips. Each tier, which is similar to a traditional 2D IC, consists of one silicon layer and several metal layers, and different tiers are connected by through-silicon vias (TS via).
... Furthermore, Nicopoulos et al. [2] evaluated the issues of NoC from system and micro architectural points of view. With the emerging of third dimension in NoC as a viable solution, Sheibanyrad et al. [24], Tan et al. [25], Vasilis et al. [39], Xie et al. [40], and Papanikolaou et al. [41] introduce the concepts, principles, and challenges of 3D NoC-based SoC. In following, the most related studies about the 3D technology and NoC integration and its advantages compared to 2D NoC will be explained: ...
Utilization of the third dimension can lead to a significant reduction in power and average hop-count in Networks- on-Chip (NoC). TSV technology, as the most promising technology in 3D integration, offers short and fast vertical links which copes with the long wire problem in 2D NoCs. Nonetheless, TSVs are huge and their manufacturing process is still immature, which reduces the yield of 3D NoC based SoC. Therefore, Vertically-Partially-Connected 3D-NoC has been introduced to benefit from both 3D technology and high yield. Moreover, Vertically-Partially-Connected 3D-NoC is flexible, due to the fact that the number, placement, and assignment of the vertical links in each layer can be decided based on the limitations and requirements of the design. However, there are challenges to present a feasible and high-performance Vertically-Partially-Connected Mesh-based 3D-NoC due to the removed vertical links between the layers. This thesis addresses the challenges of Vertically-Partially-Connected Mesh-based 3D-NoC: Routing is the major problem of the Vertically-Partially-Connected 3D-NoC. Since some vertical links are removed, some of the routers do not have up or/and down ports. Therefore, there should be a path to send a packet to upper or lower layer which obviously has to be determined by a routing algorithm. The suggested paths should not cause deadlock through the network. To cope with this problem we explain and evaluate a deadlock- and livelock-free routing algorithm called Elevator First. Fundamentally, the NoC performance is affected by both 1) micro-architecture of routers and 2) architecture of interconnection. The router architecture has a significant effect on the performance of NoC, as it is a part of transportation delay. Therefore, the simplicity and efficiency of the design of NoC router micro architecture are the critical issues, especially in Vertically-Partially-Connected 3D-NoC which has already suffered from high average latency due to some removed vertical links. Therefore, we present the design and implementation the micro-architecture of a router which not only exactly and quickly transfers the packets based on the Elevator First routing algorithm, but it also consumes a reasonable amount of area and power. From the architecture point of view, the number and placement of vertical links have a key role in the performance of the Vertically-Partially-Connected Mesh-based 3D-NoC, since they affect the average hop-count and link and buffer utilization in the network. Furthermore, the assignment of the vertical links to the routers which do not have up or/and down port(s) is an important issue which influences the performance of the 3D routers. Therefore, the architectural exploration of Vertically-Partially-Connected Mesh-based 3D-NoC is both important and non-trivial. We define, study, and evaluate the parameters which describe the behavior of the network. The parameters can be helpful to place and assign the vertical links in the layers effectively. Finally, we propose a quadratic-based estimation method to anticipate the saturation threshold of the network's average latency.
In order to meet the requirements of high performance, miniaturization, low cost, low power consumption and multi-function, three-dimensional (3D) integrated technology has gradually become a core technology. With the development of 3D integrated technology, it has been used in imaging sensors, optical integrated microsystems, inertial sensor microsystems, radio-frequency microsystems, biological microsystems and logic microsystems, etc. Through silicon via (TSV) is the core technology of a 3D integrated system, which can achieve vertical interconnection between stacked chips. In this paper, the development and progress of multi-physics simulation design for TSV-based 3D integrated systems are reviewed. Firstly, the electrical simulation design of TSV in a 3D integrated system is presented, including the lumped parameters model-based design and numerical computation model-based design. Secondly, the thermal simulation design of TSV in a 3D integrated system is presented based on the analytical model or numerical computation model. Thirdly, the multi-physics co-simulation design of TSV in a 3D integrated system is presented, including the thermal stress and electron thermal coupling simulation design. Finally, this paper is concluded, and the future perspectives of 3D integrated systems are presented, including the advanced integrated microsystems, the crossed and reconfigurable architecture design technology and the standardized and intelligent design technology.
This paper presents a compact thermal model for smartphones, Phone‐nomenon 2.0, to predict the thermal behavior of smartphones. In the beginning, non‐linearities of internal and external heat transfer mechanisms of smartphones and a compact thermal model for these non‐linearities have been studied and proposed. Then, an iterative simulation procedure to handle these non‐linearities was developed, and the basic simulation framework which is one option in Phone‐nomenon 2.0 was established and we call it Phone‐nomenon.Iter. Finally, the linearisation approach was applied, and model order reduction techniques to enhance and speed up the basic framework were employed, and these two options Phone‐nomenon.Lin and Phone‐nomenon.LinMOR were named. Compared with a commercial tool, ANSYS Icepak, Phone‐nomenon.Iter can achieve two orders of magnitude speedup with the maximum error being less than 1.90% for steady‐state simulations and three orders of magnitude speedup with the temperature difference being less than 0.65°C for transient simulations. In addition, the speedup of Phone‐nomenon.Lin over Phone‐nomenon.Iter can be at least 4.22× and 3.26× for steady‐state and transient simulations, respectively. Moreover, the speedup of Phone‐nomenon.LinMOR over Phone‐nomenon.Lin is at least 2.57×.
Chapter 8 focuses on timing closure, and its perspective is particularly unique. It offers a comprehensive coverage of timing analysis and relevant optimizations in placement, routing, and netlist restructuring. Timing-driven placement (Sect. 8.3) minimizes signal delays when assigning circuit elements to locations. Timing-driven routing (Sect. 8.4) minimizes signal delays when selecting routing topologies and specific routes. Physical synthesis (Sect. 8.5) improves timing by making changes to the netlist.
This chapter presents the background principles of multiport programmable optical processors which are a mesh of 2 × 2 reconfigurable Mach-Zehnder interferometers (MZIs) in different topologies. It demonstrates how the unitary transformation matrix of a given application is decomposed for programming such MZI-based optical processors. Additionally, a phase-error- and loss-tolerant MZI-based optical processor for optical neural networks (ONNs) is investigated. The structure has a diamond shape mesh with a set of additional MZIs compared to the commonly used Reck mesh. The additional MZIs in the Diamond mesh make its topology more symmetric yielding higher robustness to phase error and insertion loss of the MZIs, and provide extra degrees of freedom in the weight matrix optimization of the ONNs during training. The main subject of this chapter is to investigate such MZI-based optical processors, which allows for the design and implementation of more efficient and practical MZI-based optical processors that better cope with inevitable fabrication processes imperfections and experimental imperfections. The demonstration of these analyses is significant since it can be used to implement any universal MZI-based field-programmable structure to serve as optical computational accelerator, which can be experimentally configured for a given application.
Modern integrated circuit (IC) design and fabrication processes are both complex and expensive. In order to reduce the cost and improve efficiency, supply chains based on fabless design houses and pure-play foundries have evolved. Globalization of IC supply chains introduced several vulnerabilities which can be exploited by unscrupulous attackers. Split manufacturing (SM), originally introduced for yield enhancement, offers a defense to protect against some of these vulnerabilities. This chapter reviews typical IC design and fabrication processes and discusses various vulnerabilities in the globalized supply chains. We introduce 2D, 2.5D, and 3D split fabrication methods, their potential security benefits, and the design flows for each method. We discuss the basic issues and tradeoffs in SM and summarize several SM hardware demonstrations. We introduce potential attack scenarios against SM and discuss the objectives of the attackers. We classify the attacks based on the methods used and describe the assumptions made. The remaining chapters in this book discuss the proposed attacks and defense methods in detail.
Assembly and reliability of lead-free solder joints are very important topics in electronic manufacturing. There are many books [1–69] and papers [70–315] written on them. In this book, the assembly of lead-free solder joints such as prevailing lead-free materials, soldering processes, advanced specialty flux design, and characterization of lead-free solder joints will be discussed, respectively in Chaps. 2– 5. The reliability of lead-free solder joints such as reliability testing and data analyses, design for reliability, and failure analyses of lead-free solder joints will be discussed, respectively in Chaps. 6– 8. The special features of this book are the materials covered are not only for electronic manufacturing services (EMS) on the second-level interconnects, but also for packaging assembly on the first-level interconnects and for the semiconductor back-end on the 2.5D and 3D IC integration interconnects as shown in Fig. 1.1. The solder joints in various plated-through hole (PTH) and surface mount technology (SMT) printed circuit board (PCB) assemblies, and semiconductor packages will be discussed in this chapter.
After two decades of research effort, fine-pitched 3D integrated circuits are finally appearing in a growing range of industry products that leverage the benefits of high-bandwidth, high-density circuit integration. This article reflects on the historical development of these 3D technologies, their unique benefits over alternate 3D packaging methods, and the recent industry and research trends in 3D memories and 2.5D integration. Although die stacking is now happening, many potential benefits offered by these technologies remain to be explored, providing an opportunity for researchers and developers to solve these remaining challenges in architecture, methodology, and business.
Electromigration (EM) becomes a major reliability concern in 3-D integrated circuits (3-D ICs). To mitigate this problem, a typical solution is to use through-silicon via (TSV) redundancy in a reactive manner, maintaining the operability of a 3-D chip in the presence of EM failures by detecting and replacing faulty TSVs with spares. In this paper, we explore an alternative, more preferred approach to enhance the EM-related lifetime reliability of TSV grid, in which redundancy is used proactively to allow nonfaulty TSVs to be temporarily deactivated. In this way, EM wear-out can be extended by exploiting its recovery property. The proposed solution is based on two consecutive stages, in which TSV redundancy allocation and TSV repair are finalized at both design-time and runtime, respectively. Applied to 3-D benchmark designs, the recovery-aware proactive repair approach increases EM-related lifetime reliability (measured in mean-time-to-failure) of the entire TSV grid by up to $12x$ relative to the conventional reactive method, with similar area overhead. In addition, a runtime dynamic recovery approach is proposed to further improve EM-related lifetime reliability to account for stress variation across different chips and over the operational lifetime.
This book targets engineers and researchers familiar with basic computer architecture concepts who are interested in learning about on-chip networks. This work is designed to be a short synthesis of the most critical concepts in on-chip network design. It is a resource for both understanding on-chip network basics and for providing an overview of state of-the-art research in on-chip networks. We believe that an overview that teaches both fundamental concepts and highlights state-of-the-art designs will be of great value to both graduate students and industry engineers. While not an exhaustive text, we hope to illuminate fundamental concepts for the reader as well as identify trends and gaps in on-chip network research. With the rapid advances in this field, we felt it was timely to update and review the state of the art in this second edition. We introduce two new chapters at the end of the book. We have updated the latest research of the past years throughout the book and also expanded our coverage of fundamental concepts to include several research ideas that have now made their way into products and, in our opinion, should be textbook concepts that all on-chip network practitioners should know. For example, these fundamental concepts include message passing, multicast routing, and bubble flow control schemes.
This chapter is focused on the Design eco-system for realizing competitive high volume 2.5D and 3D SiP products. The die-to-die interactions precipitated by 2.5D and 3D SiP integration are highlighted, with emphases on modeling and proactive management of the Thermal and Mechanical Stress interactions. The gaps between the design methodology required for 2.5D and 3D SiPs and the current state of the art are outlined, and the possible practical shortcut solutions are proposed. The infrastructure requirements for technology characterization, including the idiosyncrasies of 2.5D and 3D Test Chip design and evaluation, as well as the special modeling needs for More-than-Moore technologies are also outlined.
The third dimension is becoming an attractive solution to integrate components in a single integrated circuit. Therefore, 3D Networks-on-Chip (NoCs) are usually adopted to provide fast connections between the layers by using Through-Silicon-Vias (TSVs). However, many challenges during the 3D manufacturing phase are making the circuits more vulnerable and prone to failure. This work investigates the impact on latency in 3D NoCs under multiple faulty TSVs and it proposes a technique to ensure the connectivity of the NoC under multiple faults scenario. A fault model was proposed with four different configurations to distribute multiple faulty TSVs in the 3D NoC. Three different fault tolerant scenarios were explored: the first is the original routing algorithm called Elevated-First used to avoid faulty vertical connections. The second and third scenarios are our new designs based on the use of dynamic monitors to observe the flow through the paths, in order to be able to select best alternative paths under multiple faults. Fault injection results show that it is possible to reduce the latency impact from 1x to 10x in the best case configuration by use the proposed solutions.
Physical limit of transistor miniaturization has driven chip design into the third dimension. 3D integration technology emerges as a viable option to improve chip performance and increase device density in a direction orthogonal to costly device scaling. As 3D integration is becoming a promising technology for next-generation chip design, recent years have seen a huge proliferation of research literature exploiting it from a security perspective. This paper presents a survey on the current state of 3D integration technology from a security perspective and summarizes its security opportunities and challenges. We report current research work on 3D integration based security in three major applications: supply chain attack prevention, side-channel attack mitigation, and trustworthy computing system design. The security advantages and opportunities of 3D integration in these security applications are highlighted. Besides, the paper discusses new vulnerabilities risen by 3D integration that require researchers' attention. Based on the survey result, we summarize the distinct characteristics of 3D ICs and investigate their impacts on security-aware 3D IC designs.
Die Leistungsparameter moderner elektronischer Systeme mit hoher Integrationsdichte werden wesentlich durch die im Betrieb entstehende Verlustleistung und die damit verbundenen Temperaturen begrenzt. Dementsprechend ist das Entstehen und Abführen von Verlustwärme bereits im Entwurf solcher Systeme auf allen Systemebenen zu berücksichtigen, d. h. sowohl beim Bauelemente-, Baugruppen- als auch Geräteentwurf. Dazu sind einerseits die zu erwartenden Temperaturen mit thermischen Modellen vorauszuberechnen, als auch andererseits optimale Anordnungen und Strukturen für den effektiven Wärmetransport auf allen Systemebenen zu entwickeln und in den Entwurf einzubeziehen. Dabei ist die Temperaturfeldberechnung die Lösung eines direkten Problems. Dagegen stellt der Entwurf von Anordnungen, die bestimmte thermische Randbedingungen einhalten, also z. B. bestimmte Grenztemperaturen nicht überschreiten, die wesentlich schwierigere Lösung inverser, im allgemeinen schlecht gestellter Probleme dar. Die zuletzt genannte Aufgabe lässt sich mit vertretbarem Aufwand in der Regel nur heuristisch lösen.
Three-dimensional (3D) integration is a promising alternative option to traditional two-dimensional (2D) planar chips. The 3D integration is mainly concerned with the communication infrastructure between different stacked dies of future multi-core system-on-chip (SoC) and network-on-chip (NoC). Among several 3D integration technologies, the through silicon via (TSV) approach is the most promising one and therefore is the focus of the majority of 3D integration R&D activities. However, there are challenges that should be overcome before the production of TSV-based 3D integrated circuits (ICs) becomes possible, e.g., electrical modeling challenges, thermal and power challenges, technological challenges, design methodology challenges, and computer-aided design (CAD) tool development challenges. The manufacturability of TSV-based 3D-ICs is an important issue for realizing real 3D-ICs designs.
3D integration is a promising and attractive solution for interconnect bottleneck problem, transistor scaling physical limitations, and impractical small-scale lithography. 3D integration extends Moore’s law in the third dimension, offering heterogeneous integration, higher density, lower power consumption, and faster performance. However, in order to fabricate 3D integrated circuits (ICs), new capabilities are needed: process technology, physical modeling, physical design tools, 3D architectures, design methods, and tools. The goal of this chapter is to cover the manufacturability of through silicon via (TSV)-based 3D-ICs, i.e., process technology and fabrication capability.
Moore’s law has inspired the growth of integrated circuit (IC) technology since its inception in 1965 [75]. Each new technology node produces smaller and faster devices keeping pace with Moore’s prediction of 2 ×scaling every 18 months. The exponential decrease in feature size, from 10 μm [87] to 22 nm [20] over the past four decades, has resulted in an astronomical performance increase. For this trend to continue, significant challenges need to be overcome in several key areas [74]. IC technology has evolved from a device-centric technology to one where interconnect also plays a critical role. The latency of interconnect dominates that of transistors [70]. Oxide thickness of a metal oxide semiconductor field effect transistor (MOSFET) determines the size and the leakage current of a transistor. Oxide thickness approaching atomic levels imposes a practical bound on the leakage current and hence limits transistor sizes [93, 105]. Exponential increase in capital cost, to set up a foundry, poses a threat to the viability of future technology scaling [26].
Previous chapters have described various aspects of 3D integration technology, including the fundamentals of process technology and EDA design flows for 3D IC design. In this chapter, we discuss how to leverage the emerging 3D integration technology for future microprocessor design.
IntroductionEquivalent Circuit Model for TSVMOS Capacitance Effect of TSVConclusion
References
The emerging three-dimensional (3D) chip architectures, with their intrinsic capability of reducing the wire length, is ne of the promising solutions to mitigate the interconnect problem in modern microprocessor designs. To leverage the benefits of fast latency, high bandwidth, and heterogeneous integration capability that are offered by 3D technology, new design methodologies should be developed targeting the unique feature of 3D integration. In this chapter, various approaches to model 3D electrical behavior, handle 3D thermal reliability problems, and design future 3D microprocessors are surveyed.
3D Integration is a promising and attractive solution for interconnect bottleneck problem, transistor scaling physical limitations, and impractical small-scale lithography. 3D integration extends Moore's law in the third dimension, offering heterogeneous integration, higher density, lower power consumption, and faster performance. However, in order to fabricate 3D ICs, new capabilities are needed: process technology, physical modeling, physical design tools, 3D architectures, design methods and tools. The goal of this paper is to cover the manufacturability of TSV-based 3D-ICs Le. process technology, and fabrication capability.
In this paper, based on the formulas of the classic theory of heat conduction, proposed a temperature distribution formula in the three-dimensional space, which can effectively and accurately calculated the temperature value at any coordinate-point within the TSV(Through Silicon Via) model. By simulating the behavior of heat conduction and analyzing temperature data, this paper proposed the simplified empirical formula of temperature distribution for analyzing in 3D IC, and compared the calculated value with the simulation value to validate. These results will be easy to estimate the range of temperature change for EDA toll.
This paper presents the design of tier-to-tier interface circuits for 3-D-ICs, where different tiers may operate at different voltages and/or frequencies. The design and partitioning methodologies for the tier-to-tier interface circuit are discussed. The footprint, power, and performance of the interface are analyzed considering the effects of tier-to-tier process variations in 3-D-ICs and technology scaling. The simulation results show that dividing the interface circuit evenly between two tiers reduces footprint but increases power dissipation. For heterogeneous systems with different voltages for reading and writing tiers, dividing the interface between tiers provides better performance than the worst case scenario. On the other hand, placing the interface circuit in the reading tier maximizes throughput for a homogeneous system where both tiers operate at the same voltage. In advanced CMOS nodes, placing interface circuit in the reading tier is a better option due to high delay of the level shifters.
We experimentally demonstrate a three-dimensional x-ray ptychography in combination with precession measurements that can reconstruct multisection images of optically thick objects. We collect a tilt-series ptychographic diffraction data set of a four-layered object and then successfully reconstruct the phase images of each layer by using an improved phase retrieval algorithm with a multislice approach. The present method has great potential for nondestructively determining anisotropic structures in materials science and biology.
Recently, Through-Silicon-Via (TSV) has been more popular to provide faster inter-layer communication in three-dimensional Networks-on-Chip (3D NoCs). However, the area overhead of TSVs reduces wafer utilization and yield which impact design of 3D architectures using a large number of TSVs such as homogeneous 3D NoCs topologies. Also, 3D routers require more memory and thus they are more power hungry than conventional 2D routers. Alternatively, hybrid 3D NoCs combine both the area and performance benefits of 2D and 3D router architectures by using a limited number of TSVs. Existing hybrid architectures suffer from higher packet delays as they do not consider the dynamic communication patterns of different application and their NoC resource usage. We propose a novel algorithm to systematically generate hybrid 3D NoC topologies for a given application such that the vertical connections are minimized while the NoC performance is not sacrificed. The proposed algorithm analyses the target application and generates hybrid architectures by efficiently redistributing the vertical links and buffer spaces based on their utilizations. Furthermore, the algorithm has been evaluated with synthetic and various real-world traffic patterns. Experimental results show that the proposed algorithm generates optimized architectures with lower energy consumption and a significant reduction in packet delay compared to the existing solutions.
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