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Aspects of low-power high-speed CMOS VLSI design: A review
Abstract
VLSI and nanocomputing has become the most desirable feature of any integrated chip. Computers are also becoming more portable. ICs are being introduced everywhere. This huge implementation of IC has also opened a scope of research. Size of IC has become an issue to think about. Power dissipation is also another important consideration as performance of VLSI chip design. Low-power high-speed CMOS circuit design methodologies will be elaborated in this paper.
... For any input over the input terminals A, B, and C, the ALU performs arithmetic and logical operations depending on the input given over the select line. The 8-bit ALU is obtained by cascading all 1-Bit ALU's [18]- [20]. The above block diagram shows the cascaded form of all 1-Bit ALU's. ...
ince last few years, the tiny size of MOSFET, that is less than tens of nanometers, created some operational problems such as increased gate-oxide leakage, amplified junction leakage, high sub-threshold conduction, and reduced output resistance. To overcome the above challenges, FinFET has the advantages of an increase in the operating speed, reduced power consumption, decreased static leakage current is used to realize the majority of the applications by replacing MOSFET. By considering the attractive features of the FinFET, an ALU is designed as an application. In the digital processor, the arithmetic and logical operations are executed using the Arithmetic logic unit (ALU). In this paper, power efficient 8-bit ALU is designed with Full adder (FA) and multiplexers composed of Gate diffusion input (GDI) which gained designer's choice for digital combinational circuit realization at minimum power consumption. The design is simulated using Cadence virtuoso with 20nm technology. Comparative performance analysis is carried out in contrast to the other standard circuits by taking the critical performance metrics such as delay, power, and power delay product (PDP), energy-delay product (EDP) metrics into consideration.
In this paper, we describe a new approach to reduce dynamic power, leakage, and area of application-specified integrated circuits, without sacrificing performance. The approach is based on a design of threshold logic gates (TLGs) and their seamless integration with conventional standard-cell design flow. We first describe a new robust, standard-cell library of configurable circuits for implementing threshold functions. Abstractly, the threshold gate behaves as a multi-input, single-output, edge-triggered flip-flop, which computes a threshold function of the inputs on the clock edge. The library consists of a small number of cells, each of which can compute a set of complex threshold functions, which would otherwise require a multilevel network. The function realized by a given threshold gate is determined by how signals are mapped to its inputs. We present a method for the assignment of signals to the inputs of a threshold gate to realize a given threshold function. Next, we present an algorithm that replaces a subset of flip-flops and portions of their logic cones in a conventional logic netlist, with threshold gates from the library. The resulting circuits, with both conventional and TLGs (called hybrid circuits), are placed and routed using commercial tools. We demonstrate significant reductions (using postlayout simulations) in power, leakage, and area of the hybrid circuits when compared with the conventional logic circuits, when both are operated at the maximum possible frequency of the conventional design.
This paper presents a low voltage and high performance 1-bit full adder designed with an efficient internal logic structure that leads to have a reduced Power Delay Product (PDP). The modified NOR and NAND gates, an essential entity, are also presented. The circuit is designed with cadence virtuoso tool with UMC 90-nm and 55-nm CMOS technologies. The proposed adder is compared with some of the popular adders based on power consumption, speed and power delay product. The proposed full adder cells achieve 56% and 76.69% improvement in speed and power delay product metric when compared with conventional C-CMOS full adder. It is also found that the proposed adder cells exhibit excellent signal integrity and driving capability when operated at low voltages.
Power consumption plays a major role in present day VLSI design technology. The demand for low power consuming devices is increasing rapidly and the adiabatic logic style is said to be an attractive solution. This paper investigates different methods for designing adiabatic logics such as CMOS adiabatic circuits, ECRL, PFAL, CAL, DFAL, 2N-2P and 2N-2N2P. A lot of research has been already done using adiabatic technique. This paper presents a review of above mentioned adiabatic inverters in literature from basic elements. The SPICE simulation results show the comparison of power dissipation between conventional CMOS circuits and adiabatic logic based circuits.
The inverter is known to be the nucleus of all digital designs. Evolutionary computation may be a competent implement for automatic design of digital integrated circuits (IC). In this paper, optimal switching characteristics of a CMOS inverter are realized using an evolutionary optimization approach called Differential Evolution (DE) algorithm. The Real coded genetic algorithm (RGA) and particle swarm optimization (PSO) have been adopted for the sake of comparison. DE based design results have been compared also with those of the PSPICE results. The comparative simulation results establish the DE as a more competent candidate to other aforementioned evolutionary algorithms in terms of accuracy and convergence speed.
In this paper, we present a solution to the ultra low voltage inverter by adding a keeper transistor in order to make the semi-floating-gate more stable and to reduce the current dissipation. Moreover, we also present a differential ULV inverter and elaborate on the reliability and fault tolerance of the gate. The differential ULV gate compared to both a former ULV gate and standard CMOS are given. The results are obtained through Monte-Carlo simulations.
The parasitic capacitance in the dynamic node increases for wide tag comparator increasing the delay and power consumption. The output signal may also degrade with high performance computing that uses clock frequency over 1 GHz. In this paper a circuit is proposed to reduce the delay of the evaluation phase of the 64 bit tag comparator by reducing the parasitic capacitance at the dynamic node. The circuit is applicable for wide fan-in gates. The performance has enhanced by 60-70% with reduced leakage providing reduced voltage degradation of the output signal when compared to the rest of the dynamic circuit under study. The Mentor Graphics tool kit is used to perform pre-layout simulations, circuit layout generation and physical verification of the layout.
Dynamic power estimation is essential in designing VLSI circuits where many parameters are involved but the only circuit parameter that is related to the circuit operation is the nodes’ toggle rate. This paper discusses a deterministic and fast method to estimate the dynamic power consumption for CMOS combinational logic circuits using gate-level descriptions based on the Logic Pictures concept to obtain the circuit nodes’ toggle rate. The delay model for the logic gates is the real-delay model. To validate the results, the method is applied to several circuits and compared against exhaustive, as well as Monte Carlo, simulations. The proposed technique was shown to save up to 96% processing time compared to exhaustive simulation.
In this paper, a novel power consumption reduction strategy (PCRS) using mixed-VTH (MVT) cells with unbalanced timing arcs (UTA) for low-voltage/low-power SOC applications is presented. Via selecting the fastest timing arc for the critical path- MVT cell variant selection (CVS) criteria and adopting cell assignment algorithm (CAA) to integrate MVT cells out of the HVT/LVT/MVT pool for the circuit optimization flow, the PCRS provides a low-voltage/low-power SOC design as indicated in a 16-bit multiplier with 5584 cells, using a 90 nm CMOS technology at 1 V under the tightest delay constraint with a 5.15% reduction in power consumption as compared to the one optimized by the CBLPRP technique.
In the recent past, Mesh-based clock distribution has received interest due to their tolerance to process variations in deep-sub micron technology. Mesh buffers are placed on the mesh to drive the large load capacitance of clock sinks and mesh wire capacitance. In this paper, we propose a buffer placement algorithm which can overcome the short circuit power dissipated in clock meshes. Our buffer placement algorithm uses clustering technique to judiciously place buffers such that short-circuit power is minimized while minimizing skew at the same time. This is verified by Monte carlo simulations incorporating process, voltage and systemic variations in NGSPICE.
In this paper we propose a novel design of a low power static random access memory (SRAM) cell for high speed operations. The model adopts the voltage mode method for reducing the voltage swing during the write operation switching activity. Dynamic power dissipation increases when the operating frequency of the SRAM cell increases. In the proposed design we use two voltage sources connected with the Bit line and Bit bar line for reducing the voltage swing during the write “0” or write “1” operation. We use 90 nm CMOS technology with 1 volt of power supply. Simulation is done in Microwind 3.1 by using BSim4 model. Dynamic power for different frequencies is calculated. We compare it with conventional 6-T SRAM cell. The simulation results show that the power dissipation is almost constant even the frequency of the proposed SRAM model increases. This justifies the reduction of the dynamic power dissipation for high frequency CMOS VLSI design.
Ubiquitous computing is a next generation information technology where computers and communications will be scaled further, merged together, and materialized in consumer applications. Computers will be invisible behind broadband networks as servers, while terminals will come closer to us as wearable/implantable devices, more friendly devices with sophisticated human-computer interactions. IC chips will be implanted everywhere so that things can think and talk for distributed information processing. Key technologies here are low power, low cost, and good interfaces, especially for wireless data communications. Low-power, high-speed CMOS circuit techniques are presented in this paper, including low-voltage design with variable/multiple V<sub>DD</sub>/V<sub>TH</sub> control, embedded memory technology for reducing capacitance, and low-switching activity design.