ChapterPDF Available

Bandpass Sigma Delta A-D Conversion

Authors:

Abstract

Modern high performance radio systems increasingly rely on digital signal processing techniques. In many cases performance is limited by the A-D conversion process, particularly where high linearity is required. In this paper three examples are presented of bandpass sigma-delta A-D converters which offer a cost effective means of encoding narrowband IF signals to a high linearity and with low spurious content.
Article
In recent years, automatic diagnosis of the state of health of the heart by employing phonocardiogram has achieved remarkable success. This paper proposes a low complexity automated solution based on the direct application of a multiclass CNN to PCG signals for the purpose of recognizing and classifying heart disease. PCG signals are fed in to the neural network, bypassing transformations from the time domain to that of frequencies (for example MFCC, Wavelet, etc.). Applying a recurrence filter in the post-processing phase, the proposed method allows to increase performance in a range from 90% to 100%, with an analysis time of less than 14 seconds. The paper also proposes an analysis of the robustness of the proposed technique to environmental noise.
Chapter
This chapter focuses on specific system-level simulations of the simplest Sigma-Delta modulator, to be referred as MOD1, formed by a first-order loop filter and a single-bit quantizer. The aim of this chapter is to help beginners make the important leap from theory to actually understand the significance of the subtle concepts that are essential to becoming confident in designing a successful modulator. As mentioned, MATLAB® and Simulink® are the tools used to explore the properties of MOD1. Therefore, after a brief description of the Simulink® model provided in the Toolbox accompanying this book, a step-by-step set of practical exercises is proposed. Specifically, the reader will be able to observe the time domain waveforms of the modulator in response to both DC and sinewave inputs as well as noise shaping in the frequency domain via fast Fourier transform (FFT). A number of non-ideal effects are studied such as tones, dead zones, and saturation. Further, the prevention of the non-idealities discussed is investigated, mainly through the use of dither. Some simple mathematics is used as an aid in presenting the theoretical concepts, and for results evaluation, however, formula proofs are generally avoided in order to keep the focus on the results themselves and a rather practical approach to the subject. The interested reader is encouraged to consult the references for complete mathematical derivations.
Chapter
This chapter focuses on specific system-level simulations of the second-order Sigma-Delta modulator, to be referred as MOD2, formed by a second-order loop filter and a single-bit quantizer. Similarly to Chap. 2, the aim is to gain a significant appreciation of the practical aspects needed during the design process. Therefore, the operation for DC and sinewave inputs as well as the non-idealities affecting the modulator behavior will be studied by performing the practical exercises suggested in the MATLAB® and Simulink® environment. Since the chapter follows almost exactly the sequence of simulations conducted for MOD1, the reader is encouraged to make frequent comparisons between the performance of MOD1 and MOD2 in order to gain a better understanding of the concepts covered. Moreover, in Sect. 3.7 a comprehensive investigation on the theory underlying alternative architectures is presented, as well as suggestions on the simulations to conduct on those modulator structures.
Chapter
An implementation procedure for continuous time bandpass ΔΣ modulators as a fully integrated circuit is discussed. An overview is given of the synthesis theory. A methodology for the filter design yielding practical design equations is explained. A topology for the loop filters is proposed: they are Gm-C filters. The specifications of the various building block are discussed. Considerable attention is given to non-idealities such as circuit noise, finite Q-factor and non-linearity of the transconductance amplifiers, which affect the performance of the modulator. Circuit realizations are discussed.
Chapter
From the experiences made one can easily extrapolate that the foreseeable mobile communications market as well as the communications devices will allow for heterogeneous plurality, i.e. there will be no common standard. At least today’s standards will continue as new standards are introduced. Different operators will deploy different standards in different areas of the world, always in order to try to exploit the forces of market to their own profit. We cannot expect a unification of the mobile communications market organized by the network operators. On the other hand there is a demand for unification of the mobile communications market from the equipment manufacturer’s and user’s point-of-view. In the future few users of mobile communications services will accept to carry dedicated terminals for different services in different networks. Moreover, the equipment manufacturers can reduce the cost of their products by unifying the hardware platform.
Conference Paper
Full-text available
This paper presents a fourth-order bandpass sigma-delta modulator that has been designed using fully-differential switched-current circuits in a 0.8 μm CMOS technology. The modulator prototype has been obtained by applying a lowpass to bandpass transformation (z<sup>-1 </sup>->-z<sup>-2</sup>) to a second-order lowpass ΣΔ modulator. Specifications are SNR&ges;60dB@2.5MHz±15kHz, for a clock frequency of 10 MHz. Preliminary results from the fabricated prototype obtains the correct noise shaping up to 2.5 MHz clock frequency
Conference Paper
Full-text available
We present a fourth-order bandpass ΣΔ switched-current modulator IC in 0.8 μm CMOS single-poly technology. Its architecture is obtained by applying a lowpass to bandpass transformation (z<sup>-1 </sup>→-z<sup>-2</sup>) to a second-order lowpass modulator. It has been realized using fully-differential circuitry with common-mode feedback. Measurements show 8 bit dynamic range up to 5 MHz clock frequency and 10 KHz bandwidth
Article
A digital method of stabilising higher order sigma-delta converters is presented. Results are given for a third order bandpass ΣΔ converter with three continuous time LC filters tuned to 1/4 of clock frequency f<sub>c</sub>
Article
Delta-sigma (ΔΣ) modulators employing continuous-time elements can be transformed to equivalent discrete-time systems. The paper derives this equivalence relation and applies it to the design of a third-order low-pass modulator and a sixth-order band-pass modulator
Conference Paper
Full-text available
A new design of band-pass sigma-delta A-D converter is presented which can encode the signal at the intermediate frequency and then by digital post processing convert to baseband I and Q. The technique of band-pass sigma-delta conversion is described and a method for designing band-pass A-D converters from existing baseband modulator designs is given with an example to illustrate the theory. Practical results are described with the performance specified in conventional RF circuit terms
Conference Paper
Discusses the assessment of digital receiver performance by FFT analysis taking account of receiver architecture and analogue to digital converter behaviour. Results of such measurements on a prototype high performance digitally implemented HF receiver are presented by way of example
Article
A complete monolithic stereo 16-bit D/A converter primarily intended for use in compact-disc players and digital audio tape recorders is described. The D/A converter achieves 16-bit resolution by using a code-conversion technique based upon oversampling and noise shaping. The band-limiting filters required for waveform smoothing and out-of-band noise reduction are included. Owing to the oversampling principle most applications will require only a few components for an analog postfilter. The converter has a linear characteristic and linear phase response. The chip is processed in a 2-μm CMOS process and the die size is 44 mm/SUP 2/. Only a single 5-V supply is needed.
Analogue to Digital HF Radio Receivers”, IEE Colloquium on Systems Aspects and Applications of ADC’s for Radar, Sonar and Communications
  • T H Pearce
  • A C Baker